diff --git a/ESP32-IDF_ESPNOW-Receiver/build/.ninja_deps b/ESP32-IDF_ESPNOW-Receiver/build/.ninja_deps
index c0ee3c3f0..8c3a74f4e 100644
Binary files a/ESP32-IDF_ESPNOW-Receiver/build/.ninja_deps and b/ESP32-IDF_ESPNOW-Receiver/build/.ninja_deps differ
diff --git a/ESP32-IDF_ESPNOW-Receiver/build/.ninja_log b/ESP32-IDF_ESPNOW-Receiver/build/.ninja_log
index 0cab85609..5ef5dfbfe 100644
--- a/ESP32-IDF_ESPNOW-Receiver/build/.ninja_log
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+# define SIMULATE_ID "GNU"
+#endif
+/* __INTEL_LLVM_COMPILER = VVVVRP prior to 2021.2.0, VVVVRRPP for 2021.2.0 and
+ * later.  Look for 6 digit vs. 8 digit version number to decide encoding.
+ * VVVV is no smaller than the current year when a version is released.
+ */
+#if __INTEL_LLVM_COMPILER < 1000000L
+# define COMPILER_VERSION_MAJOR DEC(__INTEL_LLVM_COMPILER/100)
+# define COMPILER_VERSION_MINOR DEC(__INTEL_LLVM_COMPILER/10 % 10)
+# define COMPILER_VERSION_PATCH DEC(__INTEL_LLVM_COMPILER    % 10)
+#else
+# define COMPILER_VERSION_MAJOR DEC(__INTEL_LLVM_COMPILER/10000)
+# define COMPILER_VERSION_MINOR DEC(__INTEL_LLVM_COMPILER/100 % 100)
+# define COMPILER_VERSION_PATCH DEC(__INTEL_LLVM_COMPILER     % 100)
+#endif
+#if defined(_MSC_VER)
+  /* _MSC_VER = VVRR */
+# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100)
+# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100)
+#endif
+#if defined(__GNUC__)
+# define SIMULATE_VERSION_MAJOR DEC(__GNUC__)
+#elif defined(__GNUG__)
+# define SIMULATE_VERSION_MAJOR DEC(__GNUG__)
+#endif
+#if defined(__GNUC_MINOR__)
+# define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__)
+#endif
+#if defined(__GNUC_PATCHLEVEL__)
+# define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__)
+#endif
+
+#elif defined(__PATHCC__)
+# define COMPILER_ID "PathScale"
+# define COMPILER_VERSION_MAJOR DEC(__PATHCC__)
+# define COMPILER_VERSION_MINOR DEC(__PATHCC_MINOR__)
+# if defined(__PATHCC_PATCHLEVEL__)
+#  define COMPILER_VERSION_PATCH DEC(__PATHCC_PATCHLEVEL__)
+# endif
+
+#elif defined(__BORLANDC__) && defined(__CODEGEARC_VERSION__)
+# define COMPILER_ID "Embarcadero"
+# define COMPILER_VERSION_MAJOR HEX(__CODEGEARC_VERSION__>>24 & 0x00FF)
+# define COMPILER_VERSION_MINOR HEX(__CODEGEARC_VERSION__>>16 & 0x00FF)
+# define COMPILER_VERSION_PATCH DEC(__CODEGEARC_VERSION__     & 0xFFFF)
+
+#elif defined(__BORLANDC__)
+# define COMPILER_ID "Borland"
+  /* __BORLANDC__ = 0xVRR */
+# define COMPILER_VERSION_MAJOR HEX(__BORLANDC__>>8)
+# define COMPILER_VERSION_MINOR HEX(__BORLANDC__ & 0xFF)
+
+#elif defined(__WATCOMC__) && __WATCOMC__ < 1200
+# define COMPILER_ID "Watcom"
+   /* __WATCOMC__ = VVRR */
+# define COMPILER_VERSION_MAJOR DEC(__WATCOMC__ / 100)
+# define COMPILER_VERSION_MINOR DEC((__WATCOMC__ / 10) % 10)
+# if (__WATCOMC__ % 10) > 0
+#  define COMPILER_VERSION_PATCH DEC(__WATCOMC__ % 10)
+# endif
+
+#elif defined(__WATCOMC__)
+# define COMPILER_ID "OpenWatcom"
+   /* __WATCOMC__ = VVRP + 1100 */
+# define COMPILER_VERSION_MAJOR DEC((__WATCOMC__ - 1100) / 100)
+# define COMPILER_VERSION_MINOR DEC((__WATCOMC__ / 10) % 10)
+# if (__WATCOMC__ % 10) > 0
+#  define COMPILER_VERSION_PATCH DEC(__WATCOMC__ % 10)
+# endif
+
+#elif defined(__SUNPRO_C)
+# define COMPILER_ID "SunPro"
+# if __SUNPRO_C >= 0x5100
+   /* __SUNPRO_C = 0xVRRP */
+#  define COMPILER_VERSION_MAJOR HEX(__SUNPRO_C>>12)
+#  define COMPILER_VERSION_MINOR HEX(__SUNPRO_C>>4 & 0xFF)
+#  define COMPILER_VERSION_PATCH HEX(__SUNPRO_C    & 0xF)
+# else
+   /* __SUNPRO_CC = 0xVRP */
+#  define COMPILER_VERSION_MAJOR HEX(__SUNPRO_C>>8)
+#  define COMPILER_VERSION_MINOR HEX(__SUNPRO_C>>4 & 0xF)
+#  define COMPILER_VERSION_PATCH HEX(__SUNPRO_C    & 0xF)
+# endif
+
+#elif defined(__HP_cc)
+# define COMPILER_ID "HP"
+  /* __HP_cc = VVRRPP */
+# define COMPILER_VERSION_MAJOR DEC(__HP_cc/10000)
+# define COMPILER_VERSION_MINOR DEC(__HP_cc/100 % 100)
+# define COMPILER_VERSION_PATCH DEC(__HP_cc     % 100)
+
+#elif defined(__DECC)
+# define COMPILER_ID "Compaq"
+  /* __DECC_VER = VVRRTPPPP */
+# define COMPILER_VERSION_MAJOR DEC(__DECC_VER/10000000)
+# define COMPILER_VERSION_MINOR DEC(__DECC_VER/100000  % 100)
+# define COMPILER_VERSION_PATCH DEC(__DECC_VER         % 10000)
+
+#elif defined(__IBMC__) && defined(__COMPILER_VER__)
+# define COMPILER_ID "zOS"
+  /* __IBMC__ = VRP */
+# define COMPILER_VERSION_MAJOR DEC(__IBMC__/100)
+# define COMPILER_VERSION_MINOR DEC(__IBMC__/10 % 10)
+# define COMPILER_VERSION_PATCH DEC(__IBMC__    % 10)
+
+#elif defined(__open_xl__) && defined(__clang__)
+# define COMPILER_ID "IBMClang"
+# define COMPILER_VERSION_MAJOR DEC(__open_xl_version__)
+# define COMPILER_VERSION_MINOR DEC(__open_xl_release__)
+# define COMPILER_VERSION_PATCH DEC(__open_xl_modification__)
+# define COMPILER_VERSION_TWEAK DEC(__open_xl_ptf_fix_level__)
+
+
+#elif defined(__ibmxl__) && defined(__clang__)
+# define COMPILER_ID "XLClang"
+# define COMPILER_VERSION_MAJOR DEC(__ibmxl_version__)
+# define COMPILER_VERSION_MINOR DEC(__ibmxl_release__)
+# define COMPILER_VERSION_PATCH DEC(__ibmxl_modification__)
+# define COMPILER_VERSION_TWEAK DEC(__ibmxl_ptf_fix_level__)
+
+
+#elif defined(__IBMC__) && !defined(__COMPILER_VER__) && __IBMC__ >= 800
+# define COMPILER_ID "XL"
+  /* __IBMC__ = VRP */
+# define COMPILER_VERSION_MAJOR DEC(__IBMC__/100)
+# define COMPILER_VERSION_MINOR DEC(__IBMC__/10 % 10)
+# define COMPILER_VERSION_PATCH DEC(__IBMC__    % 10)
+
+#elif defined(__IBMC__) && !defined(__COMPILER_VER__) && __IBMC__ < 800
+# define COMPILER_ID "VisualAge"
+  /* __IBMC__ = VRP */
+# define COMPILER_VERSION_MAJOR DEC(__IBMC__/100)
+# define COMPILER_VERSION_MINOR DEC(__IBMC__/10 % 10)
+# define COMPILER_VERSION_PATCH DEC(__IBMC__    % 10)
+
+#elif defined(__NVCOMPILER)
+# define COMPILER_ID "NVHPC"
+# define COMPILER_VERSION_MAJOR DEC(__NVCOMPILER_MAJOR__)
+# define COMPILER_VERSION_MINOR DEC(__NVCOMPILER_MINOR__)
+# if defined(__NVCOMPILER_PATCHLEVEL__)
+#  define COMPILER_VERSION_PATCH DEC(__NVCOMPILER_PATCHLEVEL__)
+# endif
+
+#elif defined(__PGI)
+# define COMPILER_ID "PGI"
+# define COMPILER_VERSION_MAJOR DEC(__PGIC__)
+# define COMPILER_VERSION_MINOR DEC(__PGIC_MINOR__)
+# if defined(__PGIC_PATCHLEVEL__)
+#  define COMPILER_VERSION_PATCH DEC(__PGIC_PATCHLEVEL__)
+# endif
+
+#elif defined(__clang__) && defined(__cray__)
+# define COMPILER_ID "CrayClang"
+# define COMPILER_VERSION_MAJOR DEC(__cray_major__)
+# define COMPILER_VERSION_MINOR DEC(__cray_minor__)
+# define COMPILER_VERSION_PATCH DEC(__cray_patchlevel__)
+# define COMPILER_VERSION_INTERNAL_STR __clang_version__
+
+
+#elif defined(_CRAYC)
+# define COMPILER_ID "Cray"
+# define COMPILER_VERSION_MAJOR DEC(_RELEASE_MAJOR)
+# define COMPILER_VERSION_MINOR DEC(_RELEASE_MINOR)
+
+#elif defined(__TI_COMPILER_VERSION__)
+# define COMPILER_ID "TI"
+  /* __TI_COMPILER_VERSION__ = VVVRRRPPP */
+# define COMPILER_VERSION_MAJOR DEC(__TI_COMPILER_VERSION__/1000000)
+# define COMPILER_VERSION_MINOR DEC(__TI_COMPILER_VERSION__/1000   % 1000)
+# define COMPILER_VERSION_PATCH DEC(__TI_COMPILER_VERSION__        % 1000)
+
+#elif defined(__CLANG_FUJITSU)
+# define COMPILER_ID "FujitsuClang"
+# define COMPILER_VERSION_MAJOR DEC(__FCC_major__)
+# define COMPILER_VERSION_MINOR DEC(__FCC_minor__)
+# define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__)
+# define COMPILER_VERSION_INTERNAL_STR __clang_version__
+
+
+#elif defined(__FUJITSU)
+# define COMPILER_ID "Fujitsu"
+# if defined(__FCC_version__)
+#   define COMPILER_VERSION __FCC_version__
+# elif defined(__FCC_major__)
+#   define COMPILER_VERSION_MAJOR DEC(__FCC_major__)
+#   define COMPILER_VERSION_MINOR DEC(__FCC_minor__)
+#   define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__)
+# endif
+# if defined(__fcc_version)
+#   define COMPILER_VERSION_INTERNAL DEC(__fcc_version)
+# elif defined(__FCC_VERSION)
+#   define COMPILER_VERSION_INTERNAL DEC(__FCC_VERSION)
+# endif
+
+
+#elif defined(__ghs__)
+# define COMPILER_ID "GHS"
+/* __GHS_VERSION_NUMBER = VVVVRP */
+# ifdef __GHS_VERSION_NUMBER
+# define COMPILER_VERSION_MAJOR DEC(__GHS_VERSION_NUMBER / 100)
+# define COMPILER_VERSION_MINOR DEC(__GHS_VERSION_NUMBER / 10 % 10)
+# define COMPILER_VERSION_PATCH DEC(__GHS_VERSION_NUMBER      % 10)
+# endif
+
+#elif defined(__TASKING__)
+# define COMPILER_ID "Tasking"
+  # define COMPILER_VERSION_MAJOR DEC(__VERSION__/1000)
+  # define COMPILER_VERSION_MINOR DEC(__VERSION__ % 100)
+# define COMPILER_VERSION_INTERNAL DEC(__VERSION__)
+
+#elif defined(__ORANGEC__)
+# define COMPILER_ID "OrangeC"
+# define COMPILER_VERSION_MAJOR DEC(__ORANGEC_MAJOR__)
+# define COMPILER_VERSION_MINOR DEC(__ORANGEC_MINOR__)
+# define COMPILER_VERSION_PATCH DEC(__ORANGEC_PATCHLEVEL__)
+
+#elif defined(__TINYC__)
+# define COMPILER_ID "TinyCC"
+
+#elif defined(__BCC__)
+# define COMPILER_ID "Bruce"
+
+#elif defined(__SCO_VERSION__)
+# define COMPILER_ID "SCO"
+
+#elif defined(__ARMCC_VERSION) && !defined(__clang__)
+# define COMPILER_ID "ARMCC"
+#if __ARMCC_VERSION >= 1000000
+  /* __ARMCC_VERSION = VRRPPPP */
+  # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/1000000)
+  # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 100)
+  # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION     % 10000)
+#else
+  /* __ARMCC_VERSION = VRPPPP */
+  # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/100000)
+  # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 10)
+  # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION    % 10000)
+#endif
+
+
+#elif defined(__clang__) && defined(__apple_build_version__)
+# define COMPILER_ID "AppleClang"
+# if defined(_MSC_VER)
+#  define SIMULATE_ID "MSVC"
+# endif
+# define COMPILER_VERSION_MAJOR DEC(__clang_major__)
+# define COMPILER_VERSION_MINOR DEC(__clang_minor__)
+# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__)
+# if defined(_MSC_VER)
+   /* _MSC_VER = VVRR */
+#  define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100)
+#  define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100)
+# endif
+# define COMPILER_VERSION_TWEAK DEC(__apple_build_version__)
+
+#elif defined(__clang__) && defined(__ARMCOMPILER_VERSION)
+# define COMPILER_ID "ARMClang"
+  # define COMPILER_VERSION_MAJOR DEC(__ARMCOMPILER_VERSION/1000000)
+  # define COMPILER_VERSION_MINOR DEC(__ARMCOMPILER_VERSION/10000 % 100)
+  # define COMPILER_VERSION_PATCH DEC(__ARMCOMPILER_VERSION/100   % 100)
+# define COMPILER_VERSION_INTERNAL DEC(__ARMCOMPILER_VERSION)
+
+#elif defined(__clang__) && defined(__ti__)
+# define COMPILER_ID "TIClang"
+  # define COMPILER_VERSION_MAJOR DEC(__ti_major__)
+  # define COMPILER_VERSION_MINOR DEC(__ti_minor__)
+  # define COMPILER_VERSION_PATCH DEC(__ti_patchlevel__)
+# define COMPILER_VERSION_INTERNAL DEC(__ti_version__)
+
+#elif defined(__clang__)
+# define COMPILER_ID "Clang"
+# if defined(_MSC_VER)
+#  define SIMULATE_ID "MSVC"
+# endif
+# define COMPILER_VERSION_MAJOR DEC(__clang_major__)
+# define COMPILER_VERSION_MINOR DEC(__clang_minor__)
+# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__)
+# if defined(_MSC_VER)
+   /* _MSC_VER = VVRR */
+#  define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100)
+#  define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100)
+# endif
+
+#elif defined(__LCC__) && (defined(__GNUC__) || defined(__GNUG__) || defined(__MCST__))
+# define COMPILER_ID "LCC"
+# define COMPILER_VERSION_MAJOR DEC(__LCC__ / 100)
+# define COMPILER_VERSION_MINOR DEC(__LCC__ % 100)
+# if defined(__LCC_MINOR__)
+#  define COMPILER_VERSION_PATCH DEC(__LCC_MINOR__)
+# endif
+# if defined(__GNUC__) && defined(__GNUC_MINOR__)
+#  define SIMULATE_ID "GNU"
+#  define SIMULATE_VERSION_MAJOR DEC(__GNUC__)
+#  define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__)
+#  if defined(__GNUC_PATCHLEVEL__)
+#   define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__)
+#  endif
+# endif
+
+#elif defined(__GNUC__)
+# define COMPILER_ID "GNU"
+# define COMPILER_VERSION_MAJOR DEC(__GNUC__)
+# if defined(__GNUC_MINOR__)
+#  define COMPILER_VERSION_MINOR DEC(__GNUC_MINOR__)
+# endif
+# if defined(__GNUC_PATCHLEVEL__)
+#  define COMPILER_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__)
+# endif
+
+#elif defined(_MSC_VER)
+# define COMPILER_ID "MSVC"
+  /* _MSC_VER = VVRR */
+# define COMPILER_VERSION_MAJOR DEC(_MSC_VER / 100)
+# define COMPILER_VERSION_MINOR DEC(_MSC_VER % 100)
+# if defined(_MSC_FULL_VER)
+#  if _MSC_VER >= 1400
+    /* _MSC_FULL_VER = VVRRPPPPP */
+#   define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 100000)
+#  else
+    /* _MSC_FULL_VER = VVRRPPPP */
+#   define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 10000)
+#  endif
+# endif
+# if defined(_MSC_BUILD)
+#  define COMPILER_VERSION_TWEAK DEC(_MSC_BUILD)
+# endif
+
+#elif defined(_ADI_COMPILER)
+# define COMPILER_ID "ADSP"
+#if defined(__VERSIONNUM__)
+  /* __VERSIONNUM__ = 0xVVRRPPTT */
+#  define COMPILER_VERSION_MAJOR DEC(__VERSIONNUM__ >> 24 & 0xFF)
+#  define COMPILER_VERSION_MINOR DEC(__VERSIONNUM__ >> 16 & 0xFF)
+#  define COMPILER_VERSION_PATCH DEC(__VERSIONNUM__ >> 8 & 0xFF)
+#  define COMPILER_VERSION_TWEAK DEC(__VERSIONNUM__ & 0xFF)
+#endif
+
+#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)
+# define COMPILER_ID "IAR"
+# if defined(__VER__) && defined(__ICCARM__)
+#  define COMPILER_VERSION_MAJOR DEC((__VER__) / 1000000)
+#  define COMPILER_VERSION_MINOR DEC(((__VER__) / 1000) % 1000)
+#  define COMPILER_VERSION_PATCH DEC((__VER__) % 1000)
+#  define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__)
+# elif defined(__VER__) && (defined(__ICCAVR__) || defined(__ICCRX__) || defined(__ICCRH850__) || defined(__ICCRL78__) || defined(__ICC430__) || defined(__ICCRISCV__) || defined(__ICCV850__) || defined(__ICC8051__) || defined(__ICCSTM8__))
+#  define COMPILER_VERSION_MAJOR DEC((__VER__) / 100)
+#  define COMPILER_VERSION_MINOR DEC((__VER__) - (((__VER__) / 100)*100))
+#  define COMPILER_VERSION_PATCH DEC(__SUBVERSION__)
+#  define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__)
+# endif
+
+#elif defined(__SDCC_VERSION_MAJOR) || defined(SDCC)
+# define COMPILER_ID "SDCC"
+# if defined(__SDCC_VERSION_MAJOR)
+#  define COMPILER_VERSION_MAJOR DEC(__SDCC_VERSION_MAJOR)
+#  define COMPILER_VERSION_MINOR DEC(__SDCC_VERSION_MINOR)
+#  define COMPILER_VERSION_PATCH DEC(__SDCC_VERSION_PATCH)
+# else
+  /* SDCC = VRP */
+#  define COMPILER_VERSION_MAJOR DEC(SDCC/100)
+#  define COMPILER_VERSION_MINOR DEC(SDCC/10 % 10)
+#  define COMPILER_VERSION_PATCH DEC(SDCC    % 10)
+# endif
+
+
+/* These compilers are either not known or too old to define an
+  identification macro.  Try to identify the platform and guess that
+  it is the native compiler.  */
+#elif defined(__hpux) || defined(__hpua)
+# define COMPILER_ID "HP"
+
+#else /* unknown compiler */
+# define COMPILER_ID ""
+#endif
+
+/* Construct the string literal in pieces to prevent the source from
+   getting matched.  Store it in a pointer rather than an array
+   because some compilers will just produce instructions to fill the
+   array rather than assigning a pointer to a static array.  */
+char const* info_compiler = "INFO" ":" "compiler[" COMPILER_ID "]";
+#ifdef SIMULATE_ID
+char const* info_simulate = "INFO" ":" "simulate[" SIMULATE_ID "]";
+#endif
+
+#ifdef __QNXNTO__
+char const* qnxnto = "INFO" ":" "qnxnto[]";
+#endif
+
+#if defined(__CRAYXT_COMPUTE_LINUX_TARGET)
+char const *info_cray = "INFO" ":" "compiler_wrapper[CrayPrgEnv]";
+#endif
+
+#define STRINGIFY_HELPER(X) #X
+#define STRINGIFY(X) STRINGIFY_HELPER(X)
+
+/* Identify known platforms by name.  */
+#if defined(__linux) || defined(__linux__) || defined(linux)
+# define PLATFORM_ID "Linux"
+
+#elif defined(__MSYS__)
+# define PLATFORM_ID "MSYS"
+
+#elif defined(__CYGWIN__)
+# define PLATFORM_ID "Cygwin"
+
+#elif defined(__MINGW32__)
+# define PLATFORM_ID "MinGW"
+
+#elif defined(__APPLE__)
+# define PLATFORM_ID "Darwin"
+
+#elif defined(_WIN32) || defined(__WIN32__) || defined(WIN32)
+# define PLATFORM_ID "Windows"
+
+#elif defined(__FreeBSD__) || defined(__FreeBSD)
+# define PLATFORM_ID "FreeBSD"
+
+#elif defined(__NetBSD__) || defined(__NetBSD)
+# define PLATFORM_ID "NetBSD"
+
+#elif defined(__OpenBSD__) || defined(__OPENBSD)
+# define PLATFORM_ID "OpenBSD"
+
+#elif defined(__sun) || defined(sun)
+# define PLATFORM_ID "SunOS"
+
+#elif defined(_AIX) || defined(__AIX) || defined(__AIX__) || defined(__aix) || defined(__aix__)
+# define PLATFORM_ID "AIX"
+
+#elif defined(__hpux) || defined(__hpux__)
+# define PLATFORM_ID "HP-UX"
+
+#elif defined(__HAIKU__)
+# define PLATFORM_ID "Haiku"
+
+#elif defined(__BeOS) || defined(__BEOS__) || defined(_BEOS)
+# define PLATFORM_ID "BeOS"
+
+#elif defined(__QNX__) || defined(__QNXNTO__)
+# define PLATFORM_ID "QNX"
+
+#elif defined(__tru64) || defined(_tru64) || defined(__TRU64__)
+# define PLATFORM_ID "Tru64"
+
+#elif defined(__riscos) || defined(__riscos__)
+# define PLATFORM_ID "RISCos"
+
+#elif defined(__sinix) || defined(__sinix__) || defined(__SINIX__)
+# define PLATFORM_ID "SINIX"
+
+#elif defined(__UNIX_SV__)
+# define PLATFORM_ID "UNIX_SV"
+
+#elif defined(__bsdos__)
+# define PLATFORM_ID "BSDOS"
+
+#elif defined(_MPRAS) || defined(MPRAS)
+# define PLATFORM_ID "MP-RAS"
+
+#elif defined(__osf) || defined(__osf__)
+# define PLATFORM_ID "OSF1"
+
+#elif defined(_SCO_SV) || defined(SCO_SV) || defined(sco_sv)
+# define PLATFORM_ID "SCO_SV"
+
+#elif defined(__ultrix) || defined(__ultrix__) || defined(_ULTRIX)
+# define PLATFORM_ID "ULTRIX"
+
+#elif defined(__XENIX__) || defined(_XENIX) || defined(XENIX)
+# define PLATFORM_ID "Xenix"
+
+#elif defined(__WATCOMC__)
+# if defined(__LINUX__)
+#  define PLATFORM_ID "Linux"
+
+# elif defined(__DOS__)
+#  define PLATFORM_ID "DOS"
+
+# elif defined(__OS2__)
+#  define PLATFORM_ID "OS2"
+
+# elif defined(__WINDOWS__)
+#  define PLATFORM_ID "Windows3x"
+
+# elif defined(__VXWORKS__)
+#  define PLATFORM_ID "VxWorks"
+
+# else /* unknown platform */
+#  define PLATFORM_ID
+# endif
+
+#elif defined(__INTEGRITY)
+# if defined(INT_178B)
+#  define PLATFORM_ID "Integrity178"
+
+# else /* regular Integrity */
+#  define PLATFORM_ID "Integrity"
+# endif
+
+# elif defined(_ADI_COMPILER)
+#  define PLATFORM_ID "ADSP"
+
+#else /* unknown platform */
+# define PLATFORM_ID
+
+#endif
+
+/* For windows compilers MSVC and Intel we can determine
+   the architecture of the compiler being used.  This is because
+   the compilers do not have flags that can change the architecture,
+   but rather depend on which compiler is being used
+*/
+#if defined(_WIN32) && defined(_MSC_VER)
+# if defined(_M_IA64)
+#  define ARCHITECTURE_ID "IA64"
+
+# elif defined(_M_ARM64EC)
+#  define ARCHITECTURE_ID "ARM64EC"
+
+# elif defined(_M_X64) || defined(_M_AMD64)
+#  define ARCHITECTURE_ID "x64"
+
+# elif defined(_M_IX86)
+#  define ARCHITECTURE_ID "X86"
+
+# elif defined(_M_ARM64)
+#  define ARCHITECTURE_ID "ARM64"
+
+# elif defined(_M_ARM)
+#  if _M_ARM == 4
+#   define ARCHITECTURE_ID "ARMV4I"
+#  elif _M_ARM == 5
+#   define ARCHITECTURE_ID "ARMV5I"
+#  else
+#   define ARCHITECTURE_ID "ARMV" STRINGIFY(_M_ARM)
+#  endif
+
+# elif defined(_M_MIPS)
+#  define ARCHITECTURE_ID "MIPS"
+
+# elif defined(_M_SH)
+#  define ARCHITECTURE_ID "SHx"
+
+# else /* unknown architecture */
+#  define ARCHITECTURE_ID ""
+# endif
+
+#elif defined(__WATCOMC__)
+# if defined(_M_I86)
+#  define ARCHITECTURE_ID "I86"
+
+# elif defined(_M_IX86)
+#  define ARCHITECTURE_ID "X86"
+
+# else /* unknown architecture */
+#  define ARCHITECTURE_ID ""
+# endif
+
+#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)
+# if defined(__ICCARM__)
+#  define ARCHITECTURE_ID "ARM"
+
+# elif defined(__ICCRX__)
+#  define ARCHITECTURE_ID "RX"
+
+# elif defined(__ICCRH850__)
+#  define ARCHITECTURE_ID "RH850"
+
+# elif defined(__ICCRL78__)
+#  define ARCHITECTURE_ID "RL78"
+
+# elif defined(__ICCRISCV__)
+#  define ARCHITECTURE_ID "RISCV"
+
+# elif defined(__ICCAVR__)
+#  define ARCHITECTURE_ID "AVR"
+
+# elif defined(__ICC430__)
+#  define ARCHITECTURE_ID "MSP430"
+
+# elif defined(__ICCV850__)
+#  define ARCHITECTURE_ID "V850"
+
+# elif defined(__ICC8051__)
+#  define ARCHITECTURE_ID "8051"
+
+# elif defined(__ICCSTM8__)
+#  define ARCHITECTURE_ID "STM8"
+
+# else /* unknown architecture */
+#  define ARCHITECTURE_ID ""
+# endif
+
+#elif defined(__ghs__)
+# if defined(__PPC64__)
+#  define ARCHITECTURE_ID "PPC64"
+
+# elif defined(__ppc__)
+#  define ARCHITECTURE_ID "PPC"
+
+# elif defined(__ARM__)
+#  define ARCHITECTURE_ID "ARM"
+
+# elif defined(__x86_64__)
+#  define ARCHITECTURE_ID "x64"
+
+# elif defined(__i386__)
+#  define ARCHITECTURE_ID "X86"
+
+# else /* unknown architecture */
+#  define ARCHITECTURE_ID ""
+# endif
+
+#elif defined(__clang__) && defined(__ti__)
+# if defined(__ARM_ARCH)
+#  define ARCHITECTURE_ID "ARM"
+
+# else /* unknown architecture */
+#  define ARCHITECTURE_ID ""
+# endif
+
+#elif defined(__TI_COMPILER_VERSION__)
+# if defined(__TI_ARM__)
+#  define ARCHITECTURE_ID "ARM"
+
+# elif defined(__MSP430__)
+#  define ARCHITECTURE_ID "MSP430"
+
+# elif defined(__TMS320C28XX__)
+#  define ARCHITECTURE_ID "TMS320C28x"
+
+# elif defined(__TMS320C6X__) || defined(_TMS320C6X)
+#  define ARCHITECTURE_ID "TMS320C6x"
+
+# else /* unknown architecture */
+#  define ARCHITECTURE_ID ""
+# endif
+
+# elif defined(__ADSPSHARC__)
+#  define ARCHITECTURE_ID "SHARC"
+
+# elif defined(__ADSPBLACKFIN__)
+#  define ARCHITECTURE_ID "Blackfin"
+
+#elif defined(__TASKING__)
+
+# if defined(__CTC__) || defined(__CPTC__)
+#  define ARCHITECTURE_ID "TriCore"
+
+# elif defined(__CMCS__)
+#  define ARCHITECTURE_ID "MCS"
+
+# elif defined(__CARM__)
+#  define ARCHITECTURE_ID "ARM"
+
+# elif defined(__CARC__)
+#  define ARCHITECTURE_ID "ARC"
+
+# elif defined(__C51__)
+#  define ARCHITECTURE_ID "8051"
+
+# elif defined(__CPCP__)
+#  define ARCHITECTURE_ID "PCP"
+
+# else
+#  define ARCHITECTURE_ID ""
+# endif
+
+#else
+#  define ARCHITECTURE_ID
+#endif
+
+/* Convert integer to decimal digit literals.  */
+#define DEC(n)                   \
+  ('0' + (((n) / 10000000)%10)), \
+  ('0' + (((n) / 1000000)%10)),  \
+  ('0' + (((n) / 100000)%10)),   \
+  ('0' + (((n) / 10000)%10)),    \
+  ('0' + (((n) / 1000)%10)),     \
+  ('0' + (((n) / 100)%10)),      \
+  ('0' + (((n) / 10)%10)),       \
+  ('0' +  ((n) % 10))
+
+/* Convert integer to hex digit literals.  */
+#define HEX(n)             \
+  ('0' + ((n)>>28 & 0xF)), \
+  ('0' + ((n)>>24 & 0xF)), \
+  ('0' + ((n)>>20 & 0xF)), \
+  ('0' + ((n)>>16 & 0xF)), \
+  ('0' + ((n)>>12 & 0xF)), \
+  ('0' + ((n)>>8  & 0xF)), \
+  ('0' + ((n)>>4  & 0xF)), \
+  ('0' + ((n)     & 0xF))
+
+/* Construct a string literal encoding the version number. */
+#ifdef COMPILER_VERSION
+char const* info_version = "INFO" ":" "compiler_version[" COMPILER_VERSION "]";
+
+/* Construct a string literal encoding the version number components. */
+#elif defined(COMPILER_VERSION_MAJOR)
+char const info_version[] = {
+  'I', 'N', 'F', 'O', ':',
+  'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','[',
+  COMPILER_VERSION_MAJOR,
+# ifdef COMPILER_VERSION_MINOR
+  '.', COMPILER_VERSION_MINOR,
+#  ifdef COMPILER_VERSION_PATCH
+   '.', COMPILER_VERSION_PATCH,
+#   ifdef COMPILER_VERSION_TWEAK
+    '.', COMPILER_VERSION_TWEAK,
+#   endif
+#  endif
+# endif
+  ']','\0'};
+#endif
+
+/* Construct a string literal encoding the internal version number. */
+#ifdef COMPILER_VERSION_INTERNAL
+char const info_version_internal[] = {
+  'I', 'N', 'F', 'O', ':',
+  'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','_',
+  'i','n','t','e','r','n','a','l','[',
+  COMPILER_VERSION_INTERNAL,']','\0'};
+#elif defined(COMPILER_VERSION_INTERNAL_STR)
+char const* info_version_internal = "INFO" ":" "compiler_version_internal[" COMPILER_VERSION_INTERNAL_STR "]";
+#endif
+
+/* Construct a string literal encoding the version number components. */
+#ifdef SIMULATE_VERSION_MAJOR
+char const info_simulate_version[] = {
+  'I', 'N', 'F', 'O', ':',
+  's','i','m','u','l','a','t','e','_','v','e','r','s','i','o','n','[',
+  SIMULATE_VERSION_MAJOR,
+# ifdef SIMULATE_VERSION_MINOR
+  '.', SIMULATE_VERSION_MINOR,
+#  ifdef SIMULATE_VERSION_PATCH
+   '.', SIMULATE_VERSION_PATCH,
+#   ifdef SIMULATE_VERSION_TWEAK
+    '.', SIMULATE_VERSION_TWEAK,
+#   endif
+#  endif
+# endif
+  ']','\0'};
+#endif
+
+/* Construct the string literal in pieces to prevent the source from
+   getting matched.  Store it in a pointer rather than an array
+   because some compilers will just produce instructions to fill the
+   array rather than assigning a pointer to a static array.  */
+char const* info_platform = "INFO" ":" "platform[" PLATFORM_ID "]";
+char const* info_arch = "INFO" ":" "arch[" ARCHITECTURE_ID "]";
+
+
+
+#define C_STD_99 199901L
+#define C_STD_11 201112L
+#define C_STD_17 201710L
+#define C_STD_23 202311L
+
+#ifdef __STDC_VERSION__
+#  define C_STD __STDC_VERSION__
+#endif
+
+#if !defined(__STDC__) && !defined(__clang__)
+# if defined(_MSC_VER) || defined(__ibmxl__) || defined(__IBMC__)
+#  define C_VERSION "90"
+# else
+#  define C_VERSION
+# endif
+#elif C_STD > C_STD_17
+# define C_VERSION "23"
+#elif C_STD > C_STD_11
+# define C_VERSION "17"
+#elif C_STD > C_STD_99
+# define C_VERSION "11"
+#elif C_STD >= C_STD_99
+# define C_VERSION "99"
+#else
+# define C_VERSION "90"
+#endif
+const char* info_language_standard_default =
+  "INFO" ":" "standard_default[" C_VERSION "]";
+
+const char* info_language_extensions_default = "INFO" ":" "extensions_default["
+#if (defined(__clang__) || defined(__GNUC__) || defined(__xlC__) ||           \
+     defined(__TI_COMPILER_VERSION__)) &&                                     \
+  !defined(__STRICT_ANSI__)
+  "ON"
+#else
+  "OFF"
+#endif
+"]";
+
+/*--------------------------------------------------------------------------*/
+
+#ifdef ID_VOID_MAIN
+void main() {}
+#else
+# if defined(__CLASSIC_C__)
+int main(argc, argv) int argc; char *argv[];
+# else
+int main(int argc, char* argv[])
+# endif
+{
+  int require = 0;
+  require += info_compiler[argc];
+  require += info_platform[argc];
+  require += info_arch[argc];
+#ifdef COMPILER_VERSION_MAJOR
+  require += info_version[argc];
+#endif
+#ifdef COMPILER_VERSION_INTERNAL
+  require += info_version_internal[argc];
+#endif
+#ifdef SIMULATE_ID
+  require += info_simulate[argc];
+#endif
+#ifdef SIMULATE_VERSION_MAJOR
+  require += info_simulate_version[argc];
+#endif
+#if defined(__CRAYXT_COMPUTE_LINUX_TARGET)
+  require += info_cray[argc];
+#endif
+  require += info_language_standard_default[argc];
+  require += info_language_extensions_default[argc];
+  (void)argv;
+  return require;
+}
+#endif
diff --git a/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/3.31.6/CompilerIdC/a.out b/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/3.31.6/CompilerIdC/a.out
new file mode 100755
index 000000000..4c42435a7
Binary files /dev/null and b/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/3.31.6/CompilerIdC/a.out differ
diff --git a/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/3.31.6/CompilerIdCXX/CMakeCXXCompilerId.cpp b/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/3.31.6/CompilerIdCXX/CMakeCXXCompilerId.cpp
new file mode 100644
index 000000000..3b6e114ca
--- /dev/null
+++ b/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/3.31.6/CompilerIdCXX/CMakeCXXCompilerId.cpp
@@ -0,0 +1,919 @@
+/* This source file must have a .cpp extension so that all C++ compilers
+   recognize the extension without flags.  Borland does not know .cxx for
+   example.  */
+#ifndef __cplusplus
+# error "A C compiler has been selected for C++."
+#endif
+
+#if !defined(__has_include)
+/* If the compiler does not have __has_include, pretend the answer is
+   always no.  */
+#  define __has_include(x) 0
+#endif
+
+
+/* Version number components: V=Version, R=Revision, P=Patch
+   Version date components:   YYYY=Year, MM=Month,   DD=Day  */
+
+#if defined(__INTEL_COMPILER) || defined(__ICC)
+# define COMPILER_ID "Intel"
+# if defined(_MSC_VER)
+#  define SIMULATE_ID "MSVC"
+# endif
+# if defined(__GNUC__)
+#  define SIMULATE_ID "GNU"
+# endif
+  /* __INTEL_COMPILER = VRP prior to 2021, and then VVVV for 2021 and later,
+     except that a few beta releases use the old format with V=2021.  */
+# if __INTEL_COMPILER < 2021 || __INTEL_COMPILER == 202110 || __INTEL_COMPILER == 202111
+#  define COMPILER_VERSION_MAJOR DEC(__INTEL_COMPILER/100)
+#  define COMPILER_VERSION_MINOR DEC(__INTEL_COMPILER/10 % 10)
+#  if defined(__INTEL_COMPILER_UPDATE)
+#   define COMPILER_VERSION_PATCH DEC(__INTEL_COMPILER_UPDATE)
+#  else
+#   define COMPILER_VERSION_PATCH DEC(__INTEL_COMPILER   % 10)
+#  endif
+# else
+#  define COMPILER_VERSION_MAJOR DEC(__INTEL_COMPILER)
+#  define COMPILER_VERSION_MINOR DEC(__INTEL_COMPILER_UPDATE)
+   /* The third version component from --version is an update index,
+      but no macro is provided for it.  */
+#  define COMPILER_VERSION_PATCH DEC(0)
+# endif
+# if defined(__INTEL_COMPILER_BUILD_DATE)
+   /* __INTEL_COMPILER_BUILD_DATE = YYYYMMDD */
+#  define COMPILER_VERSION_TWEAK DEC(__INTEL_COMPILER_BUILD_DATE)
+# endif
+# if defined(_MSC_VER)
+   /* _MSC_VER = VVRR */
+#  define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100)
+#  define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100)
+# endif
+# if defined(__GNUC__)
+#  define SIMULATE_VERSION_MAJOR DEC(__GNUC__)
+# elif defined(__GNUG__)
+#  define SIMULATE_VERSION_MAJOR DEC(__GNUG__)
+# endif
+# if defined(__GNUC_MINOR__)
+#  define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__)
+# endif
+# if defined(__GNUC_PATCHLEVEL__)
+#  define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__)
+# endif
+
+#elif (defined(__clang__) && defined(__INTEL_CLANG_COMPILER)) || defined(__INTEL_LLVM_COMPILER)
+# define COMPILER_ID "IntelLLVM"
+#if defined(_MSC_VER)
+# define SIMULATE_ID "MSVC"
+#endif
+#if defined(__GNUC__)
+# define SIMULATE_ID "GNU"
+#endif
+/* __INTEL_LLVM_COMPILER = VVVVRP prior to 2021.2.0, VVVVRRPP for 2021.2.0 and
+ * later.  Look for 6 digit vs. 8 digit version number to decide encoding.
+ * VVVV is no smaller than the current year when a version is released.
+ */
+#if __INTEL_LLVM_COMPILER < 1000000L
+# define COMPILER_VERSION_MAJOR DEC(__INTEL_LLVM_COMPILER/100)
+# define COMPILER_VERSION_MINOR DEC(__INTEL_LLVM_COMPILER/10 % 10)
+# define COMPILER_VERSION_PATCH DEC(__INTEL_LLVM_COMPILER    % 10)
+#else
+# define COMPILER_VERSION_MAJOR DEC(__INTEL_LLVM_COMPILER/10000)
+# define COMPILER_VERSION_MINOR DEC(__INTEL_LLVM_COMPILER/100 % 100)
+# define COMPILER_VERSION_PATCH DEC(__INTEL_LLVM_COMPILER     % 100)
+#endif
+#if defined(_MSC_VER)
+  /* _MSC_VER = VVRR */
+# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100)
+# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100)
+#endif
+#if defined(__GNUC__)
+# define SIMULATE_VERSION_MAJOR DEC(__GNUC__)
+#elif defined(__GNUG__)
+# define SIMULATE_VERSION_MAJOR DEC(__GNUG__)
+#endif
+#if defined(__GNUC_MINOR__)
+# define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__)
+#endif
+#if defined(__GNUC_PATCHLEVEL__)
+# define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__)
+#endif
+
+#elif defined(__PATHCC__)
+# define COMPILER_ID "PathScale"
+# define COMPILER_VERSION_MAJOR DEC(__PATHCC__)
+# define COMPILER_VERSION_MINOR DEC(__PATHCC_MINOR__)
+# if defined(__PATHCC_PATCHLEVEL__)
+#  define COMPILER_VERSION_PATCH DEC(__PATHCC_PATCHLEVEL__)
+# endif
+
+#elif defined(__BORLANDC__) && defined(__CODEGEARC_VERSION__)
+# define COMPILER_ID "Embarcadero"
+# define COMPILER_VERSION_MAJOR HEX(__CODEGEARC_VERSION__>>24 & 0x00FF)
+# define COMPILER_VERSION_MINOR HEX(__CODEGEARC_VERSION__>>16 & 0x00FF)
+# define COMPILER_VERSION_PATCH DEC(__CODEGEARC_VERSION__     & 0xFFFF)
+
+#elif defined(__BORLANDC__)
+# define COMPILER_ID "Borland"
+  /* __BORLANDC__ = 0xVRR */
+# define COMPILER_VERSION_MAJOR HEX(__BORLANDC__>>8)
+# define COMPILER_VERSION_MINOR HEX(__BORLANDC__ & 0xFF)
+
+#elif defined(__WATCOMC__) && __WATCOMC__ < 1200
+# define COMPILER_ID "Watcom"
+   /* __WATCOMC__ = VVRR */
+# define COMPILER_VERSION_MAJOR DEC(__WATCOMC__ / 100)
+# define COMPILER_VERSION_MINOR DEC((__WATCOMC__ / 10) % 10)
+# if (__WATCOMC__ % 10) > 0
+#  define COMPILER_VERSION_PATCH DEC(__WATCOMC__ % 10)
+# endif
+
+#elif defined(__WATCOMC__)
+# define COMPILER_ID "OpenWatcom"
+   /* __WATCOMC__ = VVRP + 1100 */
+# define COMPILER_VERSION_MAJOR DEC((__WATCOMC__ - 1100) / 100)
+# define COMPILER_VERSION_MINOR DEC((__WATCOMC__ / 10) % 10)
+# if (__WATCOMC__ % 10) > 0
+#  define COMPILER_VERSION_PATCH DEC(__WATCOMC__ % 10)
+# endif
+
+#elif defined(__SUNPRO_CC)
+# define COMPILER_ID "SunPro"
+# if __SUNPRO_CC >= 0x5100
+   /* __SUNPRO_CC = 0xVRRP */
+#  define COMPILER_VERSION_MAJOR HEX(__SUNPRO_CC>>12)
+#  define COMPILER_VERSION_MINOR HEX(__SUNPRO_CC>>4 & 0xFF)
+#  define COMPILER_VERSION_PATCH HEX(__SUNPRO_CC    & 0xF)
+# else
+   /* __SUNPRO_CC = 0xVRP */
+#  define COMPILER_VERSION_MAJOR HEX(__SUNPRO_CC>>8)
+#  define COMPILER_VERSION_MINOR HEX(__SUNPRO_CC>>4 & 0xF)
+#  define COMPILER_VERSION_PATCH HEX(__SUNPRO_CC    & 0xF)
+# endif
+
+#elif defined(__HP_aCC)
+# define COMPILER_ID "HP"
+  /* __HP_aCC = VVRRPP */
+# define COMPILER_VERSION_MAJOR DEC(__HP_aCC/10000)
+# define COMPILER_VERSION_MINOR DEC(__HP_aCC/100 % 100)
+# define COMPILER_VERSION_PATCH DEC(__HP_aCC     % 100)
+
+#elif defined(__DECCXX)
+# define COMPILER_ID "Compaq"
+  /* __DECCXX_VER = VVRRTPPPP */
+# define COMPILER_VERSION_MAJOR DEC(__DECCXX_VER/10000000)
+# define COMPILER_VERSION_MINOR DEC(__DECCXX_VER/100000  % 100)
+# define COMPILER_VERSION_PATCH DEC(__DECCXX_VER         % 10000)
+
+#elif defined(__IBMCPP__) && defined(__COMPILER_VER__)
+# define COMPILER_ID "zOS"
+  /* __IBMCPP__ = VRP */
+# define COMPILER_VERSION_MAJOR DEC(__IBMCPP__/100)
+# define COMPILER_VERSION_MINOR DEC(__IBMCPP__/10 % 10)
+# define COMPILER_VERSION_PATCH DEC(__IBMCPP__    % 10)
+
+#elif defined(__open_xl__) && defined(__clang__)
+# define COMPILER_ID "IBMClang"
+# define COMPILER_VERSION_MAJOR DEC(__open_xl_version__)
+# define COMPILER_VERSION_MINOR DEC(__open_xl_release__)
+# define COMPILER_VERSION_PATCH DEC(__open_xl_modification__)
+# define COMPILER_VERSION_TWEAK DEC(__open_xl_ptf_fix_level__)
+
+
+#elif defined(__ibmxl__) && defined(__clang__)
+# define COMPILER_ID "XLClang"
+# define COMPILER_VERSION_MAJOR DEC(__ibmxl_version__)
+# define COMPILER_VERSION_MINOR DEC(__ibmxl_release__)
+# define COMPILER_VERSION_PATCH DEC(__ibmxl_modification__)
+# define COMPILER_VERSION_TWEAK DEC(__ibmxl_ptf_fix_level__)
+
+
+#elif defined(__IBMCPP__) && !defined(__COMPILER_VER__) && __IBMCPP__ >= 800
+# define COMPILER_ID "XL"
+  /* __IBMCPP__ = VRP */
+# define COMPILER_VERSION_MAJOR DEC(__IBMCPP__/100)
+# define COMPILER_VERSION_MINOR DEC(__IBMCPP__/10 % 10)
+# define COMPILER_VERSION_PATCH DEC(__IBMCPP__    % 10)
+
+#elif defined(__IBMCPP__) && !defined(__COMPILER_VER__) && __IBMCPP__ < 800
+# define COMPILER_ID "VisualAge"
+  /* __IBMCPP__ = VRP */
+# define COMPILER_VERSION_MAJOR DEC(__IBMCPP__/100)
+# define COMPILER_VERSION_MINOR DEC(__IBMCPP__/10 % 10)
+# define COMPILER_VERSION_PATCH DEC(__IBMCPP__    % 10)
+
+#elif defined(__NVCOMPILER)
+# define COMPILER_ID "NVHPC"
+# define COMPILER_VERSION_MAJOR DEC(__NVCOMPILER_MAJOR__)
+# define COMPILER_VERSION_MINOR DEC(__NVCOMPILER_MINOR__)
+# if defined(__NVCOMPILER_PATCHLEVEL__)
+#  define COMPILER_VERSION_PATCH DEC(__NVCOMPILER_PATCHLEVEL__)
+# endif
+
+#elif defined(__PGI)
+# define COMPILER_ID "PGI"
+# define COMPILER_VERSION_MAJOR DEC(__PGIC__)
+# define COMPILER_VERSION_MINOR DEC(__PGIC_MINOR__)
+# if defined(__PGIC_PATCHLEVEL__)
+#  define COMPILER_VERSION_PATCH DEC(__PGIC_PATCHLEVEL__)
+# endif
+
+#elif defined(__clang__) && defined(__cray__)
+# define COMPILER_ID "CrayClang"
+# define COMPILER_VERSION_MAJOR DEC(__cray_major__)
+# define COMPILER_VERSION_MINOR DEC(__cray_minor__)
+# define COMPILER_VERSION_PATCH DEC(__cray_patchlevel__)
+# define COMPILER_VERSION_INTERNAL_STR __clang_version__
+
+
+#elif defined(_CRAYC)
+# define COMPILER_ID "Cray"
+# define COMPILER_VERSION_MAJOR DEC(_RELEASE_MAJOR)
+# define COMPILER_VERSION_MINOR DEC(_RELEASE_MINOR)
+
+#elif defined(__TI_COMPILER_VERSION__)
+# define COMPILER_ID "TI"
+  /* __TI_COMPILER_VERSION__ = VVVRRRPPP */
+# define COMPILER_VERSION_MAJOR DEC(__TI_COMPILER_VERSION__/1000000)
+# define COMPILER_VERSION_MINOR DEC(__TI_COMPILER_VERSION__/1000   % 1000)
+# define COMPILER_VERSION_PATCH DEC(__TI_COMPILER_VERSION__        % 1000)
+
+#elif defined(__CLANG_FUJITSU)
+# define COMPILER_ID "FujitsuClang"
+# define COMPILER_VERSION_MAJOR DEC(__FCC_major__)
+# define COMPILER_VERSION_MINOR DEC(__FCC_minor__)
+# define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__)
+# define COMPILER_VERSION_INTERNAL_STR __clang_version__
+
+
+#elif defined(__FUJITSU)
+# define COMPILER_ID "Fujitsu"
+# if defined(__FCC_version__)
+#   define COMPILER_VERSION __FCC_version__
+# elif defined(__FCC_major__)
+#   define COMPILER_VERSION_MAJOR DEC(__FCC_major__)
+#   define COMPILER_VERSION_MINOR DEC(__FCC_minor__)
+#   define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__)
+# endif
+# if defined(__fcc_version)
+#   define COMPILER_VERSION_INTERNAL DEC(__fcc_version)
+# elif defined(__FCC_VERSION)
+#   define COMPILER_VERSION_INTERNAL DEC(__FCC_VERSION)
+# endif
+
+
+#elif defined(__ghs__)
+# define COMPILER_ID "GHS"
+/* __GHS_VERSION_NUMBER = VVVVRP */
+# ifdef __GHS_VERSION_NUMBER
+# define COMPILER_VERSION_MAJOR DEC(__GHS_VERSION_NUMBER / 100)
+# define COMPILER_VERSION_MINOR DEC(__GHS_VERSION_NUMBER / 10 % 10)
+# define COMPILER_VERSION_PATCH DEC(__GHS_VERSION_NUMBER      % 10)
+# endif
+
+#elif defined(__TASKING__)
+# define COMPILER_ID "Tasking"
+  # define COMPILER_VERSION_MAJOR DEC(__VERSION__/1000)
+  # define COMPILER_VERSION_MINOR DEC(__VERSION__ % 100)
+# define COMPILER_VERSION_INTERNAL DEC(__VERSION__)
+
+#elif defined(__ORANGEC__)
+# define COMPILER_ID "OrangeC"
+# define COMPILER_VERSION_MAJOR DEC(__ORANGEC_MAJOR__)
+# define COMPILER_VERSION_MINOR DEC(__ORANGEC_MINOR__)
+# define COMPILER_VERSION_PATCH DEC(__ORANGEC_PATCHLEVEL__)
+
+#elif defined(__SCO_VERSION__)
+# define COMPILER_ID "SCO"
+
+#elif defined(__ARMCC_VERSION) && !defined(__clang__)
+# define COMPILER_ID "ARMCC"
+#if __ARMCC_VERSION >= 1000000
+  /* __ARMCC_VERSION = VRRPPPP */
+  # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/1000000)
+  # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 100)
+  # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION     % 10000)
+#else
+  /* __ARMCC_VERSION = VRPPPP */
+  # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/100000)
+  # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 10)
+  # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION    % 10000)
+#endif
+
+
+#elif defined(__clang__) && defined(__apple_build_version__)
+# define COMPILER_ID "AppleClang"
+# if defined(_MSC_VER)
+#  define SIMULATE_ID "MSVC"
+# endif
+# define COMPILER_VERSION_MAJOR DEC(__clang_major__)
+# define COMPILER_VERSION_MINOR DEC(__clang_minor__)
+# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__)
+# if defined(_MSC_VER)
+   /* _MSC_VER = VVRR */
+#  define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100)
+#  define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100)
+# endif
+# define COMPILER_VERSION_TWEAK DEC(__apple_build_version__)
+
+#elif defined(__clang__) && defined(__ARMCOMPILER_VERSION)
+# define COMPILER_ID "ARMClang"
+  # define COMPILER_VERSION_MAJOR DEC(__ARMCOMPILER_VERSION/1000000)
+  # define COMPILER_VERSION_MINOR DEC(__ARMCOMPILER_VERSION/10000 % 100)
+  # define COMPILER_VERSION_PATCH DEC(__ARMCOMPILER_VERSION/100   % 100)
+# define COMPILER_VERSION_INTERNAL DEC(__ARMCOMPILER_VERSION)
+
+#elif defined(__clang__) && defined(__ti__)
+# define COMPILER_ID "TIClang"
+  # define COMPILER_VERSION_MAJOR DEC(__ti_major__)
+  # define COMPILER_VERSION_MINOR DEC(__ti_minor__)
+  # define COMPILER_VERSION_PATCH DEC(__ti_patchlevel__)
+# define COMPILER_VERSION_INTERNAL DEC(__ti_version__)
+
+#elif defined(__clang__)
+# define COMPILER_ID "Clang"
+# if defined(_MSC_VER)
+#  define SIMULATE_ID "MSVC"
+# endif
+# define COMPILER_VERSION_MAJOR DEC(__clang_major__)
+# define COMPILER_VERSION_MINOR DEC(__clang_minor__)
+# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__)
+# if defined(_MSC_VER)
+   /* _MSC_VER = VVRR */
+#  define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100)
+#  define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100)
+# endif
+
+#elif defined(__LCC__) && (defined(__GNUC__) || defined(__GNUG__) || defined(__MCST__))
+# define COMPILER_ID "LCC"
+# define COMPILER_VERSION_MAJOR DEC(__LCC__ / 100)
+# define COMPILER_VERSION_MINOR DEC(__LCC__ % 100)
+# if defined(__LCC_MINOR__)
+#  define COMPILER_VERSION_PATCH DEC(__LCC_MINOR__)
+# endif
+# if defined(__GNUC__) && defined(__GNUC_MINOR__)
+#  define SIMULATE_ID "GNU"
+#  define SIMULATE_VERSION_MAJOR DEC(__GNUC__)
+#  define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__)
+#  if defined(__GNUC_PATCHLEVEL__)
+#   define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__)
+#  endif
+# endif
+
+#elif defined(__GNUC__) || defined(__GNUG__)
+# define COMPILER_ID "GNU"
+# if defined(__GNUC__)
+#  define COMPILER_VERSION_MAJOR DEC(__GNUC__)
+# else
+#  define COMPILER_VERSION_MAJOR DEC(__GNUG__)
+# endif
+# if defined(__GNUC_MINOR__)
+#  define COMPILER_VERSION_MINOR DEC(__GNUC_MINOR__)
+# endif
+# if defined(__GNUC_PATCHLEVEL__)
+#  define COMPILER_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__)
+# endif
+
+#elif defined(_MSC_VER)
+# define COMPILER_ID "MSVC"
+  /* _MSC_VER = VVRR */
+# define COMPILER_VERSION_MAJOR DEC(_MSC_VER / 100)
+# define COMPILER_VERSION_MINOR DEC(_MSC_VER % 100)
+# if defined(_MSC_FULL_VER)
+#  if _MSC_VER >= 1400
+    /* _MSC_FULL_VER = VVRRPPPPP */
+#   define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 100000)
+#  else
+    /* _MSC_FULL_VER = VVRRPPPP */
+#   define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 10000)
+#  endif
+# endif
+# if defined(_MSC_BUILD)
+#  define COMPILER_VERSION_TWEAK DEC(_MSC_BUILD)
+# endif
+
+#elif defined(_ADI_COMPILER)
+# define COMPILER_ID "ADSP"
+#if defined(__VERSIONNUM__)
+  /* __VERSIONNUM__ = 0xVVRRPPTT */
+#  define COMPILER_VERSION_MAJOR DEC(__VERSIONNUM__ >> 24 & 0xFF)
+#  define COMPILER_VERSION_MINOR DEC(__VERSIONNUM__ >> 16 & 0xFF)
+#  define COMPILER_VERSION_PATCH DEC(__VERSIONNUM__ >> 8 & 0xFF)
+#  define COMPILER_VERSION_TWEAK DEC(__VERSIONNUM__ & 0xFF)
+#endif
+
+#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)
+# define COMPILER_ID "IAR"
+# if defined(__VER__) && defined(__ICCARM__)
+#  define COMPILER_VERSION_MAJOR DEC((__VER__) / 1000000)
+#  define COMPILER_VERSION_MINOR DEC(((__VER__) / 1000) % 1000)
+#  define COMPILER_VERSION_PATCH DEC((__VER__) % 1000)
+#  define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__)
+# elif defined(__VER__) && (defined(__ICCAVR__) || defined(__ICCRX__) || defined(__ICCRH850__) || defined(__ICCRL78__) || defined(__ICC430__) || defined(__ICCRISCV__) || defined(__ICCV850__) || defined(__ICC8051__) || defined(__ICCSTM8__))
+#  define COMPILER_VERSION_MAJOR DEC((__VER__) / 100)
+#  define COMPILER_VERSION_MINOR DEC((__VER__) - (((__VER__) / 100)*100))
+#  define COMPILER_VERSION_PATCH DEC(__SUBVERSION__)
+#  define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__)
+# endif
+
+
+/* These compilers are either not known or too old to define an
+  identification macro.  Try to identify the platform and guess that
+  it is the native compiler.  */
+#elif defined(__hpux) || defined(__hpua)
+# define COMPILER_ID "HP"
+
+#else /* unknown compiler */
+# define COMPILER_ID ""
+#endif
+
+/* Construct the string literal in pieces to prevent the source from
+   getting matched.  Store it in a pointer rather than an array
+   because some compilers will just produce instructions to fill the
+   array rather than assigning a pointer to a static array.  */
+char const* info_compiler = "INFO" ":" "compiler[" COMPILER_ID "]";
+#ifdef SIMULATE_ID
+char const* info_simulate = "INFO" ":" "simulate[" SIMULATE_ID "]";
+#endif
+
+#ifdef __QNXNTO__
+char const* qnxnto = "INFO" ":" "qnxnto[]";
+#endif
+
+#if defined(__CRAYXT_COMPUTE_LINUX_TARGET)
+char const *info_cray = "INFO" ":" "compiler_wrapper[CrayPrgEnv]";
+#endif
+
+#define STRINGIFY_HELPER(X) #X
+#define STRINGIFY(X) STRINGIFY_HELPER(X)
+
+/* Identify known platforms by name.  */
+#if defined(__linux) || defined(__linux__) || defined(linux)
+# define PLATFORM_ID "Linux"
+
+#elif defined(__MSYS__)
+# define PLATFORM_ID "MSYS"
+
+#elif defined(__CYGWIN__)
+# define PLATFORM_ID "Cygwin"
+
+#elif defined(__MINGW32__)
+# define PLATFORM_ID "MinGW"
+
+#elif defined(__APPLE__)
+# define PLATFORM_ID "Darwin"
+
+#elif defined(_WIN32) || defined(__WIN32__) || defined(WIN32)
+# define PLATFORM_ID "Windows"
+
+#elif defined(__FreeBSD__) || defined(__FreeBSD)
+# define PLATFORM_ID "FreeBSD"
+
+#elif defined(__NetBSD__) || defined(__NetBSD)
+# define PLATFORM_ID "NetBSD"
+
+#elif defined(__OpenBSD__) || defined(__OPENBSD)
+# define PLATFORM_ID "OpenBSD"
+
+#elif defined(__sun) || defined(sun)
+# define PLATFORM_ID "SunOS"
+
+#elif defined(_AIX) || defined(__AIX) || defined(__AIX__) || defined(__aix) || defined(__aix__)
+# define PLATFORM_ID "AIX"
+
+#elif defined(__hpux) || defined(__hpux__)
+# define PLATFORM_ID "HP-UX"
+
+#elif defined(__HAIKU__)
+# define PLATFORM_ID "Haiku"
+
+#elif defined(__BeOS) || defined(__BEOS__) || defined(_BEOS)
+# define PLATFORM_ID "BeOS"
+
+#elif defined(__QNX__) || defined(__QNXNTO__)
+# define PLATFORM_ID "QNX"
+
+#elif defined(__tru64) || defined(_tru64) || defined(__TRU64__)
+# define PLATFORM_ID "Tru64"
+
+#elif defined(__riscos) || defined(__riscos__)
+# define PLATFORM_ID "RISCos"
+
+#elif defined(__sinix) || defined(__sinix__) || defined(__SINIX__)
+# define PLATFORM_ID "SINIX"
+
+#elif defined(__UNIX_SV__)
+# define PLATFORM_ID "UNIX_SV"
+
+#elif defined(__bsdos__)
+# define PLATFORM_ID "BSDOS"
+
+#elif defined(_MPRAS) || defined(MPRAS)
+# define PLATFORM_ID "MP-RAS"
+
+#elif defined(__osf) || defined(__osf__)
+# define PLATFORM_ID "OSF1"
+
+#elif defined(_SCO_SV) || defined(SCO_SV) || defined(sco_sv)
+# define PLATFORM_ID "SCO_SV"
+
+#elif defined(__ultrix) || defined(__ultrix__) || defined(_ULTRIX)
+# define PLATFORM_ID "ULTRIX"
+
+#elif defined(__XENIX__) || defined(_XENIX) || defined(XENIX)
+# define PLATFORM_ID "Xenix"
+
+#elif defined(__WATCOMC__)
+# if defined(__LINUX__)
+#  define PLATFORM_ID "Linux"
+
+# elif defined(__DOS__)
+#  define PLATFORM_ID "DOS"
+
+# elif defined(__OS2__)
+#  define PLATFORM_ID "OS2"
+
+# elif defined(__WINDOWS__)
+#  define PLATFORM_ID "Windows3x"
+
+# elif defined(__VXWORKS__)
+#  define PLATFORM_ID "VxWorks"
+
+# else /* unknown platform */
+#  define PLATFORM_ID
+# endif
+
+#elif defined(__INTEGRITY)
+# if defined(INT_178B)
+#  define PLATFORM_ID "Integrity178"
+
+# else /* regular Integrity */
+#  define PLATFORM_ID "Integrity"
+# endif
+
+# elif defined(_ADI_COMPILER)
+#  define PLATFORM_ID "ADSP"
+
+#else /* unknown platform */
+# define PLATFORM_ID
+
+#endif
+
+/* For windows compilers MSVC and Intel we can determine
+   the architecture of the compiler being used.  This is because
+   the compilers do not have flags that can change the architecture,
+   but rather depend on which compiler is being used
+*/
+#if defined(_WIN32) && defined(_MSC_VER)
+# if defined(_M_IA64)
+#  define ARCHITECTURE_ID "IA64"
+
+# elif defined(_M_ARM64EC)
+#  define ARCHITECTURE_ID "ARM64EC"
+
+# elif defined(_M_X64) || defined(_M_AMD64)
+#  define ARCHITECTURE_ID "x64"
+
+# elif defined(_M_IX86)
+#  define ARCHITECTURE_ID "X86"
+
+# elif defined(_M_ARM64)
+#  define ARCHITECTURE_ID "ARM64"
+
+# elif defined(_M_ARM)
+#  if _M_ARM == 4
+#   define ARCHITECTURE_ID "ARMV4I"
+#  elif _M_ARM == 5
+#   define ARCHITECTURE_ID "ARMV5I"
+#  else
+#   define ARCHITECTURE_ID "ARMV" STRINGIFY(_M_ARM)
+#  endif
+
+# elif defined(_M_MIPS)
+#  define ARCHITECTURE_ID "MIPS"
+
+# elif defined(_M_SH)
+#  define ARCHITECTURE_ID "SHx"
+
+# else /* unknown architecture */
+#  define ARCHITECTURE_ID ""
+# endif
+
+#elif defined(__WATCOMC__)
+# if defined(_M_I86)
+#  define ARCHITECTURE_ID "I86"
+
+# elif defined(_M_IX86)
+#  define ARCHITECTURE_ID "X86"
+
+# else /* unknown architecture */
+#  define ARCHITECTURE_ID ""
+# endif
+
+#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)
+# if defined(__ICCARM__)
+#  define ARCHITECTURE_ID "ARM"
+
+# elif defined(__ICCRX__)
+#  define ARCHITECTURE_ID "RX"
+
+# elif defined(__ICCRH850__)
+#  define ARCHITECTURE_ID "RH850"
+
+# elif defined(__ICCRL78__)
+#  define ARCHITECTURE_ID "RL78"
+
+# elif defined(__ICCRISCV__)
+#  define ARCHITECTURE_ID "RISCV"
+
+# elif defined(__ICCAVR__)
+#  define ARCHITECTURE_ID "AVR"
+
+# elif defined(__ICC430__)
+#  define ARCHITECTURE_ID "MSP430"
+
+# elif defined(__ICCV850__)
+#  define ARCHITECTURE_ID "V850"
+
+# elif defined(__ICC8051__)
+#  define ARCHITECTURE_ID "8051"
+
+# elif defined(__ICCSTM8__)
+#  define ARCHITECTURE_ID "STM8"
+
+# else /* unknown architecture */
+#  define ARCHITECTURE_ID ""
+# endif
+
+#elif defined(__ghs__)
+# if defined(__PPC64__)
+#  define ARCHITECTURE_ID "PPC64"
+
+# elif defined(__ppc__)
+#  define ARCHITECTURE_ID "PPC"
+
+# elif defined(__ARM__)
+#  define ARCHITECTURE_ID "ARM"
+
+# elif defined(__x86_64__)
+#  define ARCHITECTURE_ID "x64"
+
+# elif defined(__i386__)
+#  define ARCHITECTURE_ID "X86"
+
+# else /* unknown architecture */
+#  define ARCHITECTURE_ID ""
+# endif
+
+#elif defined(__clang__) && defined(__ti__)
+# if defined(__ARM_ARCH)
+#  define ARCHITECTURE_ID "ARM"
+
+# else /* unknown architecture */
+#  define ARCHITECTURE_ID ""
+# endif
+
+#elif defined(__TI_COMPILER_VERSION__)
+# if defined(__TI_ARM__)
+#  define ARCHITECTURE_ID "ARM"
+
+# elif defined(__MSP430__)
+#  define ARCHITECTURE_ID "MSP430"
+
+# elif defined(__TMS320C28XX__)
+#  define ARCHITECTURE_ID "TMS320C28x"
+
+# elif defined(__TMS320C6X__) || defined(_TMS320C6X)
+#  define ARCHITECTURE_ID "TMS320C6x"
+
+# else /* unknown architecture */
+#  define ARCHITECTURE_ID ""
+# endif
+
+# elif defined(__ADSPSHARC__)
+#  define ARCHITECTURE_ID "SHARC"
+
+# elif defined(__ADSPBLACKFIN__)
+#  define ARCHITECTURE_ID "Blackfin"
+
+#elif defined(__TASKING__)
+
+# if defined(__CTC__) || defined(__CPTC__)
+#  define ARCHITECTURE_ID "TriCore"
+
+# elif defined(__CMCS__)
+#  define ARCHITECTURE_ID "MCS"
+
+# elif defined(__CARM__)
+#  define ARCHITECTURE_ID "ARM"
+
+# elif defined(__CARC__)
+#  define ARCHITECTURE_ID "ARC"
+
+# elif defined(__C51__)
+#  define ARCHITECTURE_ID "8051"
+
+# elif defined(__CPCP__)
+#  define ARCHITECTURE_ID "PCP"
+
+# else
+#  define ARCHITECTURE_ID ""
+# endif
+
+#else
+#  define ARCHITECTURE_ID
+#endif
+
+/* Convert integer to decimal digit literals.  */
+#define DEC(n)                   \
+  ('0' + (((n) / 10000000)%10)), \
+  ('0' + (((n) / 1000000)%10)),  \
+  ('0' + (((n) / 100000)%10)),   \
+  ('0' + (((n) / 10000)%10)),    \
+  ('0' + (((n) / 1000)%10)),     \
+  ('0' + (((n) / 100)%10)),      \
+  ('0' + (((n) / 10)%10)),       \
+  ('0' +  ((n) % 10))
+
+/* Convert integer to hex digit literals.  */
+#define HEX(n)             \
+  ('0' + ((n)>>28 & 0xF)), \
+  ('0' + ((n)>>24 & 0xF)), \
+  ('0' + ((n)>>20 & 0xF)), \
+  ('0' + ((n)>>16 & 0xF)), \
+  ('0' + ((n)>>12 & 0xF)), \
+  ('0' + ((n)>>8  & 0xF)), \
+  ('0' + ((n)>>4  & 0xF)), \
+  ('0' + ((n)     & 0xF))
+
+/* Construct a string literal encoding the version number. */
+#ifdef COMPILER_VERSION
+char const* info_version = "INFO" ":" "compiler_version[" COMPILER_VERSION "]";
+
+/* Construct a string literal encoding the version number components. */
+#elif defined(COMPILER_VERSION_MAJOR)
+char const info_version[] = {
+  'I', 'N', 'F', 'O', ':',
+  'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','[',
+  COMPILER_VERSION_MAJOR,
+# ifdef COMPILER_VERSION_MINOR
+  '.', COMPILER_VERSION_MINOR,
+#  ifdef COMPILER_VERSION_PATCH
+   '.', COMPILER_VERSION_PATCH,
+#   ifdef COMPILER_VERSION_TWEAK
+    '.', COMPILER_VERSION_TWEAK,
+#   endif
+#  endif
+# endif
+  ']','\0'};
+#endif
+
+/* Construct a string literal encoding the internal version number. */
+#ifdef COMPILER_VERSION_INTERNAL
+char const info_version_internal[] = {
+  'I', 'N', 'F', 'O', ':',
+  'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','_',
+  'i','n','t','e','r','n','a','l','[',
+  COMPILER_VERSION_INTERNAL,']','\0'};
+#elif defined(COMPILER_VERSION_INTERNAL_STR)
+char const* info_version_internal = "INFO" ":" "compiler_version_internal[" COMPILER_VERSION_INTERNAL_STR "]";
+#endif
+
+/* Construct a string literal encoding the version number components. */
+#ifdef SIMULATE_VERSION_MAJOR
+char const info_simulate_version[] = {
+  'I', 'N', 'F', 'O', ':',
+  's','i','m','u','l','a','t','e','_','v','e','r','s','i','o','n','[',
+  SIMULATE_VERSION_MAJOR,
+# ifdef SIMULATE_VERSION_MINOR
+  '.', SIMULATE_VERSION_MINOR,
+#  ifdef SIMULATE_VERSION_PATCH
+   '.', SIMULATE_VERSION_PATCH,
+#   ifdef SIMULATE_VERSION_TWEAK
+    '.', SIMULATE_VERSION_TWEAK,
+#   endif
+#  endif
+# endif
+  ']','\0'};
+#endif
+
+/* Construct the string literal in pieces to prevent the source from
+   getting matched.  Store it in a pointer rather than an array
+   because some compilers will just produce instructions to fill the
+   array rather than assigning a pointer to a static array.  */
+char const* info_platform = "INFO" ":" "platform[" PLATFORM_ID "]";
+char const* info_arch = "INFO" ":" "arch[" ARCHITECTURE_ID "]";
+
+
+
+#define CXX_STD_98 199711L
+#define CXX_STD_11 201103L
+#define CXX_STD_14 201402L
+#define CXX_STD_17 201703L
+#define CXX_STD_20 202002L
+#define CXX_STD_23 202302L
+
+#if defined(__INTEL_COMPILER) && defined(_MSVC_LANG)
+#  if _MSVC_LANG > CXX_STD_17
+#    define CXX_STD _MSVC_LANG
+#  elif _MSVC_LANG == CXX_STD_17 && defined(__cpp_aggregate_paren_init)
+#    define CXX_STD CXX_STD_20
+#  elif _MSVC_LANG > CXX_STD_14 && __cplusplus > CXX_STD_17
+#    define CXX_STD CXX_STD_20
+#  elif _MSVC_LANG > CXX_STD_14
+#    define CXX_STD CXX_STD_17
+#  elif defined(__INTEL_CXX11_MODE__) && defined(__cpp_aggregate_nsdmi)
+#    define CXX_STD CXX_STD_14
+#  elif defined(__INTEL_CXX11_MODE__)
+#    define CXX_STD CXX_STD_11
+#  else
+#    define CXX_STD CXX_STD_98
+#  endif
+#elif defined(_MSC_VER) && defined(_MSVC_LANG)
+#  if _MSVC_LANG > __cplusplus
+#    define CXX_STD _MSVC_LANG
+#  else
+#    define CXX_STD __cplusplus
+#  endif
+#elif defined(__NVCOMPILER)
+#  if __cplusplus == CXX_STD_17 && defined(__cpp_aggregate_paren_init)
+#    define CXX_STD CXX_STD_20
+#  else
+#    define CXX_STD __cplusplus
+#  endif
+#elif defined(__INTEL_COMPILER) || defined(__PGI)
+#  if __cplusplus == CXX_STD_11 && defined(__cpp_namespace_attributes)
+#    define CXX_STD CXX_STD_17
+#  elif __cplusplus == CXX_STD_11 && defined(__cpp_aggregate_nsdmi)
+#    define CXX_STD CXX_STD_14
+#  else
+#    define CXX_STD __cplusplus
+#  endif
+#elif (defined(__IBMCPP__) || defined(__ibmxl__)) && defined(__linux__)
+#  if __cplusplus == CXX_STD_11 && defined(__cpp_aggregate_nsdmi)
+#    define CXX_STD CXX_STD_14
+#  else
+#    define CXX_STD __cplusplus
+#  endif
+#elif __cplusplus == 1 && defined(__GXX_EXPERIMENTAL_CXX0X__)
+#  define CXX_STD CXX_STD_11
+#else
+#  define CXX_STD __cplusplus
+#endif
+
+const char* info_language_standard_default = "INFO" ":" "standard_default["
+#if CXX_STD > CXX_STD_23
+  "26"
+#elif CXX_STD > CXX_STD_20
+  "23"
+#elif CXX_STD > CXX_STD_17
+  "20"
+#elif CXX_STD > CXX_STD_14
+  "17"
+#elif CXX_STD > CXX_STD_11
+  "14"
+#elif CXX_STD >= CXX_STD_11
+  "11"
+#else
+  "98"
+#endif
+"]";
+
+const char* info_language_extensions_default = "INFO" ":" "extensions_default["
+#if (defined(__clang__) || defined(__GNUC__) || defined(__xlC__) ||           \
+     defined(__TI_COMPILER_VERSION__)) &&                                     \
+  !defined(__STRICT_ANSI__)
+  "ON"
+#else
+  "OFF"
+#endif
+"]";
+
+/*--------------------------------------------------------------------------*/
+
+int main(int argc, char* argv[])
+{
+  int require = 0;
+  require += info_compiler[argc];
+  require += info_platform[argc];
+  require += info_arch[argc];
+#ifdef COMPILER_VERSION_MAJOR
+  require += info_version[argc];
+#endif
+#ifdef COMPILER_VERSION_INTERNAL
+  require += info_version_internal[argc];
+#endif
+#ifdef SIMULATE_ID
+  require += info_simulate[argc];
+#endif
+#ifdef SIMULATE_VERSION_MAJOR
+  require += info_simulate_version[argc];
+#endif
+#if defined(__CRAYXT_COMPUTE_LINUX_TARGET)
+  require += info_cray[argc];
+#endif
+  require += info_language_standard_default[argc];
+  require += info_language_extensions_default[argc];
+  (void)argv;
+  return require;
+}
diff --git a/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/3.31.6/CompilerIdCXX/a.out b/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/3.31.6/CompilerIdCXX/a.out
new file mode 100755
index 000000000..aafe5061a
Binary files /dev/null and b/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/3.31.6/CompilerIdCXX/a.out differ
diff --git a/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/CMakeConfigureLog.yaml b/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/CMakeConfigureLog.yaml
new file mode 100644
index 000000000..784587c51
--- /dev/null
+++ b/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/CMakeConfigureLog.yaml
@@ -0,0 +1,539 @@
+
+---
+events:
+  -
+    kind: "message-v1"
+    backtrace:
+      - "/usr/share/cmake-3.31/Modules/CMakeDetermineSystem.cmake:200 (message)"
+      - "/home/abobkov/esp/v5.4.1/esp-idf/tools/cmake/project.cmake:571 (__project)"
+      - "CMakeLists.txt:67 (project)"
+    message: |
+      The target system is: Generic -  - 
+      The host system is: Linux - 6.14.0-22-generic - x86_64
+  -
+    kind: "message-v1"
+    backtrace:
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+      - "/usr/share/cmake-3.31/Modules/CMakeDetermineCompilerId.cmake:64 (__determine_compiler_id_test)"
+      - "/usr/share/cmake-3.31/Modules/CMakeDetermineCCompiler.cmake:123 (CMAKE_DETERMINE_COMPILER_ID)"
+      - "/home/abobkov/esp/v5.4.1/esp-idf/tools/cmake/project.cmake:571 (__project)"
+      - "CMakeLists.txt:67 (project)"
+    message: |
+      Compiling the C compiler identification source file "CMakeCCompilerId.c" succeeded.
+      Compiler: /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/riscv32-esp-elf-gcc 
+      Build flags: -march=rv32imc_zicsr_zifencei
+      Id flags:  
+      
+      The output was:
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+      /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/bin/ld: /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32/libc.a(libc_a-closer.o): in function `_close_r':
+      /builds/idf/crosstool-NG/.build/riscv32-esp-elf/src/newlib/newlib/libc/reent/closer.c:47:(.text+0x14): warning: _close is not implemented and will always fail
+      /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/bin/ld: /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32/libc.a(libc_a-lseekr.o): in function `_lseek_r':
+      /builds/idf/crosstool-NG/.build/riscv32-esp-elf/src/newlib/newlib/libc/reent/lseekr.c:49:(.text+0x18): warning: _lseek is not implemented and will always fail
+      /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/bin/ld: /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32/libc.a(libc_a-readr.o): in function `_read_r':
+      /builds/idf/crosstool-NG/.build/riscv32-esp-elf/src/newlib/newlib/libc/reent/readr.c:49:(.text+0x18): warning: _read is not implemented and will always fail
+      /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/bin/ld: /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32/libc.a(libc_a-writer.o): in function `_write_r':
+      /builds/idf/crosstool-NG/.build/riscv32-esp-elf/src/newlib/newlib/libc/reent/writer.c:49:(.text+0x18): warning: _write is not implemented and will always fail
+      /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/bin/ld: /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32/libc.a(libc_a-fclose.o): in function `fclose':
+      /builds/idf/crosstool-NG/.build/riscv32-esp-elf/src/newlib/newlib/libc/stdio/fclose.c:125:(.text+0xf4): warning: __getreent is not implemented and will always fail
+      
+      
+      Compilation of the C compiler identification source "CMakeCCompilerId.c" produced "a.out"
+      
+      The C compiler identification is GNU, found in:
+        /home/abobkov/MyProjects/ESP-Nodes/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/3.31.6/CompilerIdC/a.out
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+      - "/usr/share/cmake-3.31/Modules/CMakeDetermineCompilerId.cmake:64 (__determine_compiler_id_test)"
+      - "/usr/share/cmake-3.31/Modules/CMakeDetermineCXXCompiler.cmake:126 (CMAKE_DETERMINE_COMPILER_ID)"
+      - "/home/abobkov/esp/v5.4.1/esp-idf/tools/cmake/project.cmake:571 (__project)"
+      - "CMakeLists.txt:67 (project)"
+    message: |
+      Compiling the CXX compiler identification source file "CMakeCXXCompilerId.cpp" succeeded.
+      Compiler: /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/riscv32-esp-elf-g++ 
+      Build flags: -march=rv32imc_zicsr_zifencei
+      Id flags:  
+      
+      The output was:
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+      /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/bin/ld: /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32/libc.a(libc_a-closer.o): in function `_close_r':
+      /builds/idf/crosstool-NG/.build/riscv32-esp-elf/src/newlib/newlib/libc/reent/closer.c:47:(.text+0x14): warning: _close is not implemented and will always fail
+      /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/bin/ld: /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32/libc.a(libc_a-lseekr.o): in function `_lseek_r':
+      /builds/idf/crosstool-NG/.build/riscv32-esp-elf/src/newlib/newlib/libc/reent/lseekr.c:49:(.text+0x18): warning: _lseek is not implemented and will always fail
+      /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/bin/ld: /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32/libc.a(libc_a-readr.o): in function `_read_r':
+      /builds/idf/crosstool-NG/.build/riscv32-esp-elf/src/newlib/newlib/libc/reent/readr.c:49:(.text+0x18): warning: _read is not implemented and will always fail
+      /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/bin/ld: /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32/libc.a(libc_a-writer.o): in function `_write_r':
+      /builds/idf/crosstool-NG/.build/riscv32-esp-elf/src/newlib/newlib/libc/reent/writer.c:49:(.text+0x18): warning: _write is not implemented and will always fail
+      /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/bin/ld: /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32/libc.a(libc_a-fclose.o): in function `fclose':
+      /builds/idf/crosstool-NG/.build/riscv32-esp-elf/src/newlib/newlib/libc/stdio/fclose.c:125:(.text+0xf4): warning: __getreent is not implemented and will always fail
+      
+      
+      Compilation of the CXX compiler identification source "CMakeCXXCompilerId.cpp" produced "a.out"
+      
+      The CXX compiler identification is GNU, found in:
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+      - "/usr/share/cmake-3.31/Modules/CMakeDetermineASMCompiler.cmake:135 (CMAKE_DETERMINE_COMPILER_ID_VENDOR)"
+      - "/home/abobkov/esp/v5.4.1/esp-idf/tools/cmake/project.cmake:571 (__project)"
+      - "CMakeLists.txt:67 (project)"
+    message: |
+      Checking whether the ASM compiler is GNU using "--version" matched "(GNU assembler)|(GCC)|(Free Software Foundation)":
+      riscv32-esp-elf-gcc (crosstool-NG esp-14.2.0_20241119) 14.2.0
+      Copyright (C) 2024 Free Software Foundation, Inc.
+      This is free software; see the source for copying conditions.  There is NO
+      warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+      
+  -
+    kind: "try_compile-v1"
+    backtrace:
+      - "/usr/share/cmake-3.31/Modules/CMakeDetermineCompilerABI.cmake:74 (try_compile)"
+      - "/usr/share/cmake-3.31/Modules/CMakeTestCCompiler.cmake:26 (CMAKE_DETERMINE_COMPILER_ABI)"
+      - "/home/abobkov/esp/v5.4.1/esp-idf/tools/cmake/project.cmake:571 (__project)"
+      - "CMakeLists.txt:67 (project)"
+    checks:
+      - "Detecting C compiler ABI info"
+    directories:
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+      CMAKE_EXE_LINKER_FLAGS: "-nostartfiles -march=rv32imc_zicsr_zifencei --specs=nosys.specs "
+      CMAKE_MODULE_PATH: "/home/abobkov/esp/v5.4.1/esp-idf/tools/cmake;/home/abobkov/esp/v5.4.1/esp-idf/tools/cmake/third_party"
+    buildResult:
+      variable: "CMAKE_C_ABI_COMPILED"
+      cached: true
+      stdout: |
+        Change Dir: '/home/abobkov/MyProjects/ESP-Nodes/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/CMakeScratch/TryCompile-mFTWm6'
+        
+        Run Build Command(s): /usr/bin/ninja -v cmTC_03a7a
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+        Using built-in specs.
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+        GNU C17 (crosstool-NG esp-14.2.0_20241119) version 14.2.0 (riscv32-esp-elf)
+        	compiled by GNU C version 4.9.2, GMP version 6.2.1, MPFR version 4.2.1, MPC version 1.2.1, isl version isl-0.26-GMP
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+        ignoring duplicate directory "/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/../../lib/gcc/riscv32-esp-elf/14.2.0/include-fixed"
+        ignoring duplicate directory "/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/../../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/include"
+        ignoring duplicate directory "/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/include"
+        #include "..." search starts here:
+        #include <...> search starts here:
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+         /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/include-fixed
+         /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/include
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+        [2/2] : && /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/riscv32-esp-elf-gcc -march=rv32imc_zicsr_zifencei -nostartfiles -march=rv32imc_zicsr_zifencei --specs=nosys.specs  -v CMakeFiles/cmTC_03a7a.dir/CMakeCCompilerABI.c.obj -o cmTC_03a7a   && :
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+        rename spec link_gcc_c_sequence to nosys_link_gcc_c_sequence
+        COLLECT_GCC=/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/riscv32-esp-elf-gcc
+        COLLECT_LTO_WRAPPER=/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../libexec/gcc/riscv32-esp-elf/14.2.0/lto-wrapper
+        Target: riscv32-esp-elf
+        Configured with: /builds/idf/crosstool-NG/.build/riscv32-esp-elf/src/gcc/configure --build=x86_64-build_pc-linux-gnu --host=x86_64-build_pc-linux-gnu --target=riscv32-esp-elf --prefix=/builds/idf/crosstool-NG/builds/riscv32-esp-elf --exec_prefix=/builds/idf/crosstool-NG/builds/riscv32-esp-elf --with-local-prefix=/builds/idf/crosstool-NG/builds/riscv32-esp-elf/riscv32-esp-elf --with-sysroot=/builds/idf/crosstool-NG/builds/riscv32-esp-elf/riscv32-esp-elf --with-native-system-header-dir=/include --with-newlib --enable-threads=no --disable-shared --with-arch=rv32gc --with-abi=ilp32 --with-pkgversion='crosstool-NG esp-14.2.0_20241119' --disable-__cxa_atexit --enable-cxx-flags=-ffunction-sections --disable-libgomp --disable-libmudflap --disable-libmpx --disable-libssp --disable-libquadmath --disable-libquadmath-support --disable-libstdcxx-verbose --with-gmp=/builds/idf/crosstool-NG/.build/riscv32-esp-elf/buildtools --with-mpfr=/builds/idf/crosstool-NG/.build/riscv32-esp-elf/buildtools --with-mpc=/builds/idf/crosstool-NG/.build/riscv32-esp-elf/buildtools --with-isl=/builds/idf/crosstool-NG/.build/riscv32-esp-elf/buildtools --enable-lto --enable-target-optspace --without-long-double-128 --disable-nls --enable-multiarch --enable-languages=c,c++ --disable-libstdcxx-verbose --enable-threads=posix --enable-gcov-custom-rtio --enable-libstdcxx-time=yes
+        Thread model: posix
+        Supported LTO compression algorithms: zlib zstd
+        gcc version 14.2.0 (crosstool-NG esp-14.2.0_20241119) 
+        COMPILER_PATH=/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../libexec/gcc/riscv32-esp-elf/14.2.0/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../libexec/gcc/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/bin/
+        LIBRARY_PATH=/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/rv32imc_zicsr_zifencei/ilp32/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/lib/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/usr/lib/
+        COLLECT_GCC_OPTIONS='-nostartfiles' '-march=rv32imc_zicsr_zifencei' '-specs=nosys.specs' '-v' '-o' 'cmTC_03a7a' '-mabi=ilp32' '-misa-spec=20191213' '-march=rv32imc_zicsr_zifencei' '-dumpdir' 'cmTC_03a7a.'
+         /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../libexec/gcc/riscv32-esp-elf/14.2.0/collect2 -plugin /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../libexec/gcc/riscv32-esp-elf/14.2.0/liblto_plugin.so -plugin-opt=/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../libexec/gcc/riscv32-esp-elf/14.2.0/lto-wrapper -plugin-opt=-fresolution=/tmp/ccIfLCS5.res -plugin-opt=-pass-through=-lgcc -plugin-opt=-pass-through=-lc -plugin-opt=-pass-through=-lnosys -plugin-opt=-pass-through=-lc -plugin-opt=-pass-through=-lgcc -plugin-opt=-pass-through=-lgcc -plugin-opt=-pass-through=-lc -plugin-opt=-pass-through=-lnosys --sysroot=/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf -melf32lriscv -X -o cmTC_03a7a -L/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/rv32imc_zicsr_zifencei/ilp32 -L/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32 -L/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32 -L/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0 -L/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc -L/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib -L/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/lib -L/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/usr/lib CMakeFiles/cmTC_03a7a.dir/CMakeCCompilerABI.c.obj -lgcc -lc -lnosys -lc -lgcc --start-group -lgcc -lc -lnosys --end-group
+        /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/bin/ld: warning: cannot find entry symbol _start; defaulting to 00010094
+        COLLECT_GCC_OPTIONS='-nostartfiles' '-march=rv32imc_zicsr_zifencei' '-specs=nosys.specs' '-v' '-o' 'cmTC_03a7a' '-mabi=ilp32' '-misa-spec=20191213' '-march=rv32imc_zicsr_zifencei' '-dumpdir' 'cmTC_03a7a.'
+        
+      exitCode: 0
+  -
+    kind: "message-v1"
+    backtrace:
+      - "/usr/share/cmake-3.31/Modules/CMakeDetermineCompilerABI.cmake:182 (message)"
+      - "/usr/share/cmake-3.31/Modules/CMakeTestCCompiler.cmake:26 (CMAKE_DETERMINE_COMPILER_ABI)"
+      - "/home/abobkov/esp/v5.4.1/esp-idf/tools/cmake/project.cmake:571 (__project)"
+      - "CMakeLists.txt:67 (project)"
+    message: |
+      Parsed C implicit include dir info: rv=done
+        found start of include info
+        found start of implicit include info
+          add: [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/include]
+          add: [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/include-fixed]
+          add: [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/include]
+        end of search list found
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+        collapse include dir [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/include-fixed] ==> [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/lib/gcc/riscv32-esp-elf/14.2.0/include-fixed]
+        collapse include dir [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/include] ==> [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/riscv32-esp-elf/include]
+        implicit include dirs: [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/lib/gcc/riscv32-esp-elf/14.2.0/include;/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/lib/gcc/riscv32-esp-elf/14.2.0/include-fixed;/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/riscv32-esp-elf/include]
+      
+      
+  -
+    kind: "message-v1"
+    backtrace:
+      - "/usr/share/cmake-3.31/Modules/CMakeDetermineCompilerABI.cmake:218 (message)"
+      - "/usr/share/cmake-3.31/Modules/CMakeTestCCompiler.cmake:26 (CMAKE_DETERMINE_COMPILER_ABI)"
+      - "/home/abobkov/esp/v5.4.1/esp-idf/tools/cmake/project.cmake:571 (__project)"
+      - "CMakeLists.txt:67 (project)"
+    message: |
+      Parsed C implicit link information:
+        link line regex: [^( *|.*[/\\])(ld[0-9]*(\\.[a-z]+)?|CMAKE_LINK_STARTFILE-NOTFOUND|([^/\\]+-)?ld|collect2)[^/\\]*( |$)]
+        linker tool regex: [^[ 	]*(->|")?[ 	]*(([^"]*[/\\])?(ld[0-9]*(\\.[a-z]+)?))("|,| |$)]
+        ignore line: [Change Dir: '/home/abobkov/MyProjects/ESP-Nodes/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/CMakeScratch/TryCompile-mFTWm6']
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+        ignore line: [Run Build Command(s): /usr/bin/ninja -v cmTC_03a7a]
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+        ignore line: [Target: riscv32-esp-elf]
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+        
+        Run Build Command(s): /usr/bin/ninja -v cmTC_a5c8a
+        [1/2] /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/riscv32-esp-elf-g++   -march=rv32imc_zicsr_zifencei     -v -o CMakeFiles/cmTC_a5c8a.dir/CMakeCXXCompilerABI.cpp.obj -c /usr/share/cmake-3.31/Modules/CMakeCXXCompilerABI.cpp
+        Using built-in specs.
+        COLLECT_GCC=/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/riscv32-esp-elf-g++
+        Target: riscv32-esp-elf
+        Configured with: /builds/idf/crosstool-NG/.build/riscv32-esp-elf/src/gcc/configure --build=x86_64-build_pc-linux-gnu --host=x86_64-build_pc-linux-gnu --target=riscv32-esp-elf --prefix=/builds/idf/crosstool-NG/builds/riscv32-esp-elf --exec_prefix=/builds/idf/crosstool-NG/builds/riscv32-esp-elf --with-local-prefix=/builds/idf/crosstool-NG/builds/riscv32-esp-elf/riscv32-esp-elf --with-sysroot=/builds/idf/crosstool-NG/builds/riscv32-esp-elf/riscv32-esp-elf --with-native-system-header-dir=/include --with-newlib --enable-threads=no --disable-shared --with-arch=rv32gc --with-abi=ilp32 --with-pkgversion='crosstool-NG esp-14.2.0_20241119' --disable-__cxa_atexit --enable-cxx-flags=-ffunction-sections --disable-libgomp --disable-libmudflap --disable-libmpx --disable-libssp --disable-libquadmath --disable-libquadmath-support --disable-libstdcxx-verbose --with-gmp=/builds/idf/crosstool-NG/.build/riscv32-esp-elf/buildtools --with-mpfr=/builds/idf/crosstool-NG/.build/riscv32-esp-elf/buildtools --with-mpc=/builds/idf/crosstool-NG/.build/riscv32-esp-elf/buildtools --with-isl=/builds/idf/crosstool-NG/.build/riscv32-esp-elf/buildtools --enable-lto --enable-target-optspace --without-long-double-128 --disable-nls --enable-multiarch --enable-languages=c,c++ --disable-libstdcxx-verbose --enable-threads=posix --enable-gcov-custom-rtio --enable-libstdcxx-time=yes
+        Thread model: posix
+        Supported LTO compression algorithms: zlib zstd
+        gcc version 14.2.0 (crosstool-NG esp-14.2.0_20241119) 
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+        GNU C++17 (crosstool-NG esp-14.2.0_20241119) version 14.2.0 (riscv32-esp-elf)
+        	compiled by GNU C version 4.9.2, GMP version 6.2.1, MPFR version 4.2.1, MPC version 1.2.1, isl version isl-0.26-GMP
+        
+        GGC heuristics: --param ggc-min-expand=100 --param ggc-min-heapsize=131072
+        ignoring duplicate directory "/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/../../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/include/c++/14.2.0"
+        ignoring duplicate directory "/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/../../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/include/c++/14.2.0/riscv32-esp-elf/rv32imc_zicsr_zifencei/ilp32"
+        ignoring duplicate directory "/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/../../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/include/c++/14.2.0/backward"
+        ignoring duplicate directory "/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/../../lib/gcc/riscv32-esp-elf/14.2.0/include"
+        ignoring nonexistent directory "/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/builds/idf/crosstool-NG/builds/riscv32-esp-elf/riscv32-esp-elf/include"
+        ignoring duplicate directory "/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/../../lib/gcc/riscv32-esp-elf/14.2.0/include-fixed"
+        ignoring duplicate directory "/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/../../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/include"
+        ignoring duplicate directory "/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/include"
+        #include "..." search starts here:
+        #include <...> search starts here:
+         /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/include/c++/14.2.0
+         /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/include/c++/14.2.0/riscv32-esp-elf/rv32imc_zicsr_zifencei/ilp32
+         /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/include/c++/14.2.0/backward
+         /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/include
+         /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/include-fixed
+         /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/include
+        End of search list.
+        Compiler executable checksum: c7cd21a23c5c74d612ca7681e3115c94
+        COLLECT_GCC_OPTIONS='-march=rv32imc_zicsr_zifencei' '-v' '-o' 'CMakeFiles/cmTC_a5c8a.dir/CMakeCXXCompilerABI.cpp.obj' '-c' '-mabi=ilp32' '-misa-spec=20191213' '-march=rv32imc_zicsr_zifencei' '-dumpdir' 'CMakeFiles/cmTC_a5c8a.dir/'
+         /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/bin/as -v --traditional-format -march=rv32imc_zicsr_zifencei -march=rv32imc_zicsr_zifencei -mabi=ilp32 -misa-spec=20191213 -o CMakeFiles/cmTC_a5c8a.dir/CMakeCXXCompilerABI.cpp.obj /tmp/cc8Sfg83.s
+        GNU assembler version 2.43.1 (riscv32-esp-elf) using BFD version (crosstool-NG esp-14.2.0_20241119) 2.43.1
+        COMPILER_PATH=/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../libexec/gcc/riscv32-esp-elf/14.2.0/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../libexec/gcc/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/bin/
+        LIBRARY_PATH=/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/rv32imc_zicsr_zifencei/ilp32/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/lib/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/usr/lib/
+        COLLECT_GCC_OPTIONS='-march=rv32imc_zicsr_zifencei' '-v' '-o' 'CMakeFiles/cmTC_a5c8a.dir/CMakeCXXCompilerABI.cpp.obj' '-c' '-mabi=ilp32' '-misa-spec=20191213' '-march=rv32imc_zicsr_zifencei' '-dumpdir' 'CMakeFiles/cmTC_a5c8a.dir/CMakeCXXCompilerABI.cpp.'
+        [2/2] : && /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/riscv32-esp-elf-g++ -march=rv32imc_zicsr_zifencei -nostartfiles -march=rv32imc_zicsr_zifencei --specs=nosys.specs  -v CMakeFiles/cmTC_a5c8a.dir/CMakeCXXCompilerABI.cpp.obj -o cmTC_a5c8a   && :
+        Using built-in specs.
+        Reading specs from /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib/nosys.specs
+        rename spec link_gcc_c_sequence to nosys_link_gcc_c_sequence
+        COLLECT_GCC=/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/riscv32-esp-elf-g++
+        COLLECT_LTO_WRAPPER=/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../libexec/gcc/riscv32-esp-elf/14.2.0/lto-wrapper
+        Target: riscv32-esp-elf
+        Configured with: /builds/idf/crosstool-NG/.build/riscv32-esp-elf/src/gcc/configure --build=x86_64-build_pc-linux-gnu --host=x86_64-build_pc-linux-gnu --target=riscv32-esp-elf --prefix=/builds/idf/crosstool-NG/builds/riscv32-esp-elf --exec_prefix=/builds/idf/crosstool-NG/builds/riscv32-esp-elf --with-local-prefix=/builds/idf/crosstool-NG/builds/riscv32-esp-elf/riscv32-esp-elf --with-sysroot=/builds/idf/crosstool-NG/builds/riscv32-esp-elf/riscv32-esp-elf --with-native-system-header-dir=/include --with-newlib --enable-threads=no --disable-shared --with-arch=rv32gc --with-abi=ilp32 --with-pkgversion='crosstool-NG esp-14.2.0_20241119' --disable-__cxa_atexit --enable-cxx-flags=-ffunction-sections --disable-libgomp --disable-libmudflap --disable-libmpx --disable-libssp --disable-libquadmath --disable-libquadmath-support --disable-libstdcxx-verbose --with-gmp=/builds/idf/crosstool-NG/.build/riscv32-esp-elf/buildtools --with-mpfr=/builds/idf/crosstool-NG/.build/riscv32-esp-elf/buildtools --with-mpc=/builds/idf/crosstool-NG/.build/riscv32-esp-elf/buildtools --with-isl=/builds/idf/crosstool-NG/.build/riscv32-esp-elf/buildtools --enable-lto --enable-target-optspace --without-long-double-128 --disable-nls --enable-multiarch --enable-languages=c,c++ --disable-libstdcxx-verbose --enable-threads=posix --enable-gcov-custom-rtio --enable-libstdcxx-time=yes
+        Thread model: posix
+        Supported LTO compression algorithms: zlib zstd
+        gcc version 14.2.0 (crosstool-NG esp-14.2.0_20241119) 
+        COMPILER_PATH=/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../libexec/gcc/riscv32-esp-elf/14.2.0/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../libexec/gcc/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/bin/
+        LIBRARY_PATH=/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/rv32imc_zicsr_zifencei/ilp32/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/lib/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/usr/lib/
+        COLLECT_GCC_OPTIONS='-nostartfiles' '-march=rv32imc_zicsr_zifencei' '-specs=nosys.specs' '-v' '-o' 'cmTC_a5c8a' '-mabi=ilp32' '-misa-spec=20191213' '-march=rv32imc_zicsr_zifencei' '-dumpdir' 'cmTC_a5c8a.'
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+        /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/bin/ld: warning: cannot find entry symbol _start; defaulting to 00010094
+        COLLECT_GCC_OPTIONS='-nostartfiles' '-march=rv32imc_zicsr_zifencei' '-specs=nosys.specs' '-v' '-o' 'cmTC_a5c8a' '-mabi=ilp32' '-misa-spec=20191213' '-march=rv32imc_zicsr_zifencei' '-dumpdir' 'cmTC_a5c8a.'
+        
+      exitCode: 0
+  -
+    kind: "message-v1"
+    backtrace:
+      - "/usr/share/cmake-3.31/Modules/CMakeDetermineCompilerABI.cmake:182 (message)"
+      - "/usr/share/cmake-3.31/Modules/CMakeTestCXXCompiler.cmake:26 (CMAKE_DETERMINE_COMPILER_ABI)"
+      - "/home/abobkov/esp/v5.4.1/esp-idf/tools/cmake/project.cmake:571 (__project)"
+      - "CMakeLists.txt:67 (project)"
+    message: |
+      Parsed CXX implicit include dir info: rv=done
+        found start of include info
+        found start of implicit include info
+          add: [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/include/c++/14.2.0]
+          add: [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/include/c++/14.2.0/riscv32-esp-elf/rv32imc_zicsr_zifencei/ilp32]
+          add: [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/include/c++/14.2.0/backward]
+          add: [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/include]
+          add: [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/include-fixed]
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+        ignore line: [LIBRARY_PATH=/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/rv32imc_zicsr_zifencei/ilp32/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/lib/:/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/usr/lib/]
+        ignore line: [COLLECT_GCC_OPTIONS='-nostartfiles' '-march=rv32imc_zicsr_zifencei' '-specs=nosys.specs' '-v' '-o' 'cmTC_a5c8a' '-mabi=ilp32' '-misa-spec=20191213' '-march=rv32imc_zicsr_zifencei' '-dumpdir' 'cmTC_a5c8a.']
+        link line: [ /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../libexec/gcc/riscv32-esp-elf/14.2.0/collect2 -plugin /home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../libexec/gcc/riscv32-esp-elf/14.2.0/liblto_plugin.so -plugin-opt=/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../libexec/gcc/riscv32-esp-elf/14.2.0/lto-wrapper -plugin-opt=-fresolution=/tmp/ccuGxSzL.res -plugin-opt=-pass-through=-lgcc -plugin-opt=-pass-through=-lc -plugin-opt=-pass-through=-lnosys -plugin-opt=-pass-through=-lc -plugin-opt=-pass-through=-lgcc -plugin-opt=-pass-through=-lgcc -plugin-opt=-pass-through=-lc -plugin-opt=-pass-through=-lnosys --sysroot=/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf -melf32lriscv -X -o cmTC_a5c8a -L/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/rv32imc_zicsr_zifencei/ilp32 -L/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32 -L/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32 -L/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0 -L/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc -L/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib -L/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/lib -L/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/usr/lib CMakeFiles/cmTC_a5c8a.dir/CMakeCXXCompilerABI.cpp.obj -lstdc++ -lm -lgcc -lc -lnosys -lc -lgcc --start-group -lgcc -lc -lnosys --end-group]
+          arg [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../libexec/gcc/riscv32-esp-elf/14.2.0/collect2] ==> ignore
+          arg [-plugin] ==> ignore
+          arg [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../libexec/gcc/riscv32-esp-elf/14.2.0/liblto_plugin.so] ==> ignore
+          arg [-plugin-opt=/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../libexec/gcc/riscv32-esp-elf/14.2.0/lto-wrapper] ==> ignore
+          arg [-plugin-opt=-fresolution=/tmp/ccuGxSzL.res] ==> ignore
+          arg [-plugin-opt=-pass-through=-lgcc] ==> ignore
+          arg [-plugin-opt=-pass-through=-lc] ==> ignore
+          arg [-plugin-opt=-pass-through=-lnosys] ==> ignore
+          arg [-plugin-opt=-pass-through=-lc] ==> ignore
+          arg [-plugin-opt=-pass-through=-lgcc] ==> ignore
+          arg [-plugin-opt=-pass-through=-lgcc] ==> ignore
+          arg [-plugin-opt=-pass-through=-lc] ==> ignore
+          arg [-plugin-opt=-pass-through=-lnosys] ==> ignore
+          arg [--sysroot=/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf] ==> ignore
+          arg [-melf32lriscv] ==> ignore
+          arg [-X] ==> ignore
+          arg [-o] ==> ignore
+          arg [cmTC_a5c8a] ==> ignore
+          arg [-L/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/rv32imc_zicsr_zifencei/ilp32] ==> dir [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/rv32imc_zicsr_zifencei/ilp32]
+          arg [-L/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32] ==> dir [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32]
+          arg [-L/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32] ==> dir [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32]
+          arg [-L/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0] ==> dir [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0]
+          arg [-L/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc] ==> dir [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc]
+          arg [-L/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib] ==> dir [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib]
+          arg [-L/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/lib] ==> dir [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/lib]
+          arg [-L/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/usr/lib] ==> dir [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/usr/lib]
+          arg [CMakeFiles/cmTC_a5c8a.dir/CMakeCXXCompilerABI.cpp.obj] ==> ignore
+          arg [-lstdc++] ==> lib [stdc++]
+          arg [-lm] ==> lib [m]
+          arg [-lgcc] ==> lib [gcc]
+          arg [-lc] ==> lib [c]
+          arg [-lnosys] ==> lib [nosys]
+          arg [-lc] ==> lib [c]
+          arg [-lgcc] ==> lib [gcc]
+          arg [--start-group] ==> ignore
+          arg [-lgcc] ==> lib [gcc]
+          arg [-lc] ==> lib [c]
+          arg [-lnosys] ==> lib [nosys]
+          arg [--end-group] ==> ignore
+        ignore line: [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/bin/ld: warning: cannot find entry symbol _start]
+        ignore line: [ defaulting to 00010094]
+        ignore line: [COLLECT_GCC_OPTIONS='-nostartfiles' '-march=rv32imc_zicsr_zifencei' '-specs=nosys.specs' '-v' '-o' 'cmTC_a5c8a' '-mabi=ilp32' '-misa-spec=20191213' '-march=rv32imc_zicsr_zifencei' '-dumpdir' 'cmTC_a5c8a.']
+        ignore line: []
+        ignore line: []
+        collapse library dir [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/rv32imc_zicsr_zifencei/ilp32] ==> [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/lib/gcc/riscv32-esp-elf/14.2.0/rv32imc_zicsr_zifencei/ilp32]
+        collapse library dir [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32] ==> [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32]
+        collapse library dir [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32] ==> [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32]
+        collapse library dir [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0] ==> [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/lib/gcc/riscv32-esp-elf/14.2.0]
+        collapse library dir [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc] ==> [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/lib/gcc]
+        collapse library dir [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../lib/gcc/riscv32-esp-elf/14.2.0/../../../../riscv32-esp-elf/lib] ==> [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/riscv32-esp-elf/lib]
+        collapse library dir [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/lib] ==> [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/riscv32-esp-elf/lib]
+        collapse library dir [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/bin/../riscv32-esp-elf/usr/lib] ==> [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/riscv32-esp-elf/usr/lib]
+        implicit libs: [stdc++;m;gcc;c;nosys;c;gcc;gcc;c;nosys]
+        implicit objs: []
+        implicit dirs: [/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/lib/gcc/riscv32-esp-elf/14.2.0/rv32imc_zicsr_zifencei/ilp32;/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/riscv32-esp-elf/lib/rv32imc_zicsr_zifencei/ilp32;/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/lib/gcc/riscv32-esp-elf/14.2.0;/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/lib/gcc;/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/riscv32-esp-elf/lib;/home/abobkov/.espressif/tools/riscv32-esp-elf/esp-14.2.0_20241119/riscv32-esp-elf/riscv32-esp-elf/usr/lib]
+        implicit fwks: []
+      
+      
diff --git a/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/git-data/HEAD b/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/git-data/HEAD
new file mode 100644
index 000000000..b3440b61b
--- /dev/null
+++ b/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/git-data/HEAD
@@ -0,0 +1 @@
+4c2820d377d1375e787bcef612f0c32c1427d183
diff --git a/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/git-data/grabRef.cmake b/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/git-data/grabRef.cmake
new file mode 100644
index 000000000..2e22add75
--- /dev/null
+++ b/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/git-data/grabRef.cmake
@@ -0,0 +1,50 @@
+#
+# Internal file for GetGitRevisionDescription.cmake
+#
+# Requires CMake 2.6 or newer (uses the 'function' command)
+#
+# Original Author:
+# 2009-2010 Ryan Pavlik <rpavlik@iastate.edu> <abiryan@ryand.net>
+# http://academic.cleardefinition.com
+# Iowa State University HCI Graduate Program/VRAC
+#
+# Copyright Iowa State University 2009-2010.
+# Distributed under the Boost Software License, Version 1.0.
+# (See accompanying file LICENSE_1_0.txt or copy at
+# http://www.boost.org/LICENSE_1_0.txt)
+
+set(HEAD_HASH)
+
+file(READ "/home/abobkov/MyProjects/ESP-Nodes/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/git-data/HEAD" HEAD_CONTENTS LIMIT 1024)
+
+string(STRIP "${HEAD_CONTENTS}" HEAD_CONTENTS)
+set(GIT_DIR "/home/abobkov/esp/v5.4.1/esp-idf/.git")
+# handle git-worktree
+if(EXISTS "${GIT_DIR}/commondir")
+	file(READ "${GIT_DIR}/commondir" GIT_DIR_NEW LIMIT 1024)
+	string(STRIP "${GIT_DIR_NEW}" GIT_DIR_NEW)
+	if(NOT IS_ABSOLUTE "${GIT_DIR_NEW}")
+		get_filename_component(GIT_DIR_NEW ${GIT_DIR}/${GIT_DIR_NEW} ABSOLUTE)
+	endif()
+	if(EXISTS "${GIT_DIR_NEW}")
+		set(GIT_DIR "${GIT_DIR_NEW}")
+	endif()
+endif()
+if(HEAD_CONTENTS MATCHES "ref")
+	# named branch
+	string(REPLACE "ref: " "" HEAD_REF "${HEAD_CONTENTS}")
+	if(EXISTS "${GIT_DIR}/${HEAD_REF}")
+		configure_file("${GIT_DIR}/${HEAD_REF}" "/home/abobkov/MyProjects/ESP-Nodes/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/git-data/head-ref" COPYONLY)
+	elseif(EXISTS "${GIT_DIR}/logs/${HEAD_REF}")
+		configure_file("${GIT_DIR}/logs/${HEAD_REF}" "/home/abobkov/MyProjects/ESP-Nodes/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/git-data/head-ref" COPYONLY)
+		set(HEAD_HASH "${HEAD_REF}")
+	endif()
+else()
+	# detached HEAD
+	configure_file("${GIT_DIR}/HEAD" "/home/abobkov/MyProjects/ESP-Nodes/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/git-data/head-ref" COPYONLY)
+endif()
+
+if(NOT HEAD_HASH)
+	file(READ "/home/abobkov/MyProjects/ESP-Nodes/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/git-data/head-ref" HEAD_HASH LIMIT 1024)
+	string(STRIP "${HEAD_HASH}" HEAD_HASH)
+endif()
diff --git a/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/git-data/head-ref b/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/git-data/head-ref
new file mode 100644
index 000000000..b3440b61b
--- /dev/null
+++ b/ESP32-IDF_ESPNOW-Receiver/build/bootloader/CMakeFiles/git-data/head-ref
@@ -0,0 +1 @@
+4c2820d377d1375e787bcef612f0c32c1427d183
diff --git a/ESP32-IDF_ESPNOW-Receiver/build/bootloader/config.env b/ESP32-IDF_ESPNOW-Receiver/build/bootloader/config.env
new file mode 100644
index 000000000..b35857c65
--- /dev/null
+++ b/ESP32-IDF_ESPNOW-Receiver/build/bootloader/config.env
@@ -0,0 +1,12 @@
+{
+    "COMPONENT_KCONFIGS": "/home/abobkov/esp/v5.4.1/esp-idf/components/efuse/Kconfig;/home/abobkov/esp/v5.4.1/esp-idf/components/esp_common/Kconfig;/home/abobkov/esp/v5.4.1/esp-idf/components/esp_hw_support/Kconfig;/home/abobkov/esp/v5.4.1/esp-idf/components/esp_security/Kconfig;/home/abobkov/esp/v5.4.1/esp-idf/components/esp_system/Kconfig;/home/abobkov/esp/v5.4.1/esp-idf/components/freertos/Kconfig;/home/abobkov/esp/v5.4.1/esp-idf/components/hal/Kconfig;/home/abobkov/esp/v5.4.1/esp-idf/components/log/Kconfig;/home/abobkov/esp/v5.4.1/esp-idf/components/newlib/Kconfig;/home/abobkov/esp/v5.4.1/esp-idf/components/soc/Kconfig;/home/abobkov/esp/v5.4.1/esp-idf/components/spi_flash/Kconfig",
+    "COMPONENT_KCONFIGS_PROJBUILD": "/home/abobkov/esp/v5.4.1/esp-idf/components/bootloader/Kconfig.projbuild;/home/abobkov/esp/v5.4.1/esp-idf/components/esp_app_format/Kconfig.projbuild;/home/abobkov/esp/v5.4.1/esp-idf/components/esp_rom/Kconfig.projbuild;/home/abobkov/esp/v5.4.1/esp-idf/components/esptool_py/Kconfig.projbuild;/home/abobkov/esp/v5.4.1/esp-idf/components/partition_table/Kconfig.projbuild",
+    "COMPONENT_SDKCONFIG_RENAMES": "/home/abobkov/esp/v5.4.1/esp-idf/components/bootloader/sdkconfig.rename;/home/abobkov/esp/v5.4.1/esp-idf/components/esp_hw_support/sdkconfig.rename;/home/abobkov/esp/v5.4.1/esp-idf/components/esp_hw_support/sdkconfig.rename.esp32c3;/home/abobkov/esp/v5.4.1/esp-idf/components/esp_system/sdkconfig.rename;/home/abobkov/esp/v5.4.1/esp-idf/components/esp_system/sdkconfig.rename.esp32c3;/home/abobkov/esp/v5.4.1/esp-idf/components/esptool_py/sdkconfig.rename;/home/abobkov/esp/v5.4.1/esp-idf/components/freertos/sdkconfig.rename;/home/abobkov/esp/v5.4.1/esp-idf/components/hal/sdkconfig.rename;/home/abobkov/esp/v5.4.1/esp-idf/components/newlib/sdkconfig.rename.esp32c3;/home/abobkov/esp/v5.4.1/esp-idf/components/spi_flash/sdkconfig.rename",
+    "IDF_TARGET": "esp32c3",
+    "IDF_TOOLCHAIN": "gcc",
+    "IDF_VERSION": "5.4.1",
+    "IDF_ENV_FPGA": "",
+    "IDF_PATH": "/home/abobkov/esp/v5.4.1/esp-idf",
+    "COMPONENT_KCONFIGS_SOURCE_FILE": "/home/abobkov/MyProjects/ESP-Nodes/ESP32-IDF_ESPNOW-Receiver/build/bootloader/kconfigs.in",
+    "COMPONENT_KCONFIGS_PROJBUILD_SOURCE_FILE": "/home/abobkov/MyProjects/ESP-Nodes/ESP32-IDF_ESPNOW-Receiver/build/bootloader/kconfigs_projbuild.in"
+}
diff --git a/ESP32-IDF_ESPNOW-Receiver/build/bootloader/config/kconfig_menus.json b/ESP32-IDF_ESPNOW-Receiver/build/bootloader/config/kconfig_menus.json
new file mode 100644
index 000000000..c64a93aee
--- /dev/null
+++ b/ESP32-IDF_ESPNOW-Receiver/build/bootloader/config/kconfig_menus.json
@@ -0,0 +1,9991 @@
+[
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+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_ADC_SUPPORTED",
+        "name": "SOC_ADC_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_DEDICATED_GPIO_SUPPORTED",
+        "name": "SOC_DEDICATED_GPIO_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_UART_SUPPORTED",
+        "name": "SOC_UART_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
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+        "id": "SOC_GDMA_SUPPORTED",
+        "name": "SOC_GDMA_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
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+        "name": "SOC_AHB_GDMA_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
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+        "id": "SOC_GPTIMER_SUPPORTED",
+        "name": "SOC_GPTIMER_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
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+        "name": "SOC_TWAI_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
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+        "id": "SOC_BT_SUPPORTED",
+        "name": "SOC_BT_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
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+        "type": "bool"
+    },
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+        "id": "SOC_USB_SERIAL_JTAG_SUPPORTED",
+        "name": "SOC_USB_SERIAL_JTAG_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
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+        "id": "SOC_TEMP_SENSOR_SUPPORTED",
+        "name": "SOC_TEMP_SENSOR_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
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+        "name": "SOC_XT_WDT_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
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+        "id": "SOC_PHY_SUPPORTED",
+        "name": "SOC_PHY_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
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+        "help": null,
+        "id": "SOC_WIFI_SUPPORTED",
+        "name": "SOC_WIFI_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SUPPORTS_SECURE_DL_MODE",
+        "name": "SOC_SUPPORTS_SECURE_DL_MODE",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_EFUSE_KEY_PURPOSE_FIELD",
+        "name": "SOC_EFUSE_KEY_PURPOSE_FIELD",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
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+        "depends_on": null,
+        "help": null,
+        "id": "SOC_EFUSE_HAS_EFUSE_RST_BUG",
+        "name": "SOC_EFUSE_HAS_EFUSE_RST_BUG",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
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+        "depends_on": null,
+        "help": null,
+        "id": "SOC_EFUSE_SUPPORTED",
+        "name": "SOC_EFUSE_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_RTC_FAST_MEM_SUPPORTED",
+        "name": "SOC_RTC_FAST_MEM_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
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+        "id": "SOC_RTC_MEM_SUPPORTED",
+        "name": "SOC_RTC_MEM_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_I2S_SUPPORTED",
+        "name": "SOC_I2S_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_RMT_SUPPORTED",
+        "name": "SOC_RMT_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SDM_SUPPORTED",
+        "name": "SOC_SDM_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_GPSPI_SUPPORTED",
+        "name": "SOC_GPSPI_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_LEDC_SUPPORTED",
+        "name": "SOC_LEDC_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_I2C_SUPPORTED",
+        "name": "SOC_I2C_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SYSTIMER_SUPPORTED",
+        "name": "SOC_SYSTIMER_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
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+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SUPPORT_COEXISTENCE",
+        "name": "SOC_SUPPORT_COEXISTENCE",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_AES_SUPPORTED",
+        "name": "SOC_AES_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_MPI_SUPPORTED",
+        "name": "SOC_MPI_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SHA_SUPPORTED",
+        "name": "SOC_SHA_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_HMAC_SUPPORTED",
+        "name": "SOC_HMAC_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_DIG_SIGN_SUPPORTED",
+        "name": "SOC_DIG_SIGN_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_FLASH_ENC_SUPPORTED",
+        "name": "SOC_FLASH_ENC_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SECURE_BOOT_SUPPORTED",
+        "name": "SOC_SECURE_BOOT_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
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+        "id": "SOC_MEMPROT_SUPPORTED",
+        "name": "SOC_MEMPROT_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_BOD_SUPPORTED",
+        "name": "SOC_BOD_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_CLK_TREE_SUPPORTED",
+        "name": "SOC_CLK_TREE_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_ASSIST_DEBUG_SUPPORTED",
+        "name": "SOC_ASSIST_DEBUG_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_WDT_SUPPORTED",
+        "name": "SOC_WDT_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SPI_FLASH_SUPPORTED",
+        "name": "SOC_SPI_FLASH_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_RNG_SUPPORTED",
+        "name": "SOC_RNG_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_LIGHT_SLEEP_SUPPORTED",
+        "name": "SOC_LIGHT_SLEEP_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_DEEP_SLEEP_SUPPORTED",
+        "name": "SOC_DEEP_SLEEP_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_LP_PERIPH_SHARE_INTERRUPT",
+        "name": "SOC_LP_PERIPH_SHARE_INTERRUPT",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_PM_SUPPORTED",
+        "name": "SOC_PM_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_XTAL_SUPPORT_40M",
+        "name": "SOC_XTAL_SUPPORT_40M",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_AES_SUPPORT_DMA",
+        "name": "SOC_AES_SUPPORT_DMA",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_AES_GDMA",
+        "name": "SOC_AES_GDMA",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_AES_SUPPORT_AES_128",
+        "name": "SOC_AES_SUPPORT_AES_128",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_AES_SUPPORT_AES_256",
+        "name": "SOC_AES_SUPPORT_AES_256",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_ADC_DIG_CTRL_SUPPORTED",
+        "name": "SOC_ADC_DIG_CTRL_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_ADC_ARBITER_SUPPORTED",
+        "name": "SOC_ADC_ARBITER_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_ADC_DIG_IIR_FILTER_SUPPORTED",
+        "name": "SOC_ADC_DIG_IIR_FILTER_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_ADC_MONITOR_SUPPORTED",
+        "name": "SOC_ADC_MONITOR_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_ADC_DMA_SUPPORTED",
+        "name": "SOC_ADC_DMA_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_ADC_PERIPH_NUM",
+        "name": "SOC_ADC_PERIPH_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_ADC_MAX_CHANNEL_NUM",
+        "name": "SOC_ADC_MAX_CHANNEL_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_ADC_ATTEN_NUM",
+        "name": "SOC_ADC_ATTEN_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_ADC_DIGI_CONTROLLER_NUM",
+        "name": "SOC_ADC_DIGI_CONTROLLER_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_ADC_PATT_LEN_MAX",
+        "name": "SOC_ADC_PATT_LEN_MAX",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_ADC_DIGI_MIN_BITWIDTH",
+        "name": "SOC_ADC_DIGI_MIN_BITWIDTH",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_ADC_DIGI_MAX_BITWIDTH",
+        "name": "SOC_ADC_DIGI_MAX_BITWIDTH",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_ADC_DIGI_RESULT_BYTES",
+        "name": "SOC_ADC_DIGI_RESULT_BYTES",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_ADC_DIGI_DATA_BYTES_PER_CONV",
+        "name": "SOC_ADC_DIGI_DATA_BYTES_PER_CONV",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_ADC_DIGI_IIR_FILTER_NUM",
+        "name": "SOC_ADC_DIGI_IIR_FILTER_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_ADC_DIGI_MONITOR_NUM",
+        "name": "SOC_ADC_DIGI_MONITOR_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
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+        "id": "SOC_ADC_SAMPLE_FREQ_THRES_HIGH",
+        "name": "SOC_ADC_SAMPLE_FREQ_THRES_HIGH",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_ADC_SAMPLE_FREQ_THRES_LOW",
+        "name": "SOC_ADC_SAMPLE_FREQ_THRES_LOW",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_ADC_RTC_MIN_BITWIDTH",
+        "name": "SOC_ADC_RTC_MIN_BITWIDTH",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_ADC_RTC_MAX_BITWIDTH",
+        "name": "SOC_ADC_RTC_MAX_BITWIDTH",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_ADC_CALIBRATION_V1_SUPPORTED",
+        "name": "SOC_ADC_CALIBRATION_V1_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_ADC_SELF_HW_CALI_SUPPORTED",
+        "name": "SOC_ADC_SELF_HW_CALI_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_ADC_SHARED_POWER",
+        "name": "SOC_ADC_SHARED_POWER",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_APB_BACKUP_DMA",
+        "name": "SOC_APB_BACKUP_DMA",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_BROWNOUT_RESET_SUPPORTED",
+        "name": "SOC_BROWNOUT_RESET_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
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+        "name": "SOC_SHARED_IDCACHE_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
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+        "range": null,
+        "title": null,
+        "type": "hex"
+    },
+    {
+        "children": [],
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+        "name": "SOC_CPU_CORES_NUM",
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+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
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+        "name": "SOC_CPU_INTR_NUM",
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+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
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+        "name": "SOC_CPU_HAS_FLEXIBLE_INTC",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
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+        "id": "SOC_CPU_HAS_CSR_PC",
+        "name": "SOC_CPU_HAS_CSR_PC",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
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+        "id": "SOC_CPU_BREAKPOINTS_NUM",
+        "name": "SOC_CPU_BREAKPOINTS_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
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+        "id": "SOC_CPU_WATCHPOINTS_NUM",
+        "name": "SOC_CPU_WATCHPOINTS_NUM",
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+        "title": null,
+        "type": "int"
+    },
+    {
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+        "range": null,
+        "title": null,
+        "type": "hex"
+    },
+    {
+        "children": [],
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+        "title": null,
+        "type": "int"
+    },
+    {
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+        "title": null,
+        "type": "int"
+    },
+    {
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+        "name": "SOC_DS_KEY_CHECK_MAX_WAIT_US",
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+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
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+        "name": "SOC_AHB_GDMA_VERSION",
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+        "title": null,
+        "type": "int"
+    },
+    {
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+        "name": "SOC_GDMA_NUM_GROUPS_MAX",
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+        "type": "int"
+    },
+    {
+        "children": [],
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+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
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+        "name": "SOC_GPIO_PORT",
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+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
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+        "title": null,
+        "type": "int"
+    },
+    {
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+        "title": null,
+        "type": "bool"
+    },
+    {
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+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
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+        "title": null,
+        "type": "bool"
+    },
+    {
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+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
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+        "name": "SOC_GPIO_IN_RANGE_MAX",
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+        "title": null,
+        "type": "int"
+    },
+    {
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+        "title": null,
+        "type": "int"
+    },
+    {
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+        "id": "SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK",
+        "name": "SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
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+        "name": "SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
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+        "name": "SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK",
+        "range": null,
+        "title": null,
+        "type": "hex"
+    },
+    {
+        "children": [],
+        "depends_on": null,
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+        "name": "SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
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+        "id": "SOC_GPIO_CLOCKOUT_CHANNEL_NUM",
+        "name": "SOC_GPIO_CLOCKOUT_CHANNEL_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
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+        "name": "SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_DEDIC_GPIO_OUT_CHANNELS_NUM",
+        "name": "SOC_DEDIC_GPIO_OUT_CHANNELS_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
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+        "id": "SOC_DEDIC_GPIO_IN_CHANNELS_NUM",
+        "name": "SOC_DEDIC_GPIO_IN_CHANNELS_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
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+        "name": "SOC_DEDIC_PERIPH_ALWAYS_ENABLE",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
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+        "id": "SOC_I2C_NUM",
+        "name": "SOC_I2C_NUM",
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+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
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+        "id": "SOC_HP_I2C_NUM",
+        "name": "SOC_HP_I2C_NUM",
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+        "title": null,
+        "type": "int"
+    },
+    {
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+        "title": null,
+        "type": "int"
+    },
+    {
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+        "name": "SOC_I2C_CMD_REG_NUM",
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+        "title": null,
+        "type": "int"
+    },
+    {
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+        "name": "SOC_I2C_SUPPORT_SLAVE",
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+        "title": null,
+        "type": "bool"
+    },
+    {
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+        "name": "SOC_I2C_SUPPORT_HW_CLR_BUS",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
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+        "id": "SOC_I2C_SUPPORT_XTAL",
+        "name": "SOC_I2C_SUPPORT_XTAL",
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+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
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+        "id": "SOC_I2C_SUPPORT_RTC",
+        "name": "SOC_I2C_SUPPORT_RTC",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
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+        "id": "SOC_I2C_SUPPORT_10BIT_ADDR",
+        "name": "SOC_I2C_SUPPORT_10BIT_ADDR",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
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+        "name": "SOC_I2C_SLAVE_SUPPORT_BROADCAST",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
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+        "name": "SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
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+        "name": "SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
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+        "id": "SOC_I2S_NUM",
+        "name": "SOC_I2S_NUM",
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+        "title": null,
+        "type": "int"
+    },
+    {
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+        "name": "SOC_I2S_HW_VERSION_2",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
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+        "name": "SOC_I2S_SUPPORTS_XTAL",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
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+        "id": "SOC_I2S_SUPPORTS_PLL_F160M",
+        "name": "SOC_I2S_SUPPORTS_PLL_F160M",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
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+        "id": "SOC_I2S_SUPPORTS_PCM",
+        "name": "SOC_I2S_SUPPORTS_PCM",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
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+        "id": "SOC_I2S_SUPPORTS_PDM",
+        "name": "SOC_I2S_SUPPORTS_PDM",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
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+        "id": "SOC_I2S_SUPPORTS_PDM_TX",
+        "name": "SOC_I2S_SUPPORTS_PDM_TX",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
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+        "name": "SOC_I2S_PDM_MAX_TX_LINES",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
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+        "id": "SOC_I2S_SUPPORTS_TDM",
+        "name": "SOC_I2S_SUPPORTS_TDM",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
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+        "id": "SOC_LEDC_SUPPORT_APB_CLOCK",
+        "name": "SOC_LEDC_SUPPORT_APB_CLOCK",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
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+        "id": "SOC_LEDC_SUPPORT_XTAL_CLOCK",
+        "name": "SOC_LEDC_SUPPORT_XTAL_CLOCK",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
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+        "id": "SOC_LEDC_TIMER_NUM",
+        "name": "SOC_LEDC_TIMER_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
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+        "help": null,
+        "id": "SOC_LEDC_CHANNEL_NUM",
+        "name": "SOC_LEDC_CHANNEL_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_LEDC_TIMER_BIT_WIDTH",
+        "name": "SOC_LEDC_TIMER_BIT_WIDTH",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_LEDC_SUPPORT_FADE_STOP",
+        "name": "SOC_LEDC_SUPPORT_FADE_STOP",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_MMU_LINEAR_ADDRESS_REGION_NUM",
+        "name": "SOC_MMU_LINEAR_ADDRESS_REGION_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_MMU_PERIPH_NUM",
+        "name": "SOC_MMU_PERIPH_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED",
+        "name": "SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
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+        "id": "SOC_MPU_MIN_REGION_SIZE",
+        "name": "SOC_MPU_MIN_REGION_SIZE",
+        "range": null,
+        "title": null,
+        "type": "hex"
+    },
+    {
+        "children": [],
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+        "help": null,
+        "id": "SOC_MPU_REGIONS_MAX_NUM",
+        "name": "SOC_MPU_REGIONS_MAX_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
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+        "id": "SOC_MPU_REGION_RO_SUPPORTED",
+        "name": "SOC_MPU_REGION_RO_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_MPU_REGION_WO_SUPPORTED",
+        "name": "SOC_MPU_REGION_WO_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_RMT_GROUPS",
+        "name": "SOC_RMT_GROUPS",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_RMT_TX_CANDIDATES_PER_GROUP",
+        "name": "SOC_RMT_TX_CANDIDATES_PER_GROUP",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_RMT_RX_CANDIDATES_PER_GROUP",
+        "name": "SOC_RMT_RX_CANDIDATES_PER_GROUP",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_RMT_CHANNELS_PER_GROUP",
+        "name": "SOC_RMT_CHANNELS_PER_GROUP",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_RMT_MEM_WORDS_PER_CHANNEL",
+        "name": "SOC_RMT_MEM_WORDS_PER_CHANNEL",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_RMT_SUPPORT_RX_PINGPONG",
+        "name": "SOC_RMT_SUPPORT_RX_PINGPONG",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_RMT_SUPPORT_RX_DEMODULATION",
+        "name": "SOC_RMT_SUPPORT_RX_DEMODULATION",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_RMT_SUPPORT_TX_ASYNC_STOP",
+        "name": "SOC_RMT_SUPPORT_TX_ASYNC_STOP",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_RMT_SUPPORT_TX_LOOP_COUNT",
+        "name": "SOC_RMT_SUPPORT_TX_LOOP_COUNT",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_RMT_SUPPORT_TX_SYNCHRO",
+        "name": "SOC_RMT_SUPPORT_TX_SYNCHRO",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY",
+        "name": "SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_RMT_SUPPORT_XTAL",
+        "name": "SOC_RMT_SUPPORT_XTAL",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_RMT_SUPPORT_APB",
+        "name": "SOC_RMT_SUPPORT_APB",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_RMT_SUPPORT_RC_FAST",
+        "name": "SOC_RMT_SUPPORT_RC_FAST",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH",
+        "name": "SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM",
+        "name": "SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SLEEP_SYSTIMER_STALL_WORKAROUND",
+        "name": "SOC_SLEEP_SYSTIMER_STALL_WORKAROUND",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SLEEP_TGWDT_STOP_WORKAROUND",
+        "name": "SOC_SLEEP_TGWDT_STOP_WORKAROUND",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_RTCIO_PIN_COUNT",
+        "name": "SOC_RTCIO_PIN_COUNT",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_MPI_MEM_BLOCKS_NUM",
+        "name": "SOC_MPI_MEM_BLOCKS_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_MPI_OPERATIONS_NUM",
+        "name": "SOC_MPI_OPERATIONS_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_RSA_MAX_BIT_LEN",
+        "name": "SOC_RSA_MAX_BIT_LEN",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SHA_DMA_MAX_BUFFER_SIZE",
+        "name": "SOC_SHA_DMA_MAX_BUFFER_SIZE",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SHA_SUPPORT_DMA",
+        "name": "SOC_SHA_SUPPORT_DMA",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SHA_SUPPORT_RESUME",
+        "name": "SOC_SHA_SUPPORT_RESUME",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SHA_GDMA",
+        "name": "SOC_SHA_GDMA",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SHA_SUPPORT_SHA1",
+        "name": "SOC_SHA_SUPPORT_SHA1",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SHA_SUPPORT_SHA224",
+        "name": "SOC_SHA_SUPPORT_SHA224",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SHA_SUPPORT_SHA256",
+        "name": "SOC_SHA_SUPPORT_SHA256",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SDM_GROUPS",
+        "name": "SOC_SDM_GROUPS",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SDM_CHANNELS_PER_GROUP",
+        "name": "SOC_SDM_CHANNELS_PER_GROUP",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SDM_CLK_SUPPORT_APB",
+        "name": "SOC_SDM_CLK_SUPPORT_APB",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SPI_PERIPH_NUM",
+        "name": "SOC_SPI_PERIPH_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SPI_MAX_CS_NUM",
+        "name": "SOC_SPI_MAX_CS_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SPI_MAXIMUM_BUFFER_SIZE",
+        "name": "SOC_SPI_MAXIMUM_BUFFER_SIZE",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SPI_SUPPORT_DDRCLK",
+        "name": "SOC_SPI_SUPPORT_DDRCLK",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SPI_SLAVE_SUPPORT_SEG_TRANS",
+        "name": "SOC_SPI_SLAVE_SUPPORT_SEG_TRANS",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SPI_SUPPORT_CD_SIG",
+        "name": "SOC_SPI_SUPPORT_CD_SIG",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SPI_SUPPORT_CONTINUOUS_TRANS",
+        "name": "SOC_SPI_SUPPORT_CONTINUOUS_TRANS",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SPI_SUPPORT_SLAVE_HD_VER2",
+        "name": "SOC_SPI_SUPPORT_SLAVE_HD_VER2",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SPI_SUPPORT_CLK_APB",
+        "name": "SOC_SPI_SUPPORT_CLK_APB",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SPI_SUPPORT_CLK_XTAL",
+        "name": "SOC_SPI_SUPPORT_CLK_XTAL",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT",
+        "name": "SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SPI_SCT_SUPPORTED",
+        "name": "SOC_SPI_SCT_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SPI_SCT_REG_NUM",
+        "name": "SOC_SPI_SCT_REG_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SPI_SCT_BUFFER_NUM_MAX",
+        "name": "SOC_SPI_SCT_BUFFER_NUM_MAX",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SPI_SCT_CONF_BITLEN_MAX",
+        "name": "SOC_SPI_SCT_CONF_BITLEN_MAX",
+        "range": null,
+        "title": null,
+        "type": "hex"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_MEMSPI_IS_INDEPENDENT",
+        "name": "SOC_MEMSPI_IS_INDEPENDENT",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SPI_MAX_PRE_DIVIDER",
+        "name": "SOC_SPI_MAX_PRE_DIVIDER",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE",
+        "name": "SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND",
+        "name": "SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SPI_MEM_SUPPORT_AUTO_RESUME",
+        "name": "SOC_SPI_MEM_SUPPORT_AUTO_RESUME",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SPI_MEM_SUPPORT_IDLE_INTR",
+        "name": "SOC_SPI_MEM_SUPPORT_IDLE_INTR",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SPI_MEM_SUPPORT_SW_SUSPEND",
+        "name": "SOC_SPI_MEM_SUPPORT_SW_SUSPEND",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SPI_MEM_SUPPORT_CHECK_SUS",
+        "name": "SOC_SPI_MEM_SUPPORT_CHECK_SUS",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE",
+        "name": "SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SPI_MEM_SUPPORT_WRAP",
+        "name": "SOC_SPI_MEM_SUPPORT_WRAP",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED",
+        "name": "SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED",
+        "name": "SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED",
+        "name": "SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED",
+        "name": "SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SYSTIMER_COUNTER_NUM",
+        "name": "SOC_SYSTIMER_COUNTER_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SYSTIMER_ALARM_NUM",
+        "name": "SOC_SYSTIMER_ALARM_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SYSTIMER_BIT_WIDTH_LO",
+        "name": "SOC_SYSTIMER_BIT_WIDTH_LO",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SYSTIMER_BIT_WIDTH_HI",
+        "name": "SOC_SYSTIMER_BIT_WIDTH_HI",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SYSTIMER_FIXED_DIVIDER",
+        "name": "SOC_SYSTIMER_FIXED_DIVIDER",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SYSTIMER_INT_LEVEL",
+        "name": "SOC_SYSTIMER_INT_LEVEL",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SYSTIMER_ALARM_MISS_COMPENSATE",
+        "name": "SOC_SYSTIMER_ALARM_MISS_COMPENSATE",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_TIMER_GROUPS",
+        "name": "SOC_TIMER_GROUPS",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_TIMER_GROUP_TIMERS_PER_GROUP",
+        "name": "SOC_TIMER_GROUP_TIMERS_PER_GROUP",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_TIMER_GROUP_COUNTER_BIT_WIDTH",
+        "name": "SOC_TIMER_GROUP_COUNTER_BIT_WIDTH",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_TIMER_GROUP_SUPPORT_XTAL",
+        "name": "SOC_TIMER_GROUP_SUPPORT_XTAL",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_TIMER_GROUP_SUPPORT_APB",
+        "name": "SOC_TIMER_GROUP_SUPPORT_APB",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_TIMER_GROUP_TOTAL_TIMERS",
+        "name": "SOC_TIMER_GROUP_TOTAL_TIMERS",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_LP_TIMER_BIT_WIDTH_LO",
+        "name": "SOC_LP_TIMER_BIT_WIDTH_LO",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_LP_TIMER_BIT_WIDTH_HI",
+        "name": "SOC_LP_TIMER_BIT_WIDTH_HI",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_MWDT_SUPPORT_XTAL",
+        "name": "SOC_MWDT_SUPPORT_XTAL",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_TWAI_CONTROLLER_NUM",
+        "name": "SOC_TWAI_CONTROLLER_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_TWAI_CLK_SUPPORT_APB",
+        "name": "SOC_TWAI_CLK_SUPPORT_APB",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_TWAI_BRP_MIN",
+        "name": "SOC_TWAI_BRP_MIN",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_TWAI_BRP_MAX",
+        "name": "SOC_TWAI_BRP_MAX",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_TWAI_SUPPORTS_RX_STATUS",
+        "name": "SOC_TWAI_SUPPORTS_RX_STATUS",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_EFUSE_DIS_DOWNLOAD_ICACHE",
+        "name": "SOC_EFUSE_DIS_DOWNLOAD_ICACHE",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_EFUSE_DIS_PAD_JTAG",
+        "name": "SOC_EFUSE_DIS_PAD_JTAG",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_EFUSE_DIS_USB_JTAG",
+        "name": "SOC_EFUSE_DIS_USB_JTAG",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_EFUSE_DIS_DIRECT_BOOT",
+        "name": "SOC_EFUSE_DIS_DIRECT_BOOT",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_EFUSE_SOFT_DIS_JTAG",
+        "name": "SOC_EFUSE_SOFT_DIS_JTAG",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_EFUSE_DIS_ICACHE",
+        "name": "SOC_EFUSE_DIS_ICACHE",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK",
+        "name": "SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SECURE_BOOT_V2_RSA",
+        "name": "SOC_SECURE_BOOT_V2_RSA",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS",
+        "name": "SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS",
+        "name": "SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY",
+        "name": "SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX",
+        "name": "SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_FLASH_ENCRYPTION_XTS_AES",
+        "name": "SOC_FLASH_ENCRYPTION_XTS_AES",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_FLASH_ENCRYPTION_XTS_AES_128",
+        "name": "SOC_FLASH_ENCRYPTION_XTS_AES_128",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE",
+        "name": "SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_MEMPROT_MEM_ALIGN_SIZE",
+        "name": "SOC_MEMPROT_MEM_ALIGN_SIZE",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_UART_NUM",
+        "name": "SOC_UART_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_UART_HP_NUM",
+        "name": "SOC_UART_HP_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_UART_FIFO_LEN",
+        "name": "SOC_UART_FIFO_LEN",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_UART_BITRATE_MAX",
+        "name": "SOC_UART_BITRATE_MAX",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_UART_SUPPORT_APB_CLK",
+        "name": "SOC_UART_SUPPORT_APB_CLK",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_UART_SUPPORT_RTC_CLK",
+        "name": "SOC_UART_SUPPORT_RTC_CLK",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_UART_SUPPORT_XTAL_CLK",
+        "name": "SOC_UART_SUPPORT_XTAL_CLK",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_UART_SUPPORT_WAKEUP_INT",
+        "name": "SOC_UART_SUPPORT_WAKEUP_INT",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_UART_SUPPORT_FSM_TX_WAIT_SEND",
+        "name": "SOC_UART_SUPPORT_FSM_TX_WAIT_SEND",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_COEX_HW_PTI",
+        "name": "SOC_COEX_HW_PTI",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_EXTERNAL_COEX_ADVANCE",
+        "name": "SOC_EXTERNAL_COEX_ADVANCE",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_EXTERNAL_COEX_LEADER_TX_LINE",
+        "name": "SOC_EXTERNAL_COEX_LEADER_TX_LINE",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_PHY_DIG_REGS_MEM_SIZE",
+        "name": "SOC_PHY_DIG_REGS_MEM_SIZE",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_MAC_BB_PD_MEM_SIZE",
+        "name": "SOC_MAC_BB_PD_MEM_SIZE",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH",
+        "name": "SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_PM_SUPPORT_WIFI_WAKEUP",
+        "name": "SOC_PM_SUPPORT_WIFI_WAKEUP",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_PM_SUPPORT_BT_WAKEUP",
+        "name": "SOC_PM_SUPPORT_BT_WAKEUP",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_PM_SUPPORT_CPU_PD",
+        "name": "SOC_PM_SUPPORT_CPU_PD",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_PM_SUPPORT_WIFI_PD",
+        "name": "SOC_PM_SUPPORT_WIFI_PD",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_PM_SUPPORT_BT_PD",
+        "name": "SOC_PM_SUPPORT_BT_PD",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_PM_SUPPORT_RC_FAST_PD",
+        "name": "SOC_PM_SUPPORT_RC_FAST_PD",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_PM_SUPPORT_VDDSDIO_PD",
+        "name": "SOC_PM_SUPPORT_VDDSDIO_PD",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_PM_SUPPORT_MAC_BB_PD",
+        "name": "SOC_PM_SUPPORT_MAC_BB_PD",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_PM_CPU_RETENTION_BY_RTCCNTL",
+        "name": "SOC_PM_CPU_RETENTION_BY_RTCCNTL",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_PM_MODEM_RETENTION_BY_BACKUPDMA",
+        "name": "SOC_PM_MODEM_RETENTION_BY_BACKUPDMA",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_PM_MODEM_PD_BY_SW",
+        "name": "SOC_PM_MODEM_PD_BY_SW",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_CLK_RC_FAST_D256_SUPPORTED",
+        "name": "SOC_CLK_RC_FAST_D256_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256",
+        "name": "SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_CLK_RC_FAST_SUPPORT_CALIBRATION",
+        "name": "SOC_CLK_RC_FAST_SUPPORT_CALIBRATION",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_CLK_XTAL32K_SUPPORTED",
+        "name": "SOC_CLK_XTAL32K_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC",
+        "name": "SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL",
+        "name": "SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_WIFI_HW_TSF",
+        "name": "SOC_WIFI_HW_TSF",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_WIFI_FTM_SUPPORT",
+        "name": "SOC_WIFI_FTM_SUPPORT",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_WIFI_GCMP_SUPPORT",
+        "name": "SOC_WIFI_GCMP_SUPPORT",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_WIFI_WAPI_SUPPORT",
+        "name": "SOC_WIFI_WAPI_SUPPORT",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_WIFI_CSI_SUPPORT",
+        "name": "SOC_WIFI_CSI_SUPPORT",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_WIFI_MESH_SUPPORT",
+        "name": "SOC_WIFI_MESH_SUPPORT",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW",
+        "name": "SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_WIFI_PHY_NEEDS_USB_WORKAROUND",
+        "name": "SOC_WIFI_PHY_NEEDS_USB_WORKAROUND",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_BLE_SUPPORTED",
+        "name": "SOC_BLE_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_BLE_MESH_SUPPORTED",
+        "name": "SOC_BLE_MESH_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_BLE_50_SUPPORTED",
+        "name": "SOC_BLE_50_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_BLE_DEVICE_PRIVACY_SUPPORTED",
+        "name": "SOC_BLE_DEVICE_PRIVACY_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_BLUFI_SUPPORTED",
+        "name": "SOC_BLUFI_SUPPORTED",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "SOC_PHY_COMBO_MODULE",
+        "name": "SOC_PHY_COMBO_MODULE",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "IDF_CMAKE",
+        "name": "IDF_CMAKE",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": "- This option is for internal use only.\n- Enabling this option will help enable all FPGA support so as to\n  run ESP-IDF on an FPGA. This can help reproduce some issues that\n  only happens on FPGA condition, or when you have to burn some\n  efuses multiple times.",
+        "id": "IDF_ENV_FPGA",
+        "name": "IDF_ENV_FPGA",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": "- This option is ONLY used when doing new chip bringup.\n- This option will only enable necessary hw / sw settings for running\n  a hello_world application.",
+        "id": "IDF_ENV_BRINGUP",
+        "name": "IDF_ENV_BRINGUP",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "IDF_CI_BUILD",
+        "name": "IDF_CI_BUILD",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "IDF_DOC_BUILD",
+        "name": "IDF_DOC_BUILD",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "IDF_TOOLCHAIN",
+        "name": "IDF_TOOLCHAIN",
+        "range": null,
+        "title": null,
+        "type": "string"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "IDF_TOOLCHAIN_CLANG",
+        "name": "IDF_TOOLCHAIN_CLANG",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "IDF_TOOLCHAIN_GCC",
+        "name": "IDF_TOOLCHAIN_GCC",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "IDF_TARGET_ARCH_RISCV",
+        "name": "IDF_TARGET_ARCH_RISCV",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "IDF_TARGET_ARCH_XTENSA",
+        "name": "IDF_TARGET_ARCH_XTENSA",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "IDF_TARGET_ARCH",
+        "name": "IDF_TARGET_ARCH",
+        "range": null,
+        "title": null,
+        "type": "string"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "IDF_TARGET",
+        "name": "IDF_TARGET",
+        "range": null,
+        "title": null,
+        "type": "string"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "IDF_INIT_VERSION",
+        "name": "IDF_INIT_VERSION",
+        "range": null,
+        "title": null,
+        "type": "string"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "IDF_TARGET_ESP32",
+        "name": "IDF_TARGET_ESP32",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "IDF_TARGET_ESP32S2",
+        "name": "IDF_TARGET_ESP32S2",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "IDF_TARGET_ESP32S3",
+        "name": "IDF_TARGET_ESP32S3",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "IDF_TARGET_ESP32C3",
+        "name": "IDF_TARGET_ESP32C3",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "IDF_TARGET_ESP32C2",
+        "name": "IDF_TARGET_ESP32C2",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "IDF_TARGET_ESP32C6",
+        "name": "IDF_TARGET_ESP32C6",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "IDF_TARGET_ESP32C5",
+        "name": "IDF_TARGET_ESP32C5",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "IDF_TARGET_ESP32P4",
+        "name": "IDF_TARGET_ESP32P4",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "IDF_TARGET_ESP32H2",
+        "name": "IDF_TARGET_ESP32H2",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "IDF_TARGET_ESP32C61",
+        "name": "IDF_TARGET_ESP32C61",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "IDF_TARGET_LINUX",
+        "name": "IDF_TARGET_LINUX",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "IDF_FIRMWARE_CHIP_ID",
+        "name": "IDF_FIRMWARE_CHIP_ID",
+        "range": null,
+        "title": null,
+        "type": "hex"
+    },
+    {
+        "children": [
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "!IDF_TARGET_LINUX && <choice APP_BUILD_TYPE>",
+                        "help": null,
+                        "id": "APP_BUILD_TYPE_APP_2NDBOOT",
+                        "name": "APP_BUILD_TYPE_APP_2NDBOOT",
+                        "range": null,
+                        "title": "Default (binary application + 2nd stage bootloader)",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice APP_BUILD_TYPE>",
+                        "help": null,
+                        "id": "APP_BUILD_TYPE_RAM",
+                        "name": "APP_BUILD_TYPE_RAM",
+                        "range": null,
+                        "title": "Build app runs entirely in RAM (EXPERIMENTAL)",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": null,
+                "help": "Select the way the application is built.\n\nBy default, the application is built as a binary file in a format compatible with\nthe ESP-IDF bootloader. In addition to this application, 2nd stage bootloader is\nalso built. Application and bootloader binaries can be written into flash and\nloaded/executed from there.\n\nAnother option, useful for only very small and limited applications, is to only link\nthe .elf file of the application, such that it can be loaded directly into RAM over\nJTAG or UART. Note that since IRAM and DRAM sizes are very limited, it is not possible\nto build any complex application this way. However for some kinds of testing and debugging,\nthis option may provide faster iterations, since the application does not need to be\nwritten into flash.\n\nNote: when APP_BUILD_TYPE_RAM is selected and loaded with JTAG, ESP-IDF does not contain\nall the startup code required to initialize the CPUs and ROM memory (data/bss).\nTherefore it is necessary to execute a bit of ROM code prior to executing the application.\nA gdbinit file may look as follows (for ESP32):\n\n    # Connect to a running instance of OpenOCD\n    target remote :3333\n    # Reset and halt the target\n    mon reset halt\n    # Run to a specific point in ROM code,\n    #  where most of initialization is complete.\n    thb *0x40007d54\n    c\n    # Load the application into RAM\n    load\n    # Run till app_main\n    tb app_main\n    c\n\nExecute this gdbinit file as follows:\n\n    xtensa-esp32-elf-gdb build/app-name.elf -x gdbinit\n\nExample gdbinit files for other targets can be found in tools/test_apps/system/gdb_loadable_elf/\n\nWhen loading the BIN with UART, the ROM will jump to ram and run the app after finishing the ROM\nstartup code, so there's no additional startup initialization required. You can use the\n`load_ram` in esptool.py to load the generated .bin file into ram and execute.\n\nExample:\n    esptool.py --chip {chip} -p {port} -b {baud} --no-stub load_ram {app.bin}\n\nRecommended sdkconfig.defaults for building loadable ELF files is as follows.\nCONFIG_APP_BUILD_TYPE_RAM is required, other options help reduce application\nmemory footprint.\n\n    CONFIG_APP_BUILD_TYPE_RAM=y\n    CONFIG_VFS_SUPPORT_TERMIOS=\n    CONFIG_NEWLIB_NANO_FORMAT=y\n    CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT=y\n    CONFIG_ESP_DEBUG_STUBS_ENABLE=\n    CONFIG_ESP_ERR_TO_NAME_LOOKUP=",
+                "id": "build-type-application-build-type",
+                "name": "APP_BUILD_TYPE",
+                "title": "Application build type",
+                "type": "choice"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": null,
+                "id": "APP_BUILD_GENERATE_BINARIES",
+                "name": "APP_BUILD_GENERATE_BINARIES",
+                "range": null,
+                "title": null,
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": null,
+                "id": "APP_BUILD_BOOTLOADER",
+                "name": "APP_BUILD_BOOTLOADER",
+                "range": null,
+                "title": null,
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": "APP_BUILD_TYPE_RAM",
+                "help": "If this option is enabled, external memory and related peripherals, such as Cache, MMU,\nFlash and PSRAM, won't be initialized. Corresponding drivers won't be introduced either.\nComponents that depend on the spi_flash component will also be unavailable, such as\napp_update, etc. When this option is enabled, about 26KB of RAM space can be saved.",
+                "id": "APP_BUILD_TYPE_PURE_RAM_APP",
+                "name": "APP_BUILD_TYPE_PURE_RAM_APP",
+                "range": null,
+                "title": "Build app without SPI_FLASH/PSRAM support (saves ram)",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": null,
+                "id": "APP_BUILD_USE_FLASH_SECTIONS",
+                "name": "APP_BUILD_USE_FLASH_SECTIONS",
+                "range": null,
+                "title": null,
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": "If enabled, all date, time, and path information would be eliminated. A .gdbinit file would be create\nautomatically. (or will be append if you have one already)",
+                "id": "APP_REPRODUCIBLE_BUILD",
+                "name": "APP_REPRODUCIBLE_BUILD",
+                "range": null,
+                "title": "Enable reproducible build",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": "If enabled, this disables the linking of binary libraries in the application build. Note\nthat after enabling this Wi-Fi/Bluetooth will not work.",
+                "id": "APP_NO_BLOBS",
+                "name": "APP_NO_BLOBS",
+                "range": null,
+                "title": "No Binary Blobs",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": "IDF_TARGET_ESP32",
+                "help": "Bootloaders before ESP-IDF v2.1 did less initialisation of the\nsystem clock. This setting needs to be enabled to build an app\nwhich can be booted by these older bootloaders.\n\nIf this setting is enabled, the app can be booted by any bootloader\nfrom IDF v1.0 up to the current version.\n\nIf this setting is disabled, the app can only be booted by bootloaders\nfrom IDF v2.1 or newer.\n\nEnabling this setting adds approximately 1KB to the app's IRAM usage.",
+                "id": "APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS",
+                "name": "APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS",
+                "range": null,
+                "title": "App compatible with bootloaders before ESP-IDF v2.1",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": "IDF_TARGET_ESP32",
+                "help": "Partition tables before ESP-IDF V3.1 do not contain an MD5 checksum\nfield, and the bootloader before ESP-IDF v3.1 cannot read a partition\ntable that contains an MD5 checksum field.\n\nEnable this option only if your app needs to boot on a bootloader and/or\npartition table that was generated from a version *before* ESP-IDF v3.1.\n\nIf this option and Flash Encryption are enabled at the same time, and any\ndata partitions in the partition table are marked Encrypted, then the\npartition encrypted flag should be manually verified in the app before accessing\nthe partition (see CVE-2021-27926).",
+                "id": "APP_COMPATIBLE_PRE_V3_1_BOOTLOADERS",
+                "name": "APP_COMPATIBLE_PRE_V3_1_BOOTLOADERS",
+                "range": null,
+                "title": "App compatible with bootloader and partition table before ESP-IDF v3.1",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": "IDF_TARGET_ESP32",
+                "help": null,
+                "id": "APP_INIT_CLK",
+                "name": "APP_INIT_CLK",
+                "range": null,
+                "title": null,
+                "type": "bool"
+            }
+        ],
+        "depends_on": null,
+        "id": "build-type",
+        "title": "Build type",
+        "type": "menu"
+    },
+    {
+        "children": [
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "!APP_REPRODUCIBLE_BUILD",
+                        "help": "If set, then the bootloader will be built with the current time/date stamp.\nIt is stored in the bootloader description\nstructure. If not set, time/date stamp will be excluded from bootloader image.\nThis can be useful for getting the\nsame binary image files made from the same source, but at different times.",
+                        "id": "BOOTLOADER_COMPILE_TIME_DATE",
+                        "name": "BOOTLOADER_COMPILE_TIME_DATE",
+                        "range": null,
+                        "title": "Use time/date stamp for bootloader",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": "Project version. It is placed in \"version\" field of the esp_bootloader_desc structure.\nThe type of this field is \"uint32_t\".",
+                        "id": "BOOTLOADER_PROJECT_VER",
+                        "name": "BOOTLOADER_PROJECT_VER",
+                        "range": [
+                            0,
+                            4294967295
+                        ],
+                        "title": "Project version",
+                        "type": "int"
+                    }
+                ],
+                "depends_on": null,
+                "id": "bootloader-config-bootloader-manager",
+                "title": "Bootloader manager",
+                "type": "menu"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": "Offset address that 2nd bootloader will be flashed to.\nThe value is determined by the ROM bootloader.\nIt's not configurable in ESP-IDF.",
+                "id": "BOOTLOADER_OFFSET_IN_FLASH",
+                "name": "BOOTLOADER_OFFSET_IN_FLASH",
+                "range": null,
+                "title": null,
+                "type": "hex"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "<choice BOOTLOADER_COMPILER_OPTIMIZATION>",
+                        "help": null,
+                        "id": "BOOTLOADER_COMPILER_OPTIMIZATION_SIZE",
+                        "name": "BOOTLOADER_COMPILER_OPTIMIZATION_SIZE",
+                        "range": null,
+                        "title": "Size (-Os with GCC, -Oz with Clang)",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice BOOTLOADER_COMPILER_OPTIMIZATION>",
+                        "help": null,
+                        "id": "BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG",
+                        "name": "BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG",
+                        "range": null,
+                        "title": "Debug (-Og)",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice BOOTLOADER_COMPILER_OPTIMIZATION>",
+                        "help": null,
+                        "id": "BOOTLOADER_COMPILER_OPTIMIZATION_PERF",
+                        "name": "BOOTLOADER_COMPILER_OPTIMIZATION_PERF",
+                        "range": null,
+                        "title": "Optimize for performance (-O2)",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "(IDF_TARGET_ARCH_XTENSA || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C2) && <choice BOOTLOADER_COMPILER_OPTIMIZATION>",
+                        "help": null,
+                        "id": "BOOTLOADER_COMPILER_OPTIMIZATION_NONE",
+                        "name": "BOOTLOADER_COMPILER_OPTIMIZATION_NONE",
+                        "range": null,
+                        "title": "Debug without optimization (-O0) (Deprecated, will be removed in IDF v6.0)",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": null,
+                "help": "This option sets compiler optimization level (gcc -O argument)\nfor the bootloader.\n\n- The default \"Size\" setting will add the -Os (-Oz with clang) flag to CFLAGS.\n- The \"Debug\" setting will add the -Og flag to CFLAGS.\n- The \"Performance\" setting will add the -O2 flag to CFLAGS.\n\nNote that custom optimization levels may be unsupported.",
+                "id": "bootloader-config-bootloader-optimization-level",
+                "name": "BOOTLOADER_COMPILER_OPTIMIZATION",
+                "title": "Bootloader optimization Level",
+                "type": "choice"
+            },
+            {
+                "children": [
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "<choice BOOTLOADER_LOG_LEVEL>",
+                                "help": null,
+                                "id": "BOOTLOADER_LOG_LEVEL_NONE",
+                                "name": "BOOTLOADER_LOG_LEVEL_NONE",
+                                "range": null,
+                                "title": "No output",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice BOOTLOADER_LOG_LEVEL>",
+                                "help": null,
+                                "id": "BOOTLOADER_LOG_LEVEL_ERROR",
+                                "name": "BOOTLOADER_LOG_LEVEL_ERROR",
+                                "range": null,
+                                "title": "Error",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice BOOTLOADER_LOG_LEVEL>",
+                                "help": null,
+                                "id": "BOOTLOADER_LOG_LEVEL_WARN",
+                                "name": "BOOTLOADER_LOG_LEVEL_WARN",
+                                "range": null,
+                                "title": "Warning",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice BOOTLOADER_LOG_LEVEL>",
+                                "help": null,
+                                "id": "BOOTLOADER_LOG_LEVEL_INFO",
+                                "name": "BOOTLOADER_LOG_LEVEL_INFO",
+                                "range": null,
+                                "title": "Info",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice BOOTLOADER_LOG_LEVEL>",
+                                "help": null,
+                                "id": "BOOTLOADER_LOG_LEVEL_DEBUG",
+                                "name": "BOOTLOADER_LOG_LEVEL_DEBUG",
+                                "range": null,
+                                "title": "Debug",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice BOOTLOADER_LOG_LEVEL>",
+                                "help": null,
+                                "id": "BOOTLOADER_LOG_LEVEL_VERBOSE",
+                                "name": "BOOTLOADER_LOG_LEVEL_VERBOSE",
+                                "range": null,
+                                "title": "Verbose",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": null,
+                        "help": "Specify how much output to see in bootloader logs.",
+                        "id": "bootloader-config-log-bootloader-log-verbosity",
+                        "name": "BOOTLOADER_LOG_LEVEL",
+                        "title": "Bootloader log verbosity",
+                        "type": "choice"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": null,
+                        "id": "BOOTLOADER_LOG_LEVEL",
+                        "name": "BOOTLOADER_LOG_LEVEL",
+                        "range": null,
+                        "title": null,
+                        "type": "int"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "Use ANSI terminal colors in log output\nEnable ANSI terminal color codes.\nIn order to view these, your terminal program must support ANSI color codes.",
+                                "id": "BOOTLOADER_LOG_COLORS",
+                                "name": "BOOTLOADER_LOG_COLORS",
+                                "range": null,
+                                "title": "Color",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [
+                                    {
+                                        "children": [],
+                                        "depends_on": "NO_SYMBOL && <choice BOOTLOADER_LOG_TIMESTAMP_SOURCE>",
+                                        "help": null,
+                                        "id": "BOOTLOADER_LOG_TIMESTAMP_SOURCE_NONE",
+                                        "name": "BOOTLOADER_LOG_TIMESTAMP_SOURCE_NONE",
+                                        "range": null,
+                                        "title": "None",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice BOOTLOADER_LOG_TIMESTAMP_SOURCE>",
+                                        "help": null,
+                                        "id": "BOOTLOADER_LOG_TIMESTAMP_SOURCE_CPU_TICKS",
+                                        "name": "BOOTLOADER_LOG_TIMESTAMP_SOURCE_CPU_TICKS",
+                                        "range": null,
+                                        "title": "Milliseconds Since Boot",
+                                        "type": "bool"
+                                    }
+                                ],
+                                "depends_on": null,
+                                "help": "Choose what sort of timestamp is displayed in the log output:\n\n- \"None\" - The log will only contain the actual log messages themselves\n  without any time-related information. Avoiding timestamps can help conserve\n  processing power and memory. It might useful when you\n  perform log analysis or debugging, sometimes it's more straightforward\n  to work with logs that lack timestamps, especially if the time of occurrence\n  is not critical for understanding the issues.\n  \"I log_test: info message\"\n\n- \"Milliseconds since boot\" is calculated from the RTOS tick count multiplied\n  by the tick period. This time will reset after a software reboot.\n  \"I (112500) log_test: info message\"",
+                                "id": "bootloader-config-log-format-timestamp",
+                                "name": "BOOTLOADER_LOG_TIMESTAMP_SOURCE",
+                                "title": "Timestamp",
+                                "type": "choice"
+                            }
+                        ],
+                        "depends_on": null,
+                        "id": "bootloader-config-log-format",
+                        "title": "Format",
+                        "type": "menu"
+                    }
+                ],
+                "depends_on": null,
+                "id": "bootloader-config-log",
+                "title": "Log",
+                "type": "menu"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_QIO || ESPTOOLPY_FLASHMODE_QOUT)",
+                        "help": "This setting is only used if the SPI flash pins have been overridden by setting the eFuses\nSPI_PAD_CONFIG_xxx, and the SPI flash mode is QIO or QOUT.\n\nWhen this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka\nESP32 pin \"SD_DATA_3\" or SPI flash pin \"IO2\") is not specified in eFuse. The same pin is also used\nfor external SPIRAM if it is enabled.\n\nIf this config item is set to N (default), the correct WP pin will be automatically used for any\nEspressif chip or module with integrated flash. If a custom setting is needed, set this config item to\nY and specify the GPIO number connected to the WP.",
+                        "id": "BOOTLOADER_SPI_CUSTOM_WP_PIN",
+                        "name": "BOOTLOADER_SPI_CUSTOM_WP_PIN",
+                        "range": null,
+                        "title": "Use custom SPI Flash WP Pin when flash pins set in eFuse (read help)",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_QIO || ESPTOOLPY_FLASHMODE_QOUT)",
+                        "help": "The option \"Use custom SPI Flash WP Pin\" must be set or this value is ignored\n\nIf burning a customized set of SPI flash pins in eFuse and using QIO or QOUT mode for flash, set this\nvalue to the GPIO number of the SPI flash WP pin.",
+                        "id": "BOOTLOADER_SPI_WP_PIN",
+                        "name": "BOOTLOADER_SPI_WP_PIN",
+                        "range": null,
+                        "title": "Custom SPI Flash WP Pin",
+                        "type": "int"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": "This will force 2nd bootloader to be loaded by DOUT mode, and will restore Dummy Cycle setting by\nresetting the Flash",
+                        "id": "BOOTLOADER_FLASH_DC_AWARE",
+                        "name": "BOOTLOADER_FLASH_DC_AWARE",
+                        "range": null,
+                        "title": "Allow app adjust Dummy Cycle bits in SPI Flash for higher frequency (READ HELP FIRST)",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": "Perform the startup flow recommended by XMC. Please consult XMC for the details of this flow.\nXMC chips will be forbidden to be used, when this option is disabled.\n\nDON'T DISABLE THIS UNLESS YOU KNOW WHAT YOU ARE DOING.\n\ncomment \"Features below require specific hardware (READ DOCS FIRST!)\"",
+                        "id": "BOOTLOADER_FLASH_XMC_SUPPORT",
+                        "name": "BOOTLOADER_FLASH_XMC_SUPPORT",
+                        "range": null,
+                        "title": "Enable the support for flash chips of XMC (READ DOCS FIRST)",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": "This is a helper config for 32bits address flash. Invisible for users.",
+                        "id": "BOOTLOADER_FLASH_32BIT_ADDR",
+                        "name": "BOOTLOADER_FLASH_32BIT_ADDR",
+                        "range": null,
+                        "title": null,
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": "This is a helper config for 32bits address flash. Invisible for users.",
+                        "id": "BOOTLOADER_FLASH_NEEDS_32BIT_FEAT",
+                        "name": "BOOTLOADER_FLASH_NEEDS_32BIT_FEAT",
+                        "range": null,
+                        "title": null,
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": "This is a helper config for 32bits address quad flash. Invisible for users.",
+                        "id": "BOOTLOADER_FLASH_NEEDS_32BIT_ADDR_QUAD_FLASH",
+                        "name": "BOOTLOADER_FLASH_NEEDS_32BIT_ADDR_QUAD_FLASH",
+                        "range": null,
+                        "title": null,
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "BOOTLOADER_FLASH_NEEDS_32BIT_ADDR_QUAD_FLASH && IDF_EXPERIMENTAL_FEATURES",
+                        "help": "Enabling this option allows the CPU to access 32-bit-address flash beyond 16M range.\n1. This option only valid for 4-line flash. Octal flash doesn't need this.\n2. This option is experimental, which means it can\u2019t use on all flash chips stable, for more\ninformation, please contact Espressif Business support.",
+                        "id": "BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH",
+                        "name": "BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH",
+                        "range": null,
+                        "title": "Enable cache access to 32-bit-address (over 16MB) range of SPI Flash (READ DOCS FIRST)",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": null,
+                        "id": "BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH",
+                        "name": "BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH",
+                        "range": null,
+                        "title": null,
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": null,
+                "id": "bootloader-config-serial-flash-configurations",
+                "title": "Serial Flash Configurations",
+                "type": "menu"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "!ESPTOOLPY_FLASHFREQ_80M && <choice BOOTLOADER_VDDSDIO_BOOST>",
+                        "help": null,
+                        "id": "BOOTLOADER_VDDSDIO_BOOST_1_8V",
+                        "name": "BOOTLOADER_VDDSDIO_BOOST_1_8V",
+                        "range": null,
+                        "title": "1.8V",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice BOOTLOADER_VDDSDIO_BOOST>",
+                        "help": null,
+                        "id": "BOOTLOADER_VDDSDIO_BOOST_1_9V",
+                        "name": "BOOTLOADER_VDDSDIO_BOOST_1_9V",
+                        "range": null,
+                        "title": "1.9V",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": "SOC_CONFIGURABLE_VDDSDIO_SUPPORTED",
+                "help": "If this option is enabled, and VDDSDIO LDO is set to 1.8V (using eFuse\nor MTDI bootstrapping pin), bootloader will change LDO settings to\noutput 1.9V instead. This helps prevent flash chip from browning out\nduring flash programming operations.\n\nThis option has no effect if VDDSDIO is set to 3.3V, or if the internal\nVDDSDIO regulator is disabled via eFuse.",
+                "id": "bootloader-config-vddsdio-ldo-voltage",
+                "name": "BOOTLOADER_VDDSDIO_BOOST",
+                "title": "VDDSDIO LDO voltage",
+                "type": "choice"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "BOOTLOADER_FACTORY_RESET",
+                        "help": "The selected GPIO will be configured as an input with internal pull-up enabled. To trigger a factory\nreset, this GPIO must be held high or low (as configured) on startup.\n\nNote that on some SoCs not all pins have an internal pull-up and certain pins are already\nused by ROM bootloader as bootstrapping. Refer to the technical reference manual for further\ndetails on the selected SoC.",
+                        "id": "BOOTLOADER_NUM_PIN_FACTORY_RESET",
+                        "name": "BOOTLOADER_NUM_PIN_FACTORY_RESET",
+                        "range": null,
+                        "title": "Number of the GPIO input for factory reset",
+                        "type": "int"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "<choice BOOTLOADER_FACTORY_RESET_PIN_LEVEL>",
+                                "help": null,
+                                "id": "BOOTLOADER_FACTORY_RESET_PIN_LOW",
+                                "name": "BOOTLOADER_FACTORY_RESET_PIN_LOW",
+                                "range": null,
+                                "title": "Reset on GPIO low",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice BOOTLOADER_FACTORY_RESET_PIN_LEVEL>",
+                                "help": null,
+                                "id": "BOOTLOADER_FACTORY_RESET_PIN_HIGH",
+                                "name": "BOOTLOADER_FACTORY_RESET_PIN_HIGH",
+                                "range": null,
+                                "title": "Reset on GPIO high",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": "BOOTLOADER_FACTORY_RESET",
+                        "help": "Pin level for factory reset, can be triggered on low or high.",
+                        "id": "bootloader-config-gpio-triggers-factory-reset-factory-reset-gpio-level",
+                        "name": "BOOTLOADER_FACTORY_RESET_PIN_LEVEL",
+                        "title": "Factory reset GPIO level",
+                        "type": "choice"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "BOOTLOADER_FACTORY_RESET",
+                        "help": "The device will boot from \"factory\" partition (or OTA slot 0 if no factory partition is present) after a\nfactory reset.",
+                        "id": "BOOTLOADER_OTA_DATA_ERASE",
+                        "name": "BOOTLOADER_OTA_DATA_ERASE",
+                        "range": null,
+                        "title": "Clear OTA data on factory reset (select factory partition)",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "BOOTLOADER_FACTORY_RESET",
+                        "help": "Allows customers to select which data partitions will be erased while factory reset.\n\nSpecify the names of partitions as a comma-delimited with optional spaces for readability. (Like this:\n\"nvs, phy_init, ...\")\nMake sure that the name specified in the partition table and here are the same.\nPartitions of type \"app\" cannot be specified here.",
+                        "id": "BOOTLOADER_DATA_FACTORY_RESET",
+                        "name": "BOOTLOADER_DATA_FACTORY_RESET",
+                        "range": null,
+                        "title": "Comma-separated names of partitions to clear on factory reset",
+                        "type": "string"
+                    }
+                ],
+                "depends_on": null,
+                "help": "Allows to reset the device to factory settings:\n- clear one or more data partitions;\n- boot from \"factory\" partition.\nThe factory reset will occur if there is a GPIO input held at the configured level while\ndevice starts up. See settings below.",
+                "id": "BOOTLOADER_FACTORY_RESET",
+                "name": "BOOTLOADER_FACTORY_RESET",
+                "range": null,
+                "title": "GPIO triggers factory reset",
+                "type": "bool"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "BOOTLOADER_APP_TEST",
+                        "help": "The selected GPIO will be configured as an input with internal pull-up enabled.\nTo trigger a test app, this GPIO must be pulled low on reset.\nAfter the GPIO input is deactivated and the device reboots, the old application will boot.\n(factory or OTA[x]).\n\nNote that on some SoCs not all pins have an internal pull-up and certain pins are already\nused by ROM bootloader as bootstrapping. Refer to the technical reference manual for further\ndetails on the selected SoC.",
+                        "id": "BOOTLOADER_NUM_PIN_APP_TEST",
+                        "name": "BOOTLOADER_NUM_PIN_APP_TEST",
+                        "range": null,
+                        "title": "Number of the GPIO input to boot TEST partition",
+                        "type": "int"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "<choice BOOTLOADER_APP_TEST_PIN_LEVEL>",
+                                "help": null,
+                                "id": "BOOTLOADER_APP_TEST_PIN_LOW",
+                                "name": "BOOTLOADER_APP_TEST_PIN_LOW",
+                                "range": null,
+                                "title": "Enter test app on GPIO low",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice BOOTLOADER_APP_TEST_PIN_LEVEL>",
+                                "help": null,
+                                "id": "BOOTLOADER_APP_TEST_PIN_HIGH",
+                                "name": "BOOTLOADER_APP_TEST_PIN_HIGH",
+                                "range": null,
+                                "title": "Enter test app on GPIO high",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": "BOOTLOADER_APP_TEST",
+                        "help": "Pin level for app test, can be triggered on low or high.",
+                        "id": "bootloader-config-gpio-triggers-boot-from-test-app-partition-app-test-gpio-level",
+                        "name": "BOOTLOADER_APP_TEST_PIN_LEVEL",
+                        "title": "App test GPIO level",
+                        "type": "choice"
+                    }
+                ],
+                "depends_on": "!BOOTLOADER_APP_ANTI_ROLLBACK",
+                "help": "Allows to run the test app from \"TEST\" partition.\nA boot from \"test\" partition will occur if there is a GPIO input pulled low while device starts up.\nSee settings below.",
+                "id": "BOOTLOADER_APP_TEST",
+                "name": "BOOTLOADER_APP_TEST",
+                "range": null,
+                "title": "GPIO triggers boot from test app partition",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": "BOOTLOADER_FACTORY_RESET || BOOTLOADER_APP_TEST",
+                "help": "The GPIO must be held low continuously for this period of time after reset\nbefore a factory reset or test partition boot (as applicable) is performed.",
+                "id": "BOOTLOADER_HOLD_TIME_GPIO",
+                "name": "BOOTLOADER_HOLD_TIME_GPIO",
+                "range": null,
+                "title": "Hold time of GPIO for reset/test mode (seconds)",
+                "type": "int"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": "Protects the unmapped memory regions of the entire address space from unintended accesses.\nThis will ensure that an exception will be triggered whenever the CPU performs a memory\noperation on unmapped regions of the address space.\nNOTE: Disabling this config on some targets (ESP32-C6, ESP32-H2, ESP32-C5) would not generate\nan exception when reading from or writing to 0x0.",
+                "id": "BOOTLOADER_REGION_PROTECTION_ENABLE",
+                "name": "BOOTLOADER_REGION_PROTECTION_ENABLE",
+                "range": null,
+                "title": "Enable protection for unmapped memory regions",
+                "type": "bool"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "BOOTLOADER_WDT_ENABLE",
+                        "help": "If this option is set, the ESP-IDF app must explicitly reset, feed, or disable the rtc_wdt in\nthe app's own code.\nIf this option is not set (default), then rtc_wdt will be disabled by ESP-IDF before calling\nthe app_main() function.\n\nUse function wdt_hal_feed() for resetting counter of RTC_WDT.\nFor esp32/s2 you can also use rtc_wdt_feed().\n\nUse function wdt_hal_disable() for disabling RTC_WDT.\nFor esp32/s2 you can also use rtc_wdt_disable().",
+                        "id": "BOOTLOADER_WDT_DISABLE_IN_USER_CODE",
+                        "name": "BOOTLOADER_WDT_DISABLE_IN_USER_CODE",
+                        "range": null,
+                        "title": "Allows RTC watchdog disable in user code",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "BOOTLOADER_WDT_ENABLE",
+                        "help": "Verify that this parameter is correct and more then the execution time.\nPay attention to options such as reset to factory, trigger test partition and encryption on boot\n- these options can increase the execution time.\nNote: RTC_WDT will reset while encryption operations will be performed.",
+                        "id": "BOOTLOADER_WDT_TIME_MS",
+                        "name": "BOOTLOADER_WDT_TIME_MS",
+                        "range": [
+                            0,
+                            120000
+                        ],
+                        "title": "Timeout for RTC watchdog (ms)",
+                        "type": "int"
+                    }
+                ],
+                "depends_on": null,
+                "help": "Tracks the execution time of startup code.\nIf the execution time is exceeded, the RTC_WDT will restart system.\nIt is also useful to prevent a lock up in start code caused by an unstable power source.\nNOTE: Tracks the execution time starts from the bootloader code - re-set timeout, while selecting the\nsource for slow_clk - and ends calling app_main.\nRe-set timeout is needed due to WDT uses a SLOW_CLK clock source. After changing a frequency slow_clk a\ntime of WDT needs to re-set for new frequency.\nslow_clk depends on RTC_CLK_SRC (INTERNAL_RC or EXTERNAL_CRYSTAL).",
+                "id": "BOOTLOADER_WDT_ENABLE",
+                "name": "BOOTLOADER_WDT_ENABLE",
+                "range": null,
+                "title": "Use RTC watchdog in start code",
+                "type": "bool"
+            },
+            {
+                "children": [
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "BOOTLOADER_APP_ANTI_ROLLBACK",
+                                "help": "The secure version is the sequence number stored in the header of each firmware.\nThe security version is set in the bootloader, version is recorded in the eFuse field\nas the number of set ones. The allocated number of bits in the efuse field\nfor storing the security version is limited (see BOOTLOADER_APP_SEC_VER_SIZE_EFUSE_FIELD option).\n\nBootloader: When bootloader selects an app to boot, an app is selected that has\na security version greater or equal that recorded in eFuse field.\nThe app is booted with a higher (or equal) secure version.\n\nThe security version is worth increasing if in previous versions there is\na significant vulnerability and their use is not acceptable.\n\nYour partition table should has a scheme with ota_0 + ota_1 (without factory).",
+                                "id": "BOOTLOADER_APP_SECURE_VERSION",
+                                "name": "BOOTLOADER_APP_SECURE_VERSION",
+                                "range": null,
+                                "title": "eFuse secure version of app",
+                                "type": "int"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "BOOTLOADER_APP_ANTI_ROLLBACK",
+                                "help": "The size of the efuse secure version field.\nIts length is limited to 32 bits for ESP32 and 16 bits for ESP32-S2.\nThis determines how many times the security version can be increased.",
+                                "id": "BOOTLOADER_APP_SEC_VER_SIZE_EFUSE_FIELD",
+                                "name": "BOOTLOADER_APP_SEC_VER_SIZE_EFUSE_FIELD",
+                                "range": null,
+                                "title": "Size of the efuse secure version field",
+                                "type": "int"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "BOOTLOADER_APP_ANTI_ROLLBACK",
+                                "help": "This option allows to emulate read/write operations with all eFuses and efuse secure version.\nIt allows to test anti-rollback implementation without permanent write eFuse bits.\nThere should be an entry in partition table with following details: `emul_efuse, data, efuse, , 0x2000`.\n\nThis option enables: EFUSE_VIRTUAL and EFUSE_VIRTUAL_KEEP_IN_FLASH.",
+                                "id": "BOOTLOADER_EFUSE_SECURE_VERSION_EMULATE",
+                                "name": "BOOTLOADER_EFUSE_SECURE_VERSION_EMULATE",
+                                "range": null,
+                                "title": "Emulate operations with efuse secure version(only test)",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": "BOOTLOADER_APP_ROLLBACK_ENABLE",
+                        "help": "This option prevents rollback to previous firmware/application image with lower security version.",
+                        "id": "BOOTLOADER_APP_ANTI_ROLLBACK",
+                        "name": "BOOTLOADER_APP_ANTI_ROLLBACK",
+                        "range": null,
+                        "title": "Enable app anti-rollback support",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": null,
+                "help": "After updating the app, the bootloader runs a new app with the \"ESP_OTA_IMG_PENDING_VERIFY\" state set.\nThis state prevents the re-run of this app. After the first boot of the new app in the user code, the\nfunction should be called to confirm the operability of the app or vice versa about its non-operability.\nIf the app is working, then it is marked as valid. Otherwise, it is marked as not valid and rolls back to\nthe previous working app. A reboot is performed, and the app is booted before the software update.\nNote: If during the first boot a new app the power goes out or the WDT works, then roll back will happen.\nRollback is possible only between the apps with the same security versions.",
+                "id": "BOOTLOADER_APP_ROLLBACK_ENABLE",
+                "name": "BOOTLOADER_APP_ROLLBACK_ENABLE",
+                "range": null,
+                "title": "Enable app rollback support",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": "(SECURE_BOOT && SECURE_BOOT_INSECURE) || !SECURE_BOOT",
+                "help": "This option disables the normal validation of an image coming out of\ndeep sleep (checksums, SHA256, and signature). This is a trade-off\nbetween wakeup performance from deep sleep, and image integrity checks.\n\nOnly enable this if you know what you are doing. It should not be used\nin conjunction with using deep_sleep() entry and changing the active OTA\npartition as this would skip the validation upon first load of the new\nOTA partition.\n\nIt is possible to enable this option with Secure Boot if \"allow insecure\noptions\" is enabled, however it's strongly recommended to NOT enable it as\nit may allow a Secure Boot bypass.",
+                "id": "BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP",
+                "name": "BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP",
+                "range": null,
+                "title": "Skip image validation when exiting deep sleep",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": "!SECURE_SIGNED_ON_BOOT",
+                "help": "Some applications need to boot very quickly from power on. By default, the entire app binary\nis read from flash and verified which takes up a significant portion of the boot time.\n\nEnabling this option will skip validation of the app when the SoC boots from power on.\nNote that in this case it's not possible for the bootloader to detect if an app image is\ncorrupted in the flash, therefore it's not possible to safely fall back to a different app\npartition. Flash corruption of this kind is unlikely but can happen if there is a serious\nfirmware bug or physical damage.\n\nFollowing other reset types, the bootloader will still validate the app image. This increases\nthe chances that flash corruption resulting in a crash can be detected following soft reset, and\nthe bootloader will fall back to a valid app image. To increase the chances of successfully recovering\nfrom a flash corruption event, keep the option BOOTLOADER_WDT_ENABLE enabled and consider also enabling\nBOOTLOADER_WDT_DISABLE_IN_USER_CODE - then manually disable the RTC Watchdog once the app is running.\nIn addition, enable both the Task and Interrupt watchdog timers with reset options set.",
+                "id": "BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON",
+                "name": "BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON",
+                "range": null,
+                "title": "Skip image validation from power on reset (READ HELP FIRST)",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": "!SECURE_SIGNED_ON_BOOT",
+                "help": "Selecting this option prevents the bootloader from ever validating the app image before\nbooting it. Any flash corruption of the selected app partition will make the entire SoC\nunbootable.\n\nAlthough flash corruption is a very rare case, it is not recommended to select this option.\nConsider selecting \"Skip image validation from power on reset\" instead. However, if boot time\nis the only important factor then it can be enabled.",
+                "id": "BOOTLOADER_SKIP_VALIDATE_ALWAYS",
+                "name": "BOOTLOADER_SKIP_VALIDATE_ALWAYS",
+                "range": null,
+                "title": "Skip image validation always (READ HELP FIRST)",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": "SOC_RTC_FAST_MEM_SUPPORTED",
+                "help": "Reserve RTC FAST memory for Skip image validation. This option in bytes.\nThis option reserves an area in the RTC FAST memory (access only PRO_CPU).\nUsed to save the addresses of the selected application.\nWhen a wakeup occurs (from Deep sleep), the bootloader retrieves it and\nloads the application without validation.",
+                "id": "BOOTLOADER_RESERVE_RTC_SIZE",
+                "name": "BOOTLOADER_RESERVE_RTC_SIZE",
+                "range": null,
+                "title": null,
+                "type": "hex"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "BOOTLOADER_CUSTOM_RESERVE_RTC",
+                        "help": "This option allows the customer to use the legacy bootloader behavior when the\nRTC FAST memory CRC calculation takes place. When this option is enabled, the\nallocated user custom data will be taken into account in the CRC calculation.\nThis means that any change to the custom data would need a CRC update to prevent\nthe bootloader from marking this data as corrupted.\nIf this option is disabled, the custom data will not be taken into account when\ncalculating the RTC FAST memory CRC. The user custom data can be changed freely,\nwithout the need to update the CRC.\nTHIS OPTION MUST BE THE SAME FOR BOTH THE BOOTLOADER AND THE APPLICATION BUILDS.",
+                        "id": "BOOTLOADER_CUSTOM_RESERVE_RTC_IN_CRC",
+                        "name": "BOOTLOADER_CUSTOM_RESERVE_RTC_IN_CRC",
+                        "range": null,
+                        "title": "Include custom memory in the CRC calculation",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "BOOTLOADER_CUSTOM_RESERVE_RTC",
+                        "help": "This option reserves in RTC FAST memory the area for custom purposes.\nIf you want to create your own bootloader and save more information\nin this area of memory, you can increase it. It must be a multiple of 4 bytes.\nThis area (rtc_retain_mem_t) is reserved and has access from the bootloader and an application.",
+                        "id": "BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE",
+                        "name": "BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE",
+                        "range": null,
+                        "title": "Size in bytes for custom purposes",
+                        "type": "hex"
+                    }
+                ],
+                "depends_on": "SOC_RTC_FAST_MEM_SUPPORTED",
+                "help": "This option allows the customer to place data in the RTC FAST memory,\nthis area remains valid when rebooted, except for power loss.\nThis memory is located at a fixed address and is available\nfor both the bootloader and the application.\n(The application and bootloader must be compiled with the same option).\nThe RTC FAST memory has access only through PRO_CPU.",
+                "id": "BOOTLOADER_CUSTOM_RESERVE_RTC",
+                "name": "BOOTLOADER_CUSTOM_RESERVE_RTC",
+                "range": null,
+                "title": "Reserve RTC FAST memory for custom purposes",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": "SOC_RTC_FAST_MEM_SUPPORTED",
+                "help": "This option reserves an area in RTC FAST memory for the following features:\n- \"Skip image validation when exiting deep sleep\"\n- \"Reserve RTC FAST memory for custom purposes\"\n- \"GPIO triggers factory reset\"",
+                "id": "BOOTLOADER_RESERVE_RTC_MEM",
+                "name": "BOOTLOADER_RESERVE_RTC_MEM",
+                "range": null,
+                "title": null,
+                "type": "bool"
+            }
+        ],
+        "depends_on": null,
+        "id": "bootloader-config",
+        "title": "Bootloader config",
+        "type": "menu"
+    },
+    {
+        "children": [
+            {
+                "children": [],
+                "depends_on": "SECURE_BOOT || SECURE_SIGNED_ON_BOOT_NO_SECURE_BOOT",
+                "help": null,
+                "id": "SECURE_SIGNED_ON_BOOT",
+                "name": "SECURE_SIGNED_ON_BOOT",
+                "range": null,
+                "title": null,
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": "SECURE_BOOT || SECURE_SIGNED_ON_UPDATE_NO_SECURE_BOOT",
+                "help": null,
+                "id": "SECURE_SIGNED_ON_UPDATE",
+                "name": "SECURE_SIGNED_ON_UPDATE",
+                "range": null,
+                "title": null,
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": "SECURE_SIGNED_ON_BOOT || SECURE_SIGNED_ON_UPDATE",
+                "help": null,
+                "id": "SECURE_SIGNED_APPS",
+                "name": "SECURE_SIGNED_APPS",
+                "range": null,
+                "title": null,
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": "(IDF_TARGET_ESP32 && ESP32_REV_MIN_FULL >= 300) || SOC_SECURE_BOOT_V2_RSA",
+                "help": null,
+                "id": "SECURE_BOOT_V2_RSA_SUPPORTED",
+                "name": "SECURE_BOOT_V2_RSA_SUPPORTED",
+                "range": null,
+                "title": null,
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": "SOC_SECURE_BOOT_V2_ECC",
+                "help": null,
+                "id": "SECURE_BOOT_V2_ECC_SUPPORTED",
+                "name": "SECURE_BOOT_V2_ECC_SUPPORTED",
+                "range": null,
+                "title": null,
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": "SOC_SECURE_BOOT_V1",
+                "help": null,
+                "id": "SECURE_BOOT_V1_SUPPORTED",
+                "name": "SECURE_BOOT_V1_SUPPORTED",
+                "range": null,
+                "title": null,
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": "ESP32_REV_MIN_FULL >= 300",
+                "help": null,
+                "id": "SECURE_BOOT_V2_PREFERRED",
+                "name": "SECURE_BOOT_V2_PREFERRED",
+                "range": null,
+                "title": null,
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": null,
+                "id": "SECURE_BOOT_V2_ECDSA_ENABLED",
+                "name": "SECURE_BOOT_V2_ECDSA_ENABLED",
+                "range": null,
+                "title": null,
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": null,
+                "id": "SECURE_BOOT_V2_RSA_ENABLED",
+                "name": "SECURE_BOOT_V2_RSA_ENABLED",
+                "range": null,
+                "title": null,
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": null,
+                "id": "SECURE_BOOT_FLASH_ENC_KEYS_BURN_TOGETHER",
+                "name": "SECURE_BOOT_FLASH_ENC_KEYS_BURN_TOGETHER",
+                "range": null,
+                "title": null,
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": "!SECURE_BOOT",
+                "help": "Require apps to be signed to verify their integrity.\n\nThis option uses the same app signature scheme as hardware secure boot, but unlike hardware secure boot it\ndoes not prevent the bootloader from being physically updated. This means that the device can be secured\nagainst remote network access, but not physical access. Compared to using hardware Secure Boot this option\nis much simpler to implement.",
+                "id": "SECURE_SIGNED_APPS_NO_SECURE_BOOT",
+                "name": "SECURE_SIGNED_APPS_NO_SECURE_BOOT",
+                "range": null,
+                "title": "Require signed app images",
+                "type": "bool"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "SECURE_BOOT_V1_SUPPORTED && (SECURE_SIGNED_APPS_NO_SECURE_BOOT || SECURE_BOOT_V1_ENABLED) && <choice SECURE_SIGNED_APPS_SCHEME>",
+                        "help": "Embeds the ECDSA public key in the bootloader and signs the application with an ECDSA key.\nRefer to the documentation before enabling.",
+                        "id": "SECURE_SIGNED_APPS_ECDSA_SCHEME",
+                        "name": "SECURE_SIGNED_APPS_ECDSA_SCHEME",
+                        "range": null,
+                        "title": "ECDSA",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "SECURE_BOOT_V2_RSA_SUPPORTED && (SECURE_SIGNED_APPS_NO_SECURE_BOOT || SECURE_BOOT_V2_ENABLED) && <choice SECURE_SIGNED_APPS_SCHEME>",
+                        "help": "Appends the RSA-3072 based Signature block to the application.\nRefer to <Secure Boot Version 2 documentation link> before enabling.",
+                        "id": "SECURE_SIGNED_APPS_RSA_SCHEME",
+                        "name": "SECURE_SIGNED_APPS_RSA_SCHEME",
+                        "range": null,
+                        "title": "RSA",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "SECURE_BOOT_V2_ECC_SUPPORTED && (SECURE_SIGNED_APPS_NO_SECURE_BOOT || SECURE_BOOT_V2_ENABLED) && <choice SECURE_SIGNED_APPS_SCHEME>",
+                        "help": "For Secure boot V2 (e.g., ESP32-C2 SoC), appends ECDSA based signature block to the application.\nRefer to documentation before enabling.",
+                        "id": "SECURE_SIGNED_APPS_ECDSA_V2_SCHEME",
+                        "name": "SECURE_SIGNED_APPS_ECDSA_V2_SCHEME",
+                        "range": null,
+                        "title": "ECDSA (V2)",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": "SECURE_BOOT || SECURE_SIGNED_APPS_NO_SECURE_BOOT",
+                "help": "Select the Secure App signing scheme. Depends on the Chip Revision.\nThere are two secure boot versions:\n\n1. Secure boot V1\n    - Legacy custom secure boot scheme. Supported in ESP32 SoC.\n\n2. Secure boot V2\n    - RSA based secure boot scheme.\n      Supported in ESP32-ECO3 (ESP32 Chip Revision 3 onwards), ESP32-S2, ESP32-C3, ESP32-S3 SoCs.\n\n    - ECDSA based secure boot scheme. Supported in ESP32-C2 SoC.",
+                "id": "security-features-app-signing-scheme",
+                "name": "SECURE_SIGNED_APPS_SCHEME",
+                "title": "App Signing Scheme",
+                "type": "choice"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "SECURE_SIGNED_APPS_ECDSA_V2_SCHEME && <choice SECURE_BOOT_ECDSA_KEY_LEN_SIZE>",
+                        "help": null,
+                        "id": "SECURE_BOOT_ECDSA_KEY_LEN_192_BITS",
+                        "name": "SECURE_BOOT_ECDSA_KEY_LEN_192_BITS",
+                        "range": null,
+                        "title": "Using ECC curve NISTP192",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "SECURE_SIGNED_APPS_ECDSA_V2_SCHEME && <choice SECURE_BOOT_ECDSA_KEY_LEN_SIZE>",
+                        "help": null,
+                        "id": "SECURE_BOOT_ECDSA_KEY_LEN_256_BITS",
+                        "name": "SECURE_BOOT_ECDSA_KEY_LEN_256_BITS",
+                        "range": null,
+                        "title": "Using ECC curve NISTP256 (Recommended)",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": "SECURE_SIGNED_APPS_ECDSA_V2_SCHEME",
+                "help": "Select the ECDSA key size. Two key sizes are supported\n\n- 192 bit key using NISTP192 curve\n- 256 bit key using NISTP256 curve (Recommended)\n\nThe advantage of using 256 bit key is the extra randomness which makes it difficult to be\nbruteforced compared to 192 bit key.\nAt present, both key sizes are practically implausible to bruteforce.",
+                "id": "security-features-ecdsa-key-size",
+                "name": "SECURE_BOOT_ECDSA_KEY_LEN_SIZE",
+                "title": "ECDSA key size",
+                "type": "choice"
+            },
+            {
+                "children": [],
+                "depends_on": "SECURE_SIGNED_APPS_NO_SECURE_BOOT && SECURE_SIGNED_APPS_ECDSA_SCHEME",
+                "help": "If this option is set, the bootloader will be compiled with code to verify that an app is signed before\nbooting it.\n\nIf hardware secure boot is enabled, this option is always enabled and cannot be disabled.\nIf hardware secure boot is not enabled, this option doesn't add significant security by itself so most\nusers will want to leave it disabled.",
+                "id": "SECURE_SIGNED_ON_BOOT_NO_SECURE_BOOT",
+                "name": "SECURE_SIGNED_ON_BOOT_NO_SECURE_BOOT",
+                "range": null,
+                "title": "Bootloader verifies app signatures",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": "SECURE_SIGNED_APPS_NO_SECURE_BOOT",
+                "help": "If this option is set, any OTA updated apps will have the signature verified before being considered valid.\n\nWhen enabled, the signature is automatically checked whenever the esp_ota_ops.h APIs are used for OTA\nupdates, or esp_image_format.h APIs are used to verify apps.\n\nIf hardware secure boot is enabled, this option is always enabled and cannot be disabled.\nIf hardware secure boot is not enabled, this option still adds significant security against network-based\nattackers by preventing spoofing of OTA updates.",
+                "id": "SECURE_SIGNED_ON_UPDATE_NO_SECURE_BOOT",
+                "name": "SECURE_SIGNED_ON_UPDATE_NO_SECURE_BOOT",
+                "range": null,
+                "title": "Verify app signature on update",
+                "type": "bool"
+            },
+            {
+                "children": [
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "SECURE_BOOT_V1_SUPPORTED && <choice SECURE_BOOT_VERSION>",
+                                "help": "Build a bootloader which enables secure boot version 1 on first boot.\nRefer to the Secure Boot section of the ESP-IDF Programmer's Guide for this version before enabling.",
+                                "id": "SECURE_BOOT_V1_ENABLED",
+                                "name": "SECURE_BOOT_V1_ENABLED",
+                                "range": null,
+                                "title": "Enable Secure Boot version 1",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "(SECURE_BOOT_V2_RSA_SUPPORTED || SECURE_BOOT_V2_ECC_SUPPORTED) && <choice SECURE_BOOT_VERSION>",
+                                "help": "Build a bootloader which enables Secure Boot version 2 on first boot.\nRefer to Secure Boot V2 section of the ESP-IDF Programmer's Guide for this version before enabling.",
+                                "id": "SECURE_BOOT_V2_ENABLED",
+                                "name": "SECURE_BOOT_V2_ENABLED",
+                                "range": null,
+                                "title": "Enable Secure Boot version 2",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": "SECURE_BOOT",
+                        "help": "Select the Secure Boot Version. Depends on the Chip Revision.\nSecure Boot V2 is the new RSA / ECDSA based secure boot scheme.\n\n    - RSA based scheme is supported in ESP32 (Revision 3 onwards), ESP32-S2, ESP32-C3 (ECO3), ESP32-S3.\n    - ECDSA based scheme is supported in ESP32-C2 SoC.\n\nPlease note that, RSA or ECDSA secure boot is property of specific SoC based on its HW design, supported\ncrypto accelerators, die-size, cost and similar parameters. Please note that RSA scheme has requirement\nfor bigger key sizes but at the same time it is comparatively faster than ECDSA verification.\n\nSecure Boot V1 is the AES based (custom) secure boot scheme supported in ESP32 SoC.",
+                        "id": "security-features-enable-hardware-secure-boot-in-bootloader-read-docs-first--select-secure-boot-version",
+                        "name": "SECURE_BOOT_VERSION",
+                        "title": "Select secure boot version",
+                        "type": "choice"
+                    }
+                ],
+                "depends_on": "SOC_SECURE_BOOT_SUPPORTED && !(IDF_TARGET_ESP32C3 && ESP32C3_REV_MIN_FULL < 3)",
+                "help": "Build a bootloader which enables Secure Boot on first boot.\n\nOnce enabled, Secure Boot will not boot a modified bootloader. The bootloader will only load a partition\ntable or boot an app if the data has a verified digital signature. There are implications for reflashing\nupdated apps once secure boot is enabled.\n\nWhen enabling secure boot, JTAG and ROM BASIC Interpreter are permanently disabled by default.",
+                "id": "SECURE_BOOT",
+                "name": "SECURE_BOOT",
+                "range": null,
+                "title": "Enable hardware Secure Boot in bootloader (READ DOCS FIRST)",
+                "type": "bool"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "<choice SECURE_BOOTLOADER_MODE>",
+                        "help": "On first boot, the bootloader will generate a key which is not readable externally or by software. A\ndigest is generated from the bootloader image itself. This digest will be verified on each subsequent\nboot.\n\nEnabling this option means that the bootloader cannot be changed after the first time it is booted.",
+                        "id": "SECURE_BOOTLOADER_ONE_TIME_FLASH",
+                        "name": "SECURE_BOOTLOADER_ONE_TIME_FLASH",
+                        "range": null,
+                        "title": "One-time flash",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice SECURE_BOOTLOADER_MODE>",
+                        "help": "Generate a reusable secure bootloader key, derived (via SHA-256) from the secure boot signing key.\n\nThis allows the secure bootloader to be re-flashed by anyone with access to the secure boot signing\nkey.\n\nThis option is less secure than one-time flash, because a leak of the digest key from one device\nallows reflashing of any device that uses it.",
+                        "id": "SECURE_BOOTLOADER_REFLASHABLE",
+                        "name": "SECURE_BOOTLOADER_REFLASHABLE",
+                        "range": null,
+                        "title": "Reflashable",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": "SECURE_BOOT_V1_ENABLED",
+                "help": null,
+                "id": "security-features-secure-bootloader-mode",
+                "name": "SECURE_BOOTLOADER_MODE",
+                "title": "Secure bootloader mode",
+                "type": "choice"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "SECURE_BOOT_BUILD_SIGNED_BINARIES",
+                        "help": "Path to the key file used to sign app images.\n\nKey file is an ECDSA private key (NIST256p curve) in PEM format for Secure Boot V1.\nKey file is an RSA private key in PEM format for Secure Boot V2.\n\nPath is evaluated relative to the project directory.\n\nYou can generate a new signing key by running the following command:\nespsecure.py generate_signing_key secure_boot_signing_key.pem\n\nSee the Secure Boot section of the ESP-IDF Programmer's Guide for this version for details.",
+                        "id": "SECURE_BOOT_SIGNING_KEY",
+                        "name": "SECURE_BOOT_SIGNING_KEY",
+                        "range": null,
+                        "title": "Secure boot private signing key",
+                        "type": "string"
+                    }
+                ],
+                "depends_on": "SECURE_SIGNED_APPS",
+                "help": "Once secure boot or signed app requirement is enabled, app images are required to be signed.\n\nIf enabled (default), these binary files are signed as part of the build process. The file named in\n\"Secure boot private signing key\" will be used to sign the image.\n\nIf disabled, unsigned app/partition data will be built. They must be signed manually using espsecure.py.\nVersion 1 to enable ECDSA Based Secure Boot and Version 2 to enable RSA based Secure Boot.\n(for example, on a remote signing server.)",
+                "id": "SECURE_BOOT_BUILD_SIGNED_BINARIES",
+                "name": "SECURE_BOOT_BUILD_SIGNED_BINARIES",
+                "range": null,
+                "title": "Sign binaries during build",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": "SECURE_SIGNED_APPS && SECURE_SIGNED_APPS_ECDSA_SCHEME && !SECURE_BOOT_BUILD_SIGNED_BINARIES",
+                "help": "Path to a public key file used to verify signed images.\nSecure Boot V1: This ECDSA public key is compiled into the bootloader and/or\napp, to verify app images.\n\nKey file is in raw binary format, and can be extracted from a\nPEM formatted private key using the espsecure.py\nextract_public_key command.\n\nRefer to the Secure Boot section of the ESP-IDF Programmer's Guide for this version before enabling.",
+                "id": "SECURE_BOOT_VERIFICATION_KEY",
+                "name": "SECURE_BOOT_VERIFICATION_KEY",
+                "range": null,
+                "title": "Secure boot public signature verification key",
+                "type": "string"
+            },
+            {
+                "children": [],
+                "depends_on": "SECURE_BOOT && SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY",
+                "help": "If this option is set, ROM bootloader will revoke the public key digest burned in efuse block\nif it fails to verify the signature of software bootloader with it.\nRevocation of keys does not happen when enabling secure boot. Once secure boot is enabled,\nkey revocation checks will be done on subsequent boot-up, while verifying the software bootloader\n\nThis feature provides a strong resistance against physical attacks on the device.\n\nNOTE: Once a digest slot is revoked, it can never be used again to verify an image\nThis can lead to permanent bricking of the device, in case all keys are revoked\nbecause of signature verification failure.",
+                "id": "SECURE_BOOT_ENABLE_AGGRESSIVE_KEY_REVOKE",
+                "name": "SECURE_BOOT_ENABLE_AGGRESSIVE_KEY_REVOKE",
+                "range": null,
+                "title": "Enable Aggressive key revoke strategy",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": "SECURE_BOOT_V2_ENABLED",
+                "help": "If not set (default, recommended), on first boot the bootloader will burn the WR_DIS_RD_DIS\nefuse when Secure Boot is enabled. This prevents any more efuses from being read protected.\n\nIf this option is set, it will remain possible to write the EFUSE_RD_DIS efuse field after Secure\nBoot is enabled. This may allow an attacker to read-protect the BLK2 efuse (for ESP32) and\nBLOCK4-BLOCK10 (i.e. BLOCK_KEY0-BLOCK_KEY5)(for other chips) holding the secure boot public key digest,\ncausing an immediate denial of service and possibly allowing an additional fault injection attack to\nbypass the signature protection.\n\nThe option must be set when you need to program any read-protected key type into the efuses,\ne.g., HMAC, ECDSA etc. after secure boot has already been enabled on the device.\nPlease refer to secure boot V2 documentation guide for more details.\n\nNOTE: Once a BLOCK is read-protected, the application will read all zeros from that block\n\nNOTE: If \"UART ROM download mode (Permanently disabled (recommended))\" or\n\"UART ROM download mode (Permanently switch to Secure mode (recommended))\" is set,\nthen it is __NOT__ possible to read/write efuses using espefuse.py utility.\nHowever, efuse can be read/written from the application\n\nPlease refer to the Secure Boot V2 documentation guide for more information.",
+                "id": "SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS",
+                "name": "SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS",
+                "range": null,
+                "title": "Do not disable the ability to further read protect eFuses",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": "SECURE_BOOT_V2_ENABLED && SECURE_BOOT_BUILD_SIGNED_BINARIES",
+                "help": "When Secure Boot V2 is enabled, by default the bootloader is not flashed along with other artifacts\nlike the application and the partition table images, i.e. bootloader has to be separately flashed\nusing the command `idf.py bootloader flash`, whereas, the application and partition table can be flashed\nusing the command `idf.py flash` itself.\nEnabling this option allows flashing the bootloader along with the other artifacts\nby invocation of the command `idf.py flash`.\n\nIf this option is enabled make sure that even the bootloader is signed using the correct secure boot key,\notherwise the bootloader signature verification would fail, as hash of the public key which is present in\nthe bootloader signature would not match with the digest stored into the efuses\nand thus the device will not be able to boot up.",
+                "id": "SECURE_BOOT_FLASH_BOOTLOADER_DEFAULT",
+                "name": "SECURE_BOOT_FLASH_BOOTLOADER_DEFAULT",
+                "range": null,
+                "title": "Flash bootloader along with other artifacts when using the default flash command",
+                "type": "bool"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "<choice SECURE_BOOTLOADER_KEY_ENCODING>",
+                        "help": null,
+                        "id": "SECURE_BOOTLOADER_KEY_ENCODING_256BIT",
+                        "name": "SECURE_BOOTLOADER_KEY_ENCODING_256BIT",
+                        "range": null,
+                        "title": "No encoding (256 bit key)",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice SECURE_BOOTLOADER_KEY_ENCODING>",
+                        "help": null,
+                        "id": "SECURE_BOOTLOADER_KEY_ENCODING_192BIT",
+                        "name": "SECURE_BOOTLOADER_KEY_ENCODING_192BIT",
+                        "range": null,
+                        "title": "3/4 encoding (192 bit key)",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": "SECURE_BOOTLOADER_REFLASHABLE",
+                "help": "In reflashable secure bootloader mode, a hardware key is derived from the signing key (with SHA-256) and\ncan be written to eFuse with espefuse.py.\n\nNormally this is a 256-bit key, but if 3/4 Coding Scheme is used on the device then the eFuse key is\ntruncated to 192 bits.\n\nThis configuration item doesn't change any firmware code, it only changes the size of key binary which is\ngenerated at build time.",
+                "id": "security-features-hardware-key-encoding",
+                "name": "SECURE_BOOTLOADER_KEY_ENCODING",
+                "title": "Hardware Key Encoding",
+                "type": "choice"
+            },
+            {
+                "children": [],
+                "depends_on": "SECURE_BOOT",
+                "help": "You can disable some of the default protections offered by secure boot, in order to enable testing or a\ncustom combination of security features.\n\nOnly enable these options if you are very sure.\n\nRefer to the Secure Boot section of the ESP-IDF Programmer's Guide for this version before enabling.",
+                "id": "SECURE_BOOT_INSECURE",
+                "name": "SECURE_BOOT_INSECURE",
+                "range": null,
+                "title": "Allow potentially insecure options",
+                "type": "bool"
+            },
+            {
+                "children": [
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "SOC_FLASH_ENCRYPTION_XTS_AES_128_DERIVED && <choice SECURE_FLASH_ENCRYPTION_KEYSIZE>",
+                                "help": null,
+                                "id": "SECURE_FLASH_ENCRYPTION_AES128_DERIVED",
+                                "name": "SECURE_FLASH_ENCRYPTION_AES128_DERIVED",
+                                "range": null,
+                                "title": "AES-128 key derived from 128 bits (SHA256(128 bits))",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "SOC_FLASH_ENCRYPTION_XTS_AES_128 && !(IDF_TARGET_ESP32C2 && SECURE_BOOT) && <choice SECURE_FLASH_ENCRYPTION_KEYSIZE>",
+                                "help": null,
+                                "id": "SECURE_FLASH_ENCRYPTION_AES128",
+                                "name": "SECURE_FLASH_ENCRYPTION_AES128",
+                                "range": null,
+                                "title": "AES-128 (256-bit key)",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "SOC_FLASH_ENCRYPTION_XTS_AES_256 && <choice SECURE_FLASH_ENCRYPTION_KEYSIZE>",
+                                "help": null,
+                                "id": "SECURE_FLASH_ENCRYPTION_AES256",
+                                "name": "SECURE_FLASH_ENCRYPTION_AES256",
+                                "range": null,
+                                "title": "AES-256 (512-bit key)",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": "SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS && SECURE_FLASH_ENC_ENABLED",
+                        "help": "Size of generated XTS-AES key.\n\n- AES-128 uses a 256-bit key (32 bytes) derived from 128 bits (16 bytes) burned in half Efuse key block.\n  Internally, it calculates SHA256(128 bits)\n- AES-128 uses a 256-bit key (32 bytes) which occupies one Efuse key block.\n- AES-256 uses a 512-bit key (64 bytes) which occupies two Efuse key blocks.\n\nThis setting is ignored if either type of key is already burned to Efuse before the first boot.\nIn this case, the pre-burned key is used and no new key is generated.",
+                        "id": "security-features-enable-flash-encryption-on-boot-read-docs-first--size-of-generated-xts-aes-key",
+                        "name": "SECURE_FLASH_ENCRYPTION_KEYSIZE",
+                        "title": "Size of generated XTS-AES key",
+                        "type": "choice"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "<choice SECURE_FLASH_ENCRYPTION_MODE>",
+                                "help": null,
+                                "id": "SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT",
+                                "name": "SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT",
+                                "range": null,
+                                "title": "Development (NOT SECURE)",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "(!EFUSE_VIRTUAL || IDF_CI_BUILD) && <choice SECURE_FLASH_ENCRYPTION_MODE>",
+                                "help": null,
+                                "id": "SECURE_FLASH_ENCRYPTION_MODE_RELEASE",
+                                "name": "SECURE_FLASH_ENCRYPTION_MODE_RELEASE",
+                                "range": null,
+                                "title": "Release",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": "SECURE_FLASH_ENC_ENABLED",
+                        "help": "By default Development mode is enabled which allows ROM download mode to perform flash encryption\noperations (plaintext is sent to the device, and it encrypts it internally and writes ciphertext\nto flash.) This mode is not secure, it's possible for an attacker to write their own chosen plaintext\nto flash.\n\nRelease mode should always be selected for production or manufacturing. Once enabled it's no longer\npossible for the device in ROM Download Mode to use the flash encryption hardware.\n\nWhen EFUSE_VIRTUAL is enabled, SECURE_FLASH_ENCRYPTION_MODE_RELEASE is not available.\nFor CI tests we use IDF_CI_BUILD to bypass it (\"export IDF_CI_BUILD=1\").\nWe do not recommend bypassing it for other purposes.\n\nRefer to the Flash Encryption section of the ESP-IDF Programmer's Guide for details.",
+                        "id": "security-features-enable-flash-encryption-on-boot-read-docs-first--enable-usage-mode",
+                        "name": "SECURE_FLASH_ENCRYPTION_MODE",
+                        "title": "Enable usage mode",
+                        "type": "choice"
+                    }
+                ],
+                "depends_on": null,
+                "help": "If this option is set, flash contents will be encrypted by the bootloader on first boot.\n\nNote: After first boot, the system will be permanently encrypted. Re-flashing an encrypted\nsystem is complicated and not always possible.\n\nRead https://docs.espressif.com/projects/esp-idf/en/latest/security/flash-encryption.html\nbefore enabling.",
+                "id": "SECURE_FLASH_ENC_ENABLED",
+                "name": "SECURE_FLASH_ENC_ENABLED",
+                "range": null,
+                "title": "Enable flash encryption on boot (READ DOCS FIRST)",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": null,
+                "id": "SECURE_FLASH_HAS_WRITE_PROTECTION_CACHE",
+                "name": "SECURE_FLASH_HAS_WRITE_PROTECTION_CACHE",
+                "range": null,
+                "title": null,
+                "type": "bool"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "(SECURE_BOOT_INSECURE || SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT) && IDF_TARGET_ESP32",
+                        "help": "By default, the BASIC ROM Console starts on reset if no valid bootloader is\nread from the flash.\n\nWhen either flash encryption or secure boot are enabled, the default is to\ndisable this BASIC fallback mode permanently via eFuse.\n\nIf this option is set, this eFuse is not burned and the BASIC ROM Console may\nremain accessible.  Only set this option in testing environments.",
+                        "id": "SECURE_BOOT_ALLOW_ROM_BASIC",
+                        "name": "SECURE_BOOT_ALLOW_ROM_BASIC",
+                        "range": null,
+                        "title": "Leave ROM BASIC Interpreter available on reset",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "SECURE_BOOT_INSECURE || SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT",
+                        "help": "If not set (default), the bootloader will permanently disable JTAG (across entire chip) on first boot\nwhen either secure boot or flash encryption is enabled.\n\nSetting this option leaves JTAG on for debugging, which negates all protections of flash encryption\nand some of the protections of secure boot.\n\nOnly set this option in testing environments.",
+                        "id": "SECURE_BOOT_ALLOW_JTAG",
+                        "name": "SECURE_BOOT_ALLOW_JTAG",
+                        "range": null,
+                        "title": "Allow JTAG Debugging",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "SECURE_BOOT_INSECURE || SECURE_SIGNED_ON_UPDATE_NO_SECURE_BOOT",
+                        "help": "If not set (default), app partition size must be a multiple of 64KB. App images are padded to 64KB\nlength, and the bootloader checks any trailing bytes after the signature (before the next 64KB\nboundary) have not been written. This is because flash cache maps entire 64KB pages into the address\nspace. This prevents an attacker from appending unverified data after the app image in the flash,\ncausing it to be mapped into the address space.\n\nSetting this option allows the app partition length to be unaligned, and disables padding of the app\nimage to this length. It is generally not recommended to set this option, unless you have a legacy\npartitioning scheme which doesn't support 64KB aligned partition lengths.",
+                        "id": "SECURE_BOOT_ALLOW_SHORT_APP_PARTITION",
+                        "name": "SECURE_BOOT_ALLOW_SHORT_APP_PARTITION",
+                        "range": null,
+                        "title": "Allow app partition length not 64KB aligned",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "SECURE_BOOT_INSECURE && SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS",
+                        "help": "If not set (default), during startup in the app all unused digest slots will be revoked.\nTo revoke unused slot will be called esp_efuse_set_digest_revoke(num_digest) for each digest.\nRevoking unused digest slots makes ensures that no trusted keys can be added later by an attacker.\nIf set, it means that you have a plan to use unused digests slots later.\n\nNote that if you plan to enable secure boot during the first boot up, the bootloader will intentionally\nrevoke the unused digest slots while enabling secure boot, even if the above config is enabled because\nkeeping the unused key slots un-revoked would a security hazard.\nIn case for any development workflow if you need to avoid this revocation, you should enable\nsecure boot externally (host based mechanism) rather than enabling it during the boot up,\nso that the bootloader would not need to enable secure boot and thus you could avoid its revocation\nstrategy.",
+                        "id": "SECURE_BOOT_ALLOW_UNUSED_DIGEST_SLOTS",
+                        "name": "SECURE_BOOT_ALLOW_UNUSED_DIGEST_SLOTS",
+                        "range": null,
+                        "title": "Leave unused digest slots available (not revoke)",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT",
+                        "help": "If not set (default), the bootloader will permanently disable UART bootloader encryption access on\nfirst boot. If set, the UART bootloader will still be able to access hardware encryption.\n\nIt is recommended to only set this option in testing environments.",
+                        "id": "SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC",
+                        "name": "SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC",
+                        "range": null,
+                        "title": "Leave UART bootloader encryption enabled",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT && IDF_TARGET_ESP32",
+                        "help": "If not set (default), the bootloader will permanently disable UART bootloader decryption access on\nfirst boot. If set, the UART bootloader will still be able to access hardware decryption.\n\nOnly set this option in testing environments. Setting this option allows complete bypass of flash\nencryption.",
+                        "id": "SECURE_FLASH_UART_BOOTLOADER_ALLOW_DEC",
+                        "name": "SECURE_FLASH_UART_BOOTLOADER_ALLOW_DEC",
+                        "range": null,
+                        "title": "Leave UART bootloader decryption enabled",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT && (IDF_TARGET_ESP32 || SOC_EFUSE_DIS_DOWNLOAD_ICACHE || SOC_EFUSE_DIS_DOWNLOAD_DCACHE)",
+                        "help": "If not set (default), the bootloader will permanently disable UART bootloader flash cache access on\nfirst boot. If set, the UART bootloader will still be able to access the flash cache.\n\nOnly set this option in testing environments.",
+                        "id": "SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE",
+                        "name": "SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE",
+                        "range": null,
+                        "title": "Leave UART bootloader flash cache enabled",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT",
+                        "help": "If not set (default), and flash encryption is not yet enabled in eFuses, the 2nd stage bootloader\nwill enable flash encryption: generate the flash encryption key and program eFuses.\nIf this option is set, and flash encryption is not yet enabled, the bootloader will error out and\nreboot.\nIf flash encryption is enabled in eFuses, this option does not change the bootloader behavior.\n\nOnly use this option in testing environments, to avoid accidentally enabling flash encryption on\nthe wrong device. The device needs to have flash encryption already enabled using espefuse.py.",
+                        "id": "SECURE_FLASH_REQUIRE_ALREADY_ENABLED",
+                        "name": "SECURE_FLASH_REQUIRE_ALREADY_ENABLED",
+                        "range": null,
+                        "title": "Require flash encryption to be already enabled",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "SECURE_FLASH_HAS_WRITE_PROTECTION_CACHE",
+                        "help": "If not set (default, recommended), on the first boot the bootloader will burn the write-protection of\nDIS_CACHE(for ESP32) or DIS_ICACHE/DIS_DCACHE(for other chips) eFuse when Flash Encryption is enabled.\nWrite protection for cache disable efuse prevents the chip from being blocked if it is set by accident.\nApp and bootloader use cache so disabling it makes the chip useless for IDF.\nDue to other eFuses are linked with the same write protection bit (see the list below) then\nwrite-protection will not be done if these SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC,\nSECURE_BOOT_ALLOW_JTAG or SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE options are selected\nto give a chance to turn on the chip into the release mode later.\n\nList of eFuses with the same write protection bit:\nESP32: MAC, MAC_CRC, DISABLE_APP_CPU, DISABLE_BT, DIS_CACHE, VOL_LEVEL_HP_INV.\n\nESP32-C3: DIS_ICACHE, DIS_USB_JTAG, DIS_DOWNLOAD_ICACHE, DIS_USB_SERIAL_JTAG,\nDIS_FORCE_DOWNLOAD, DIS_TWAI, JTAG_SEL_ENABLE, DIS_PAD_JTAG, DIS_DOWNLOAD_MANUAL_ENCRYPT.\n\nESP32-C6: SWAP_UART_SDIO_EN, DIS_ICACHE, DIS_USB_JTAG, DIS_DOWNLOAD_ICACHE,\nDIS_USB_SERIAL_JTAG, DIS_FORCE_DOWNLOAD, DIS_TWAI, JTAG_SEL_ENABLE,\nDIS_PAD_JTAG, DIS_DOWNLOAD_MANUAL_ENCRYPT.\n\nESP32-H2: DIS_ICACHE, DIS_USB_JTAG, POWERGLITCH_EN, DIS_FORCE_DOWNLOAD, SPI_DOWNLOAD_MSPI_DIS,\nDIS_TWAI, JTAG_SEL_ENABLE, DIS_PAD_JTAG, DIS_DOWNLOAD_MANUAL_ENCRYPT.\n\nESP32-S2: DIS_ICACHE, DIS_DCACHE, DIS_DOWNLOAD_ICACHE, DIS_DOWNLOAD_DCACHE,\nDIS_FORCE_DOWNLOAD, DIS_USB, DIS_TWAI, DIS_BOOT_REMAP, SOFT_DIS_JTAG,\nHARD_DIS_JTAG, DIS_DOWNLOAD_MANUAL_ENCRYPT.\n\nESP32-S3: DIS_ICACHE, DIS_DCACHE, DIS_DOWNLOAD_ICACHE, DIS_DOWNLOAD_DCACHE,\nDIS_FORCE_DOWNLOAD, DIS_USB_OTG, DIS_TWAI, DIS_APP_CPU, DIS_PAD_JTAG,\nDIS_DOWNLOAD_MANUAL_ENCRYPT, DIS_USB_JTAG, DIS_USB_SERIAL_JTAG, STRAP_JTAG_SEL, USB_PHY_SEL.",
+                        "id": "SECURE_FLASH_SKIP_WRITE_PROTECTION_CACHE",
+                        "name": "SECURE_FLASH_SKIP_WRITE_PROTECTION_CACHE",
+                        "range": null,
+                        "title": "Skip write-protection of DIS_CACHE (DIS_ICACHE, DIS_DCACHE)",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": null,
+                "id": "security-features-potentially-insecure-options",
+                "title": "Potentially insecure options",
+                "type": "menu"
+            },
+            {
+                "children": [],
+                "depends_on": "SECURE_FLASH_ENC_ENABLED && !SECURE_FLASH_REQUIRE_ALREADY_ENABLED",
+                "help": "If set (default), optimise encryption time for the partition of type APP,\nby only encrypting the app image that is present in the partition,\ninstead of the whole partition.\nThe image length used for encryption is derived from the image metadata, which\nincludes the size of the app image, checksum, hash and also the signature sector\nwhen secure boot is enabled.\n\nIf not set, the whole partition of type APP would be encrypted,\nwhich increases the encryption time but might be useful if there\nis any custom data appended to the firmware image.",
+                "id": "SECURE_FLASH_ENCRYPT_ONLY_IMAGE_LEN_IN_APP_PART",
+                "name": "SECURE_FLASH_ENCRYPT_ONLY_IMAGE_LEN_IN_APP_PART",
+                "range": null,
+                "title": "Encrypt only the app image that is present in the partition of type app",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": "SECURE_FLASH_ENC_ENABLED",
+                "help": "If set (default), in an app during startup code,\nthere is a check of the flash encryption eFuse bit is on\n(as the bootloader should already have set it).\nThe app requires this bit is on to continue work otherwise abort.\n\nIf not set, the app does not care if the flash encryption eFuse bit is set or not.",
+                "id": "SECURE_FLASH_CHECK_ENC_EN_IN_APP",
+                "name": "SECURE_FLASH_CHECK_ENC_EN_IN_APP",
+                "range": null,
+                "title": "Check Flash Encryption enabled on app startup",
+                "type": "bool"
+            },
+            {
+                "children": [
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "<choice SECURE_FLASH_PSEUDO_ROUND_FUNC_STRENGTH>",
+                                "help": null,
+                                "id": "SECURE_FLASH_PSEUDO_ROUND_FUNC_STRENGTH_LOW",
+                                "name": "SECURE_FLASH_PSEUDO_ROUND_FUNC_STRENGTH_LOW",
+                                "range": null,
+                                "title": "Low",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice SECURE_FLASH_PSEUDO_ROUND_FUNC_STRENGTH>",
+                                "help": null,
+                                "id": "SECURE_FLASH_PSEUDO_ROUND_FUNC_STRENGTH_MEDIUM",
+                                "name": "SECURE_FLASH_PSEUDO_ROUND_FUNC_STRENGTH_MEDIUM",
+                                "range": null,
+                                "title": "Medium",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice SECURE_FLASH_PSEUDO_ROUND_FUNC_STRENGTH>",
+                                "help": null,
+                                "id": "SECURE_FLASH_PSEUDO_ROUND_FUNC_STRENGTH_HIGH",
+                                "name": "SECURE_FLASH_PSEUDO_ROUND_FUNC_STRENGTH_HIGH",
+                                "range": null,
+                                "title": "High",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": "SECURE_FLASH_PSEUDO_ROUND_FUNC",
+                        "help": "The strength of the pseudo rounds functions can be configured to low, medium and high,\neach denoting the values that would be stored in the efuses field.\nBy default the value to set to low.\nYou can configure the strength of the pseudo rounds functions according to your use cases,\nfor example, increasing the strength would provide higher security but would slow down the\nflash encryption/decryption operations.\nFor more info regarding the performance impact, please checkout the pseudo round function section of the\nsecurity guide documentation.",
+                        "id": "security-features-permanently-enable-xts-aes-s-pseudo-rounds-function-strength-of-the-pseudo-rounds-function",
+                        "name": "SECURE_FLASH_PSEUDO_ROUND_FUNC_STRENGTH",
+                        "title": "Strength of the pseudo rounds function",
+                        "type": "choice"
+                    }
+                ],
+                "depends_on": "SECURE_FLASH_ENCRYPTION_MODE_RELEASE && SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND",
+                "help": "If set (default), the bootloader will permanently enable the XTS-AES peripheral's pseudo rounds function.\nNote: Enabling this config would burn an efuse.",
+                "id": "SECURE_FLASH_PSEUDO_ROUND_FUNC",
+                "name": "SECURE_FLASH_PSEUDO_ROUND_FUNC",
+                "range": null,
+                "title": "Permanently enable XTS-AES's pseudo rounds function",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": null,
+                "id": "SECURE_FLASH_PSEUDO_ROUND_FUNC_STRENGTH",
+                "name": "SECURE_FLASH_PSEUDO_ROUND_FUNC_STRENGTH",
+                "range": null,
+                "title": null,
+                "type": "int"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": null,
+                "id": "SECURE_ROM_DL_MODE_ENABLED",
+                "name": "SECURE_ROM_DL_MODE_ENABLED",
+                "range": null,
+                "title": null,
+                "type": "bool"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "<choice SECURE_UART_ROM_DL_MODE>",
+                        "help": "If set, during startup the app will burn an eFuse bit to permanently disable the UART ROM\nDownload Mode. This prevents any future use of esptool.py, espefuse.py and similar tools.\n\nOnce disabled, if the SoC is booted with strapping pins set for ROM Download Mode\nthen an error is printed instead.\n\nIt is recommended to enable this option in any production application where Flash\nEncryption and/or Secure Boot is enabled and access to Download Mode is not required.\n\nIt is also possible to permanently disable Download Mode by calling\nesp_efuse_disable_rom_download_mode() at runtime.",
+                        "id": "SECURE_DISABLE_ROM_DL_MODE",
+                        "name": "SECURE_DISABLE_ROM_DL_MODE",
+                        "range": null,
+                        "title": "UART ROM download mode (Permanently disabled (recommended))",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "SOC_SUPPORTS_SECURE_DL_MODE && <choice SECURE_UART_ROM_DL_MODE>",
+                        "help": "If set, during startup the app will burn an eFuse bit to permanently switch the UART ROM\nDownload Mode into a separate Secure Download mode. This option can only work if\nDownload Mode is not already disabled by eFuse.\n\nSecure Download mode limits the use of Download Mode functions to update SPI config,\nchanging baud rate, basic flash write and a command to return a summary of currently\nenabled security features (`get_security_info`).\n\nSecure Download mode is not compatible with the esptool.py flasher stub feature,\nespefuse.py, read/writing memory or registers, encrypted download, or any other\nfeatures that interact with unsupported Download Mode commands.\n\nSecure Download mode should be enabled in any application where Flash Encryption\nand/or Secure Boot is enabled. Disabling this option does not immediately cancel\nthe benefits of the security features, but it increases the potential \"attack\nsurface\" for an attacker to try and bypass them with a successful physical attack.\n\nIt is also possible to enable secure download mode at runtime by calling\nesp_efuse_enable_rom_secure_download_mode()\n\nNote: Secure Download mode is not available for ESP32 (includes revisions till ECO3).",
+                        "id": "SECURE_ENABLE_SECURE_ROM_DL_MODE",
+                        "name": "SECURE_ENABLE_SECURE_ROM_DL_MODE",
+                        "range": null,
+                        "title": "UART ROM download mode (Permanently switch to Secure mode (recommended))",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice SECURE_UART_ROM_DL_MODE>",
+                        "help": "This is a potentially insecure option.\nEnabling this option will allow the full UART download mode to stay enabled.\nThis option SHOULD NOT BE ENABLED for production use cases.",
+                        "id": "SECURE_INSECURE_ALLOW_DL_MODE",
+                        "name": "SECURE_INSECURE_ALLOW_DL_MODE",
+                        "range": null,
+                        "title": "UART ROM download mode (Enabled (not recommended))",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": "(SECURE_BOOT_V2_ENABLED || SECURE_FLASH_ENC_ENABLED) && !(IDF_TARGET_ESP32 && ESP32_REV_MIN_FULL < 300)",
+                "help": null,
+                "id": "security-features-uart-rom-download-mode",
+                "name": "SECURE_UART_ROM_DL_MODE",
+                "title": "UART ROM download mode",
+                "type": "choice"
+            }
+        ],
+        "depends_on": null,
+        "id": "security-features",
+        "title": "Security features",
+        "type": "menu"
+    },
+    {
+        "children": [
+            {
+                "children": [],
+                "depends_on": "!APP_REPRODUCIBLE_BUILD",
+                "help": "If set, then the app will be built with the current time/date stamp. It is stored in the app description\nstructure. If not set, time/date stamp will be excluded from app image. This can be useful for getting the\nsame binary image files made from the same source, but at different times.",
+                "id": "APP_COMPILE_TIME_DATE",
+                "name": "APP_COMPILE_TIME_DATE",
+                "range": null,
+                "title": "Use time/date stamp for app",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": "The PROJECT_VER variable from the build system will not affect the firmware image.\nThis value will not be contained in the esp_app_desc structure.",
+                "id": "APP_EXCLUDE_PROJECT_VER_VAR",
+                "name": "APP_EXCLUDE_PROJECT_VER_VAR",
+                "range": null,
+                "title": "Exclude PROJECT_VER from firmware image",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": "The PROJECT_NAME variable from the build system will not affect the firmware image.\nThis value will not be contained in the esp_app_desc structure.",
+                "id": "APP_EXCLUDE_PROJECT_NAME_VAR",
+                "name": "APP_EXCLUDE_PROJECT_NAME_VAR",
+                "range": null,
+                "title": "Exclude PROJECT_NAME from firmware image",
+                "type": "bool"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "APP_PROJECT_VER_FROM_CONFIG",
+                        "help": "Project version",
+                        "id": "APP_PROJECT_VER",
+                        "name": "APP_PROJECT_VER",
+                        "range": null,
+                        "title": "Project version",
+                        "type": "string"
+                    }
+                ],
+                "depends_on": null,
+                "help": "If this is enabled, then config item APP_PROJECT_VER will be used for the variable PROJECT_VER.\nOther ways to set PROJECT_VER will be ignored.",
+                "id": "APP_PROJECT_VER_FROM_CONFIG",
+                "name": "APP_PROJECT_VER_FROM_CONFIG",
+                "range": null,
+                "title": "Get the project version from Kconfig",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": "At startup, the app will read the embedded APP ELF SHA-256 hash value from flash\nand convert it into a string and store it in a RAM buffer.\nThis ensures the panic handler and core dump will be able to print this string\neven when cache is disabled.\nThe size of the buffer is APP_RETRIEVE_LEN_ELF_SHA plus the null terminator.\nChanging this value will change the size of this buffer, in bytes.",
+                "id": "APP_RETRIEVE_LEN_ELF_SHA",
+                "name": "APP_RETRIEVE_LEN_ELF_SHA",
+                "range": [
+                    8,
+                    64
+                ],
+                "title": "The length of APP ELF SHA is stored in RAM(chars)",
+                "type": "int"
+            }
+        ],
+        "depends_on": null,
+        "id": "application-manager",
+        "title": "Application manager",
+        "type": "menu"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "ESP_ROM_HAS_CRC_LE",
+        "name": "ESP_ROM_HAS_CRC_LE",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "ESP_ROM_HAS_CRC_BE",
+        "name": "ESP_ROM_HAS_CRC_BE",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "ESP_ROM_HAS_MZ_CRC32",
+        "name": "ESP_ROM_HAS_MZ_CRC32",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "ESP_ROM_HAS_JPEG_DECODE",
+        "name": "ESP_ROM_HAS_JPEG_DECODE",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "ESP_ROM_UART_CLK_IS_XTAL",
+        "name": "ESP_ROM_UART_CLK_IS_XTAL",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "ESP_ROM_USB_SERIAL_DEVICE_NUM",
+        "name": "ESP_ROM_USB_SERIAL_DEVICE_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "ESP_ROM_HAS_RETARGETABLE_LOCKING",
+        "name": "ESP_ROM_HAS_RETARGETABLE_LOCKING",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "ESP_ROM_HAS_ERASE_0_REGION_BUG",
+        "name": "ESP_ROM_HAS_ERASE_0_REGION_BUG",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "ESP_ROM_HAS_ENCRYPTED_WRITES_USING_LEGACY_DRV",
+        "name": "ESP_ROM_HAS_ENCRYPTED_WRITES_USING_LEGACY_DRV",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "ESP_ROM_GET_CLK_FREQ",
+        "name": "ESP_ROM_GET_CLK_FREQ",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "ESP_ROM_NEEDS_SWSETUP_WORKAROUND",
+        "name": "ESP_ROM_NEEDS_SWSETUP_WORKAROUND",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "ESP_ROM_HAS_LAYOUT_TABLE",
+        "name": "ESP_ROM_HAS_LAYOUT_TABLE",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "ESP_ROM_HAS_SPI_FLASH",
+        "name": "ESP_ROM_HAS_SPI_FLASH",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "ESP_ROM_HAS_ETS_PRINTF_BUG",
+        "name": "ESP_ROM_HAS_ETS_PRINTF_BUG",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "ESP_ROM_HAS_NEWLIB",
+        "name": "ESP_ROM_HAS_NEWLIB",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "ESP_ROM_HAS_NEWLIB_NANO_FORMAT",
+        "name": "ESP_ROM_HAS_NEWLIB_NANO_FORMAT",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "ESP_ROM_HAS_NEWLIB_32BIT_TIME",
+        "name": "ESP_ROM_HAS_NEWLIB_32BIT_TIME",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE",
+        "name": "ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "ESP_ROM_RAM_APP_NEEDS_MMU_INIT",
+        "name": "ESP_ROM_RAM_APP_NEEDS_MMU_INIT",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "ESP_ROM_HAS_SW_FLOAT",
+        "name": "ESP_ROM_HAS_SW_FLOAT",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "ESP_ROM_USB_OTG_NUM",
+        "name": "ESP_ROM_USB_OTG_NUM",
+        "range": null,
+        "title": null,
+        "type": "int"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "ESP_ROM_HAS_VERSION",
+        "name": "ESP_ROM_HAS_VERSION",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": null,
+        "id": "ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB",
+        "name": "ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB",
+        "range": null,
+        "title": null,
+        "type": "bool"
+    },
+    {
+        "children": [
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "<choice BOOT_ROM_LOG_SCHEME>",
+                        "help": "Always print ROM logs, this is the default behavior.",
+                        "id": "BOOT_ROM_LOG_ALWAYS_ON",
+                        "name": "BOOT_ROM_LOG_ALWAYS_ON",
+                        "range": null,
+                        "title": "Always Log",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice BOOT_ROM_LOG_SCHEME>",
+                        "help": "Don't print ROM logs.",
+                        "id": "BOOT_ROM_LOG_ALWAYS_OFF",
+                        "name": "BOOT_ROM_LOG_ALWAYS_OFF",
+                        "range": null,
+                        "title": "Permanently disable logging",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice BOOT_ROM_LOG_SCHEME>",
+                        "help": "Print ROM logs when GPIO level is high during start up.\nThe GPIO number is chip dependent,\ne.g. on ESP32-S2, the control GPIO is GPIO46.",
+                        "id": "BOOT_ROM_LOG_ON_GPIO_HIGH",
+                        "name": "BOOT_ROM_LOG_ON_GPIO_HIGH",
+                        "range": null,
+                        "title": "Log on GPIO High",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice BOOT_ROM_LOG_SCHEME>",
+                        "help": "Print ROM logs when GPIO level is low during start up.\nThe GPIO number is chip dependent,\ne.g. on ESP32-S2, the control GPIO is GPIO46.",
+                        "id": "BOOT_ROM_LOG_ON_GPIO_LOW",
+                        "name": "BOOT_ROM_LOG_ON_GPIO_LOW",
+                        "range": null,
+                        "title": "Log on GPIO Low",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": "!IDF_TARGET_ESP32",
+                "help": "Controls the Boot ROM log behavior.\nThe rom log behavior can only be changed for once,\nspecific eFuse bit(s) will be burned at app boot stage.",
+                "id": "boot-rom-behavior-permanently-change-boot-rom-output",
+                "name": "BOOT_ROM_LOG_SCHEME",
+                "title": "Permanently change Boot ROM output",
+                "type": "choice"
+            }
+        ],
+        "depends_on": null,
+        "id": "boot-rom-behavior",
+        "title": "Boot ROM Behavior",
+        "type": "menu"
+    },
+    {
+        "children": [
+            {
+                "children": [],
+                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                "help": "The flasher tool sends a precompiled download stub first by default. That stub allows things\nlike compressed downloads and more. Usually you should not need to disable that feature",
+                "id": "ESPTOOLPY_NO_STUB",
+                "name": "ESPTOOLPY_NO_STUB",
+                "range": null,
+                "title": "Disable download stub",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": "IDF_TARGET_ESP32S3 && !APP_BUILD_TYPE_PURE_RAM_APP",
+                "help": null,
+                "id": "ESPTOOLPY_OCT_FLASH",
+                "name": "ESPTOOLPY_OCT_FLASH",
+                "range": null,
+                "title": "Enable Octal Flash",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": "IDF_TARGET_ESP32S3 && !APP_BUILD_TYPE_PURE_RAM_APP",
+                "help": "This config option helps decide whether flash is Quad or Octal, but please note some limitations:\n\n1. If the flash chip is an Octal one, even if one of \"QIO\", \"QOUT\", \"DIO\", \"DOUT\" options is\n   selected in `ESPTOOLPY_FLASHMODE`, our code will automatically change the\n   mode to \"OPI\" and the sample mode will be STR.\n2. If the flash chip is a Quad one, even if \"OPI\" is selected in `ESPTOOLPY_FLASHMODE`, our code will\n   automatically change the mode to \"DIO\".\n3. This option is mainly to improve the out-of-box experience of developers. It doesn't guarantee\n   the feature-complete. Some code still rely on `ESPTOOLPY_OCT_FLASH`. Please do not rely on this option\n   when you are pretty sure that you are using Octal flash.\n   In this case, please enable `ESPTOOLPY_OCT_FLASH` option, then you can choose `DTR` sample mode\n   in `ESPTOOLPY_FLASH_SAMPLE_MODE`. Otherwise, only `STR` mode is available.\n4. Enabling this feature reduces available internal RAM size (around 900 bytes).\n   If your IRAM space is insufficient and you're aware of your flash type,\n   disable this option and select corresponding flash type options.",
+                "id": "ESPTOOLPY_FLASH_MODE_AUTO_DETECT",
+                "name": "ESPTOOLPY_FLASH_MODE_AUTO_DETECT",
+                "range": null,
+                "title": "Choose flash mode automatically (please read help)",
+                "type": "bool"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "!ESPTOOLPY_OCT_FLASH && <choice ESPTOOLPY_FLASHMODE>",
+                        "help": null,
+                        "id": "ESPTOOLPY_FLASHMODE_QIO",
+                        "name": "ESPTOOLPY_FLASHMODE_QIO",
+                        "range": null,
+                        "title": "QIO",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "!ESPTOOLPY_OCT_FLASH && <choice ESPTOOLPY_FLASHMODE>",
+                        "help": null,
+                        "id": "ESPTOOLPY_FLASHMODE_QOUT",
+                        "name": "ESPTOOLPY_FLASHMODE_QOUT",
+                        "range": null,
+                        "title": "QOUT",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "!ESPTOOLPY_OCT_FLASH && <choice ESPTOOLPY_FLASHMODE>",
+                        "help": null,
+                        "id": "ESPTOOLPY_FLASHMODE_DIO",
+                        "name": "ESPTOOLPY_FLASHMODE_DIO",
+                        "range": null,
+                        "title": "DIO",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "!ESPTOOLPY_OCT_FLASH && <choice ESPTOOLPY_FLASHMODE>",
+                        "help": null,
+                        "id": "ESPTOOLPY_FLASHMODE_DOUT",
+                        "name": "ESPTOOLPY_FLASHMODE_DOUT",
+                        "range": null,
+                        "title": "DOUT",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "ESPTOOLPY_OCT_FLASH && <choice ESPTOOLPY_FLASHMODE>",
+                        "help": null,
+                        "id": "ESPTOOLPY_FLASHMODE_OPI",
+                        "name": "ESPTOOLPY_FLASHMODE_OPI",
+                        "range": null,
+                        "title": "OPI",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                "help": "Mode the flash chip is flashed in, as well as the default mode for the\nbinary to run in.",
+                "id": "serial-flasher-config-flash-spi-mode",
+                "name": "ESPTOOLPY_FLASHMODE",
+                "title": "Flash SPI mode",
+                "type": "choice"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "<choice ESPTOOLPY_FLASH_SAMPLE_MODE>",
+                        "help": null,
+                        "id": "ESPTOOLPY_FLASH_SAMPLE_MODE_STR",
+                        "name": "ESPTOOLPY_FLASH_SAMPLE_MODE_STR",
+                        "range": null,
+                        "title": "STR Mode",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "ESPTOOLPY_OCT_FLASH && <choice ESPTOOLPY_FLASH_SAMPLE_MODE>",
+                        "help": null,
+                        "id": "ESPTOOLPY_FLASH_SAMPLE_MODE_DTR",
+                        "name": "ESPTOOLPY_FLASH_SAMPLE_MODE_DTR",
+                        "range": null,
+                        "title": "DTR Mode",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                "help": null,
+                "id": "serial-flasher-config-flash-sampling-mode",
+                "name": "ESPTOOLPY_FLASH_SAMPLE_MODE",
+                "title": "Flash Sampling Mode",
+                "type": "choice"
+            },
+            {
+                "children": [],
+                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                "help": null,
+                "id": "ESPTOOLPY_FLASHMODE",
+                "name": "ESPTOOLPY_FLASHMODE",
+                "range": null,
+                "title": null,
+                "type": "string"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "<choice ESPTOOLPY_FLASHFREQ>",
+                        "help": null,
+                        "id": "ESPTOOLPY_FLASHFREQ_80M",
+                        "name": "ESPTOOLPY_FLASHFREQ_80M",
+                        "range": null,
+                        "title": "80 MHz",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice ESPTOOLPY_FLASHFREQ>",
+                        "help": null,
+                        "id": "ESPTOOLPY_FLASHFREQ_40M",
+                        "name": "ESPTOOLPY_FLASHFREQ_40M",
+                        "range": null,
+                        "title": "40 MHz",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice ESPTOOLPY_FLASHFREQ>",
+                        "help": null,
+                        "id": "ESPTOOLPY_FLASHFREQ_26M",
+                        "name": "ESPTOOLPY_FLASHFREQ_26M",
+                        "range": null,
+                        "title": "26 MHz",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice ESPTOOLPY_FLASHFREQ>",
+                        "help": null,
+                        "id": "ESPTOOLPY_FLASHFREQ_20M",
+                        "name": "ESPTOOLPY_FLASHFREQ_20M",
+                        "range": null,
+                        "title": "20 MHz",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                "help": null,
+                "id": "serial-flasher-config-flash-spi-speed",
+                "name": "ESPTOOLPY_FLASHFREQ",
+                "title": "Flash SPI speed",
+                "type": "choice"
+            },
+            {
+                "children": [],
+                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                "help": null,
+                "id": "ESPTOOLPY_FLASHFREQ",
+                "name": "ESPTOOLPY_FLASHFREQ",
+                "range": null,
+                "title": null,
+                "type": "string"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "<choice ESPTOOLPY_FLASHSIZE>",
+                        "help": null,
+                        "id": "ESPTOOLPY_FLASHSIZE_1MB",
+                        "name": "ESPTOOLPY_FLASHSIZE_1MB",
+                        "range": null,
+                        "title": "1 MB",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice ESPTOOLPY_FLASHSIZE>",
+                        "help": null,
+                        "id": "ESPTOOLPY_FLASHSIZE_2MB",
+                        "name": "ESPTOOLPY_FLASHSIZE_2MB",
+                        "range": null,
+                        "title": "2 MB",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice ESPTOOLPY_FLASHSIZE>",
+                        "help": null,
+                        "id": "ESPTOOLPY_FLASHSIZE_4MB",
+                        "name": "ESPTOOLPY_FLASHSIZE_4MB",
+                        "range": null,
+                        "title": "4 MB",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice ESPTOOLPY_FLASHSIZE>",
+                        "help": null,
+                        "id": "ESPTOOLPY_FLASHSIZE_8MB",
+                        "name": "ESPTOOLPY_FLASHSIZE_8MB",
+                        "range": null,
+                        "title": "8 MB",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice ESPTOOLPY_FLASHSIZE>",
+                        "help": null,
+                        "id": "ESPTOOLPY_FLASHSIZE_16MB",
+                        "name": "ESPTOOLPY_FLASHSIZE_16MB",
+                        "range": null,
+                        "title": "16 MB",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice ESPTOOLPY_FLASHSIZE>",
+                        "help": null,
+                        "id": "ESPTOOLPY_FLASHSIZE_32MB",
+                        "name": "ESPTOOLPY_FLASHSIZE_32MB",
+                        "range": null,
+                        "title": "32 MB",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice ESPTOOLPY_FLASHSIZE>",
+                        "help": null,
+                        "id": "ESPTOOLPY_FLASHSIZE_64MB",
+                        "name": "ESPTOOLPY_FLASHSIZE_64MB",
+                        "range": null,
+                        "title": "64 MB",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice ESPTOOLPY_FLASHSIZE>",
+                        "help": null,
+                        "id": "ESPTOOLPY_FLASHSIZE_128MB",
+                        "name": "ESPTOOLPY_FLASHSIZE_128MB",
+                        "range": null,
+                        "title": "128 MB",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                "help": "SPI flash size, in megabytes",
+                "id": "serial-flasher-config-flash-size",
+                "name": "ESPTOOLPY_FLASHSIZE",
+                "title": "Flash size",
+                "type": "choice"
+            },
+            {
+                "children": [],
+                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                "help": null,
+                "id": "ESPTOOLPY_FLASHSIZE",
+                "name": "ESPTOOLPY_FLASHSIZE",
+                "range": null,
+                "title": null,
+                "type": "string"
+            },
+            {
+                "children": [],
+                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                "help": "If this option is set, flashing the project will automatically detect\nthe flash size of the target chip and update the bootloader image\nbefore it is flashed.\n\nEnabling this option turns off the image protection against corruption\nby a SHA256 digest. Updating the bootloader image before flashing would\ninvalidate the digest.",
+                "id": "ESPTOOLPY_HEADER_FLASHSIZE_UPDATE",
+                "name": "ESPTOOLPY_HEADER_FLASHSIZE_UPDATE",
+                "range": null,
+                "title": "Detect flash size when flashing bootloader",
+                "type": "bool"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "<choice ESPTOOLPY_BEFORE>",
+                        "help": null,
+                        "id": "ESPTOOLPY_BEFORE_RESET",
+                        "name": "ESPTOOLPY_BEFORE_RESET",
+                        "range": null,
+                        "title": "Reset to bootloader",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice ESPTOOLPY_BEFORE>",
+                        "help": null,
+                        "id": "ESPTOOLPY_BEFORE_NORESET",
+                        "name": "ESPTOOLPY_BEFORE_NORESET",
+                        "range": null,
+                        "title": "No reset",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                "help": "Configure whether esptool.py should reset the ESP32 before flashing.\n\nAutomatic resetting depends on the RTS & DTR signals being\nwired from the serial port to the ESP32. Most USB development\nboards do this internally.",
+                "id": "serial-flasher-config-before-flashing",
+                "name": "ESPTOOLPY_BEFORE",
+                "title": "Before flashing",
+                "type": "choice"
+            },
+            {
+                "children": [],
+                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                "help": null,
+                "id": "ESPTOOLPY_BEFORE",
+                "name": "ESPTOOLPY_BEFORE",
+                "range": null,
+                "title": null,
+                "type": "string"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "<choice ESPTOOLPY_AFTER>",
+                        "help": null,
+                        "id": "ESPTOOLPY_AFTER_RESET",
+                        "name": "ESPTOOLPY_AFTER_RESET",
+                        "range": null,
+                        "title": "Reset after flashing",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice ESPTOOLPY_AFTER>",
+                        "help": null,
+                        "id": "ESPTOOLPY_AFTER_NORESET",
+                        "name": "ESPTOOLPY_AFTER_NORESET",
+                        "range": null,
+                        "title": "Stay in bootloader",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                "help": "Configure whether esptool.py should reset the ESP32 after flashing.\n\nAutomatic resetting depends on the RTS & DTR signals being\nwired from the serial port to the ESP32. Most USB development\nboards do this internally.",
+                "id": "serial-flasher-config-after-flashing",
+                "name": "ESPTOOLPY_AFTER",
+                "title": "After flashing",
+                "type": "choice"
+            },
+            {
+                "children": [],
+                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                "help": null,
+                "id": "ESPTOOLPY_AFTER",
+                "name": "ESPTOOLPY_AFTER",
+                "range": null,
+                "title": null,
+                "type": "string"
+            },
+            {
+                "children": [],
+                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                "help": null,
+                "id": "ESPTOOLPY_MONITOR_BAUD",
+                "name": "ESPTOOLPY_MONITOR_BAUD",
+                "range": null,
+                "title": null,
+                "type": "int"
+            }
+        ],
+        "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+        "id": "serial-flasher-config",
+        "title": "Serial flasher config",
+        "type": "menu"
+    },
+    {
+        "children": [
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "<choice PARTITION_TABLE_TYPE>",
+                        "help": "This is the default partition table, designed to fit into a 2MB or\nlarger flash with a single 1MB app partition.\n\nThe corresponding CSV file in the IDF directory is\ncomponents/partition_table/partitions_singleapp.csv\n\nThis partition table is not suitable for an app that needs OTA\n(over the air update) capability.",
+                        "id": "PARTITION_TABLE_SINGLE_APP",
+                        "name": "PARTITION_TABLE_SINGLE_APP",
+                        "range": null,
+                        "title": "Single factory app, no OTA",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice PARTITION_TABLE_TYPE>",
+                        "help": "This is a variation of the default partition table, that expands\nthe 1MB app partition size to 1.5MB to fit more code.\n\nThe corresponding CSV file in the IDF directory is\ncomponents/partition_table/partitions_singleapp_large.csv\n\nThis partition table is not suitable for an app that needs OTA\n(over the air update) capability.",
+                        "id": "PARTITION_TABLE_SINGLE_APP_LARGE",
+                        "name": "PARTITION_TABLE_SINGLE_APP_LARGE",
+                        "range": null,
+                        "title": "Single factory app (large), no OTA",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice PARTITION_TABLE_TYPE>",
+                        "help": "This is a basic OTA-enabled partition table with a factory app\npartition plus two OTA app partitions. All are 1MB, so this\npartition table requires 4MB or larger flash size.\n\nThe corresponding CSV file in the IDF directory is\ncomponents/partition_table/partitions_two_ota.csv",
+                        "id": "PARTITION_TABLE_TWO_OTA",
+                        "name": "PARTITION_TABLE_TWO_OTA",
+                        "range": null,
+                        "title": "Factory app, two OTA definitions",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice PARTITION_TABLE_TYPE>",
+                        "help": "This is a basic OTA-enabled partition table with\ntwo OTA app partitions. Both app partition sizes are 1700K,\nso this partition table requires 4MB or larger flash size.\n\nThe corresponding CSV file in the IDF directory is\ncomponents/partition_table/partitions_two_ota_large.csv",
+                        "id": "PARTITION_TABLE_TWO_OTA_LARGE",
+                        "name": "PARTITION_TABLE_TWO_OTA_LARGE",
+                        "range": null,
+                        "title": "Two large size OTA partitions",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice PARTITION_TABLE_TYPE>",
+                        "help": "Specify the path to the partition table CSV to use for your project.\n\nConsult the Partition Table section in the ESP-IDF Programmers Guide\nfor more information.",
+                        "id": "PARTITION_TABLE_CUSTOM",
+                        "name": "PARTITION_TABLE_CUSTOM",
+                        "range": null,
+                        "title": "Custom partition table CSV",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "!ESP32_COREDUMP_ENABLE_TO_FLASH && NVS_SEC_KEY_PROTECT_USING_FLASH_ENC && <choice PARTITION_TABLE_TYPE>",
+                        "help": "This is a variation of the default \"Single factory app, no OTA\" partition table\nthat supports encrypted NVS when using flash encryption. See the Flash Encryption section\nin the ESP-IDF Programmers Guide for more information.\n\nThe corresponding CSV file in the IDF directory is\ncomponents/partition_table/partitions_singleapp_encr_nvs.csv",
+                        "id": "PARTITION_TABLE_SINGLE_APP_ENCRYPTED_NVS",
+                        "name": "PARTITION_TABLE_SINGLE_APP_ENCRYPTED_NVS",
+                        "range": null,
+                        "title": "Single factory app, no OTA, encrypted NVS",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "!ESP32_COREDUMP_ENABLE_TO_FLASH && NVS_SEC_KEY_PROTECT_USING_FLASH_ENC && <choice PARTITION_TABLE_TYPE>",
+                        "help": "This is a variation of the \"Single factory app (large), no OTA\" partition table\nthat supports encrypted NVS when using flash encryption. See the Flash Encryption section\nin the ESP-IDF Programmers Guide for more information.\n\nThe corresponding CSV file in the IDF directory is\ncomponents/partition_table/partitions_singleapp_large_encr_nvs.csv",
+                        "id": "PARTITION_TABLE_SINGLE_APP_LARGE_ENC_NVS",
+                        "name": "PARTITION_TABLE_SINGLE_APP_LARGE_ENC_NVS",
+                        "range": null,
+                        "title": "Single factory app (large), no OTA, encrypted NVS",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "!ESP_COREDUMP_ENABLE_TO_FLASH && NVS_SEC_KEY_PROTECT_USING_FLASH_ENC && <choice PARTITION_TABLE_TYPE>",
+                        "help": "This is a variation of the \"Factory app, two OTA definitions\" partition table\nthat supports encrypted NVS when using flash encryption. See the Flash Encryption section\nin the ESP-IDF Programmers Guide for more information.\n\nThe corresponding CSV file in the IDF directory is\ncomponents/partition_table/partitions_two_ota_encr_nvs.csv",
+                        "id": "PARTITION_TABLE_TWO_OTA_ENCRYPTED_NVS",
+                        "name": "PARTITION_TABLE_TWO_OTA_ENCRYPTED_NVS",
+                        "range": null,
+                        "title": "Factory app, two OTA definitions, encrypted NVS",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": null,
+                "help": "The partition table to flash to the ESP32. The partition table\ndetermines where apps, data and other resources are expected to\nbe found.\n\nThe predefined partition table CSV descriptions can be found\nin the components/partition_table directory. These are mostly intended\nfor example and development use, it's expect that for production use you\nwill copy one of these CSV files and create a custom partition CSV for\nyour application.",
+                "id": "partition-table-partition-table",
+                "name": "PARTITION_TABLE_TYPE",
+                "title": "Partition Table",
+                "type": "choice"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": "Name of the custom partition CSV filename.\nThis path is evaluated relative to the project root directory by default.\nHowever, if the absolute path for the CSV file is provided, then the absolute path is configured.",
+                "id": "PARTITION_TABLE_CUSTOM_FILENAME",
+                "name": "PARTITION_TABLE_CUSTOM_FILENAME",
+                "range": null,
+                "title": "Custom partition CSV file",
+                "type": "string"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": null,
+                "id": "PARTITION_TABLE_FILENAME",
+                "name": "PARTITION_TABLE_FILENAME",
+                "range": null,
+                "title": null,
+                "type": "string"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": "The address of partition table (by default 0x8000).\nAllows you to move the partition table, it gives more space for the bootloader.\nNote that the bootloader and app will both need to be compiled with the same PARTITION_TABLE_OFFSET value.\n\nThis number should be a multiple of 0x1000.\n\nNote that partition offsets in the partition table CSV file may need to be changed if this value is set to\na higher value. To have each partition offset adapt to the configured partition table offset, leave all\npartition offsets blank in the CSV file.",
+                "id": "PARTITION_TABLE_OFFSET",
+                "name": "PARTITION_TABLE_OFFSET",
+                "range": null,
+                "title": "Offset of partition table",
+                "type": "hex"
+            },
+            {
+                "children": [],
+                "depends_on": "!APP_COMPATIBLE_PRE_V3_1_BOOTLOADERS && !IDF_TARGET_LINUX",
+                "help": "Generate an MD5 checksum for the partition table for protecting the\nintegrity of the table. The generation should be turned off for legacy\nbootloaders which cannot recognize the MD5 checksum in the partition\ntable.",
+                "id": "PARTITION_TABLE_MD5",
+                "name": "PARTITION_TABLE_MD5",
+                "range": null,
+                "title": "Generate an MD5 checksum for the partition table",
+                "type": "bool"
+            }
+        ],
+        "depends_on": null,
+        "id": "partition-table",
+        "title": "Partition Table",
+        "type": "menu"
+    },
+    {
+        "children": [
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "<choice COMPILER_OPTIMIZATION>",
+                        "help": null,
+                        "id": "COMPILER_OPTIMIZATION_DEBUG",
+                        "name": "COMPILER_OPTIMIZATION_DEBUG",
+                        "range": null,
+                        "title": "Debug (-Og)",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice COMPILER_OPTIMIZATION>",
+                        "help": null,
+                        "id": "COMPILER_OPTIMIZATION_SIZE",
+                        "name": "COMPILER_OPTIMIZATION_SIZE",
+                        "range": null,
+                        "title": "Optimize for size (-Os with GCC, -Oz with Clang)",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice COMPILER_OPTIMIZATION>",
+                        "help": null,
+                        "id": "COMPILER_OPTIMIZATION_PERF",
+                        "name": "COMPILER_OPTIMIZATION_PERF",
+                        "range": null,
+                        "title": "Optimize for performance (-O2)",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice COMPILER_OPTIMIZATION>",
+                        "help": null,
+                        "id": "COMPILER_OPTIMIZATION_NONE",
+                        "name": "COMPILER_OPTIMIZATION_NONE",
+                        "range": null,
+                        "title": "Debug without optimization (-O0)",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": null,
+                "help": "This option sets compiler optimization level (gcc -O argument) for the app.\n\n- The \"Debug\" setting will add the -Og flag to CFLAGS.\n- The \"Size\" setting will add the -Os flag to CFLAGS (-Oz with Clang).\n- The \"Performance\" setting will add the -O2 flag to CFLAGS.\n- The \"None\" setting will add the -O0 flag to CFLAGS.\n\nThe \"Size\" setting cause the compiled code to be smaller and faster, but\nmay lead to difficulties of correlating code addresses to source file\nlines when debugging.\n\nThe \"Performance\" setting causes the compiled code to be larger and faster,\nbut will be easier to correlated code addresses to source file lines.\n\n\"None\" with -O0 produces compiled code without optimization.\n\nNote that custom optimization levels may be unsupported.\n\nCompiler optimization for the IDF bootloader is set separately,\nsee the BOOTLOADER_COMPILER_OPTIMIZATION setting.",
+                "id": "compiler-options-optimization-level",
+                "name": "COMPILER_OPTIMIZATION",
+                "title": "Optimization Level",
+                "type": "choice"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "<choice COMPILER_OPTIMIZATION_ASSERTION_LEVEL>",
+                        "help": "Enable assertions. Assertion content and line number will be printed on failure.",
+                        "id": "COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE",
+                        "name": "COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE",
+                        "range": null,
+                        "title": "Enabled",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice COMPILER_OPTIMIZATION_ASSERTION_LEVEL>",
+                        "help": "Enable silent assertions. Failed assertions will abort(), user needs to\nuse the aborting address to find the line number with the failed assertion.",
+                        "id": "COMPILER_OPTIMIZATION_ASSERTIONS_SILENT",
+                        "name": "COMPILER_OPTIMIZATION_ASSERTIONS_SILENT",
+                        "range": null,
+                        "title": "Silent (saves code size)",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice COMPILER_OPTIMIZATION_ASSERTION_LEVEL>",
+                        "help": "If assertions are disabled, -DNDEBUG is added to CPPFLAGS.",
+                        "id": "COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE",
+                        "name": "COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE",
+                        "range": null,
+                        "title": "Disabled (sets -DNDEBUG)",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": null,
+                "help": "Assertions can be:\n\n- Enabled. Failure will print verbose assertion details. This is the default.\n\n- Set to \"silent\" to save code size (failed assertions will abort() but user\n  needs to use the aborting address to find the line number with the failed assertion.)\n\n- Disabled entirely (not recommended for most configurations.) -DNDEBUG is added\n  to CPPFLAGS in this case.",
+                "id": "compiler-options-assertion-level",
+                "name": "COMPILER_OPTIMIZATION_ASSERTION_LEVEL",
+                "title": "Assertion level",
+                "type": "choice"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": "When NDEBUG is set, assert(X) will not cause code to trigger an assertion.\nWith this option set, assert(X) will still evaluate the expression X, though\nthe result will never cause an assertion. This means that if X is a function\nthen the function will be called.\n\nThis is not according to the standard, which states that the assert(X) should\nbe replaced with ((void)0) if NDEBUG is defined.\n\nIn ESP-IDF v6.0 the default behavior will change to \"no\" to be in line with the\nstandard.",
+                "id": "COMPILER_ASSERT_NDEBUG_EVALUATE",
+                "name": "COMPILER_ASSERT_NDEBUG_EVALUATE",
+                "range": null,
+                "title": "Enable the evaluation of the expression inside assert(X) when NDEBUG is set",
+                "type": "bool"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "<choice COMPILER_FLOAT_LIB_FROM>",
+                        "help": null,
+                        "id": "COMPILER_FLOAT_LIB_FROM_GCCLIB",
+                        "name": "COMPILER_FLOAT_LIB_FROM_GCCLIB",
+                        "range": null,
+                        "title": "libgcc",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "ESP_ROM_HAS_RVFPLIB && <choice COMPILER_FLOAT_LIB_FROM>",
+                        "help": null,
+                        "id": "COMPILER_FLOAT_LIB_FROM_RVFPLIB",
+                        "name": "COMPILER_FLOAT_LIB_FROM_RVFPLIB",
+                        "range": null,
+                        "title": "librvfp",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": null,
+                "help": "In the soft-fp part of libgcc, riscv version is written in C,\nand handles all edge cases in IEEE754, which makes it larger\nand performance is slow.\n\nRVfplib is an optimized RISC-V library for FP arithmetic on 32-bit\ninteger processors, for single and double-precision FP.\nRVfplib is \"fast\", but it has a few exceptions from IEEE 754 compliance.",
+                "id": "compiler-options-compiler-float-lib-source",
+                "name": "COMPILER_FLOAT_LIB_FROM",
+                "title": "Compiler float lib source",
+                "type": "choice"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": null,
+                "id": "COMPILER_OPTIMIZATION_ASSERTION_LEVEL",
+                "name": "COMPILER_OPTIMIZATION_ASSERTION_LEVEL",
+                "range": null,
+                "title": null,
+                "type": "int"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": "If enabled, the error messages will be discarded in following check macros:\n- ESP_RETURN_ON_ERROR\n- ESP_EXIT_ON_ERROR\n- ESP_RETURN_ON_FALSE\n- ESP_EXIT_ON_FALSE",
+                "id": "COMPILER_OPTIMIZATION_CHECKS_SILENT",
+                "name": "COMPILER_OPTIMIZATION_CHECKS_SILENT",
+                "range": null,
+                "title": "Disable messages in ESP_RETURN_ON_* and ESP_EXIT_ON_* macros",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": "When expanding the __FILE__ and __BASE_FILE__ macros, replace paths inside ESP-IDF\nwith paths relative to the placeholder string \"IDF\", and convert paths inside the\nproject directory to relative paths.\n\nThis allows building the project with assertions or other code that embeds file paths,\nwithout the binary containing the exact path to the IDF or project directories.\n\nThis option passes -fmacro-prefix-map options to the GCC command line. To replace additional\npaths in your binaries, modify the project CMakeLists.txt file to pass custom -fmacro-prefix-map or\n-ffile-prefix-map arguments.",
+                "id": "COMPILER_HIDE_PATHS_MACROS",
+                "is_menuconfig": true,
+                "name": "COMPILER_HIDE_PATHS_MACROS",
+                "range": null,
+                "title": "Replace ESP-IDF and project paths in binaries",
+                "type": "menu"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "COMPILER_CXX_EXCEPTIONS",
+                        "help": "Size (in bytes) of the emergency memory pool for C++ exceptions. This pool will be used to allocate\nmemory for thrown exceptions when there is not enough memory on the heap.",
+                        "id": "COMPILER_CXX_EXCEPTIONS_EMG_POOL_SIZE",
+                        "name": "COMPILER_CXX_EXCEPTIONS_EMG_POOL_SIZE",
+                        "range": null,
+                        "title": "Emergency Pool Size",
+                        "type": "int"
+                    }
+                ],
+                "depends_on": null,
+                "help": "Enabling this option compiles all IDF C++ files with exception support enabled.\n\nDisabling this option disables C++ exception support in all compiled files, and any libstdc++ code\nwhich throws an exception will abort instead.\n\nEnabling this option currently adds an additional ~500 bytes of heap overhead\nwhen an exception is thrown in user code for the first time.",
+                "id": "COMPILER_CXX_EXCEPTIONS",
+                "is_menuconfig": true,
+                "name": "COMPILER_CXX_EXCEPTIONS",
+                "range": null,
+                "title": "Enable C++ exceptions",
+                "type": "menu"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": "Enabling this option compiles all C++ files with RTTI support enabled.\nThis increases binary size (typically by tens of kB) but allows using\ndynamic_cast conversion and typeid operator.",
+                "id": "COMPILER_CXX_RTTI",
+                "name": "COMPILER_CXX_RTTI",
+                "range": null,
+                "title": "Enable C++ run-time type info (RTTI)",
+                "type": "bool"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "<choice COMPILER_STACK_CHECK_MODE>",
+                        "help": null,
+                        "id": "COMPILER_STACK_CHECK_MODE_NONE",
+                        "name": "COMPILER_STACK_CHECK_MODE_NONE",
+                        "range": null,
+                        "title": "None",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice COMPILER_STACK_CHECK_MODE>",
+                        "help": null,
+                        "id": "COMPILER_STACK_CHECK_MODE_NORM",
+                        "name": "COMPILER_STACK_CHECK_MODE_NORM",
+                        "range": null,
+                        "title": "Normal",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice COMPILER_STACK_CHECK_MODE>",
+                        "help": null,
+                        "id": "COMPILER_STACK_CHECK_MODE_STRONG",
+                        "name": "COMPILER_STACK_CHECK_MODE_STRONG",
+                        "range": null,
+                        "title": "Strong",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice COMPILER_STACK_CHECK_MODE>",
+                        "help": null,
+                        "id": "COMPILER_STACK_CHECK_MODE_ALL",
+                        "name": "COMPILER_STACK_CHECK_MODE_ALL",
+                        "range": null,
+                        "title": "Overall",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": null,
+                "help": "Stack smashing protection mode. Emit extra code to check for buffer overflows, such as stack\nsmashing attacks. This is done by adding a guard variable to functions with vulnerable objects.\nThe guards are initialized when a function is entered and then checked when the function exits.\nIf a guard check fails, program is halted. Protection has the following modes:\n\n- In NORMAL mode (GCC flag: -fstack-protector) only functions that call alloca, and functions with\n  buffers larger than 8 bytes are protected.\n\n- STRONG mode (GCC flag: -fstack-protector-strong) is like NORMAL, but includes additional functions\n  to be protected -- those that have local array definitions, or have references to local frame\n  addresses.\n\n- In OVERALL mode (GCC flag: -fstack-protector-all) all functions are protected.\n\nModes have the following impact on code performance and coverage:\n\n- performance: NORMAL > STRONG > OVERALL\n\n- coverage: NORMAL < STRONG < OVERALL\n\nThe performance impact includes increasing the amount of stack memory required for each task.",
+                "id": "compiler-options-stack-smashing-protection-mode",
+                "name": "COMPILER_STACK_CHECK_MODE",
+                "title": "Stack smashing protection mode",
+                "type": "choice"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": "Stack smashing protection.",
+                "id": "COMPILER_STACK_CHECK",
+                "name": "COMPILER_STACK_CHECK",
+                "range": null,
+                "title": null,
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": "IDF_TOOLCHAIN_GCC",
+                "help": "Disable merging identical constants (string/floating-point) across compilation units.\nThis helps in better size analysis of the application binary as the rodata section\ndistribution is more uniform across libraries. On downside, it may increase\nthe binary size and hence should be used during development phase only.",
+                "id": "COMPILER_NO_MERGE_CONSTANTS",
+                "name": "COMPILER_NO_MERGE_CONSTANTS",
+                "range": null,
+                "title": "Disable merging const sections",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": "Adds -Wwrite-strings flag for the C/C++ compilers.\n\nFor C, this gives string constants the type ``const char[]`` so that\ncopying the address of one into a non-const ``char *`` pointer\nproduces a warning. This warning helps to find at compile time code\nthat tries to write into a string constant.\n\nFor C++, this warns about the deprecated conversion from string\nliterals to ``char *``.",
+                "id": "COMPILER_WARN_WRITE_STRINGS",
+                "name": "COMPILER_WARN_WRITE_STRINGS",
+                "range": null,
+                "title": "Enable -Wwrite-strings warning flag",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": "IDF_TARGET_ARCH_RISCV",
+                "help": "Adds -msave-restore to C/C++ compilation flags.\n\nWhen this flag is enabled, compiler will call library functions to\nsave/restore registers in function prologues/epilogues. This results\nin lower overall code size, at the expense of slightly reduced performance.\n\nThis option can be enabled for RISC-V targets only.",
+                "id": "COMPILER_SAVE_RESTORE_LIBCALLS",
+                "name": "COMPILER_SAVE_RESTORE_LIBCALLS",
+                "range": null,
+                "title": "Enable -msave-restore flag to reduce code size",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": "Enable this option if you do not want default warnings to be considered as errors,\nespecially when updating IDF.\n\nThis is a temporary flag that could help to allow upgrade while having\nsome time to address the warnings raised by those default warnings.\nAlternatives are:\n1) fix code (preferred),\n2) remove specific warnings,\n3) do not consider specific warnings as error.",
+                "id": "COMPILER_DISABLE_DEFAULT_ERRORS",
+                "name": "COMPILER_DISABLE_DEFAULT_ERRORS",
+                "range": null,
+                "title": "Disable errors for default warnings",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": "Enable this option if use GCC 12 or newer, and want to disable warnings which don't appear with\nGCC 11.",
+                "id": "COMPILER_DISABLE_GCC12_WARNINGS",
+                "name": "COMPILER_DISABLE_GCC12_WARNINGS",
+                "range": null,
+                "title": "Disable new warnings introduced in GCC 12",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": "Enable this option if use GCC 13 or newer, and want to disable warnings which don't appear with\nGCC 12.",
+                "id": "COMPILER_DISABLE_GCC13_WARNINGS",
+                "name": "COMPILER_DISABLE_GCC13_WARNINGS",
+                "range": null,
+                "title": "Disable new warnings introduced in GCC 13",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": "Enable this option if use GCC 14 or newer, and want to disable warnings which don't appear with\nGCC 13.",
+                "id": "COMPILER_DISABLE_GCC14_WARNINGS",
+                "name": "COMPILER_DISABLE_GCC14_WARNINGS",
+                "range": null,
+                "title": "Disable new warnings introduced in GCC 14",
+                "type": "bool"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": "If enabled, RTL files will be produced during compilation. These files\ncan be used by other tools, for example to calculate call graphs.",
+                "id": "COMPILER_DUMP_RTL_FILES",
+                "name": "COMPILER_DUMP_RTL_FILES",
+                "range": null,
+                "title": "Dump RTL files during compilation",
+                "type": "bool"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "!IDF_TARGET_LINUX && <choice COMPILER_RT_LIB>",
+                        "help": null,
+                        "id": "COMPILER_RT_LIB_GCCLIB",
+                        "name": "COMPILER_RT_LIB_GCCLIB",
+                        "range": null,
+                        "title": "libgcc",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "IDF_TOOLCHAIN_CLANG && !IDF_TARGET_LINUX && <choice COMPILER_RT_LIB>",
+                        "help": null,
+                        "id": "COMPILER_RT_LIB_CLANGRT",
+                        "name": "COMPILER_RT_LIB_CLANGRT",
+                        "range": null,
+                        "title": "libclang_rt",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "IDF_TARGET_LINUX && <choice COMPILER_RT_LIB>",
+                        "help": null,
+                        "id": "COMPILER_RT_LIB_HOST",
+                        "name": "COMPILER_RT_LIB_HOST",
+                        "range": null,
+                        "title": "Host",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": null,
+                "help": "Select runtime library to be used by compiler.\n- GCC toolchain supports libgcc only.\n- Clang allows to choose between libgcc or libclang_rt.\n- For host builds (\"linux\" target), uses the default library.",
+                "id": "compiler-options-compiler-runtime-library",
+                "name": "COMPILER_RT_LIB",
+                "title": "Compiler runtime library",
+                "type": "choice"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": null,
+                "id": "COMPILER_RT_LIB_NAME",
+                "name": "COMPILER_RT_LIB_NAME",
+                "range": null,
+                "title": null,
+                "type": "string"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": "<choice COMPILER_ORPHAN_SECTIONS>",
+                        "help": "Places orphan sections with a warning message.",
+                        "id": "COMPILER_ORPHAN_SECTIONS_WARNING",
+                        "name": "COMPILER_ORPHAN_SECTIONS_WARNING",
+                        "range": null,
+                        "title": "Place with warning",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "<choice COMPILER_ORPHAN_SECTIONS>",
+                        "help": "Places orphan sections without a warning/error message.",
+                        "id": "COMPILER_ORPHAN_SECTIONS_PLACE",
+                        "name": "COMPILER_ORPHAN_SECTIONS_PLACE",
+                        "range": null,
+                        "title": "Place silently",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": "!IDF_TARGET_LINUX",
+                "help": "If the linker finds orphan sections, it attempts to place orphan sections after sections of the same\nattribute such as code vs data, loadable vs non-loadable, etc.\nThat means that orphan sections could placed between sections defined in IDF linker scripts.\nThis could lead to corruption of the binary image. Configure the linker action here.",
+                "id": "compiler-options-orphan-sections-handling",
+                "name": "COMPILER_ORPHAN_SECTIONS",
+                "title": "Orphan sections handling",
+                "type": "choice"
+            },
+            {
+                "children": [],
+                "depends_on": "IDF_TOOLCHAIN_GCC",
+                "help": "Enable compiler static analyzer. This may produce false-positive results and increases compile time.",
+                "id": "COMPILER_STATIC_ANALYZER",
+                "name": "COMPILER_STATIC_ANALYZER",
+                "range": null,
+                "title": "Enable compiler static analyzer",
+                "type": "bool"
+            }
+        ],
+        "depends_on": null,
+        "id": "compiler-options",
+        "title": "Compiler options",
+        "type": "menu"
+    },
+    {
+        "children": [
+            {
+                "children": [
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "EFUSE_CUSTOM_TABLE",
+                                "help": "Name of the custom eFuse CSV filename. This path is evaluated\nrelative to the project root directory.",
+                                "id": "EFUSE_CUSTOM_TABLE_FILENAME",
+                                "name": "EFUSE_CUSTOM_TABLE_FILENAME",
+                                "range": null,
+                                "title": "Custom eFuse CSV file",
+                                "type": "string"
+                            }
+                        ],
+                        "depends_on": null,
+                        "help": "Allows to generate a structure for eFuse from the CSV file.",
+                        "id": "EFUSE_CUSTOM_TABLE",
+                        "name": "EFUSE_CUSTOM_TABLE",
+                        "range": null,
+                        "title": "Use custom eFuse table",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "EFUSE_VIRTUAL && !IDF_TARGET_LINUX",
+                                "help": "In addition to the \"Simulate eFuse operations in RAM\" option, this option just adds\na feature to keep eFuses after reboots in flash memory. To use this mode the partition_table\nshould have the `efuse` partition. partition.csv: \"efuse_em, data, efuse,   ,   0x2000,\"\n\nDuring startup, the eFuses are copied from flash or,\nin case if flash is empty, from real eFuse to RAM and then update flash.\nThis mode is useful when need to keep changes after reboot\n(testing secure_boot and flash_encryption).",
+                                "id": "EFUSE_VIRTUAL_KEEP_IN_FLASH",
+                                "name": "EFUSE_VIRTUAL_KEEP_IN_FLASH",
+                                "range": null,
+                                "title": "Keep eFuses in flash",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "EFUSE_VIRTUAL",
+                                "help": "If enabled, log efuse burns. This shows changes that would be made.",
+                                "id": "EFUSE_VIRTUAL_LOG_ALL_WRITES",
+                                "name": "EFUSE_VIRTUAL_LOG_ALL_WRITES",
+                                "range": null,
+                                "title": "Log all virtual writes",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": null,
+                        "help": "If \"n\" - No virtual mode. All eFuse operations are real and use eFuse registers.\nIf \"y\" - The virtual mode is enabled and all eFuse operations (read and write) are redirected\nto RAM instead of eFuse registers, all permanent changes (via eFuse) are disabled.\nLog output will state changes that would be applied, but they will not be.\n\nIf it is \"y\", then SECURE_FLASH_ENCRYPTION_MODE_RELEASE cannot be used.\nBecause the EFUSE VIRT mode is for testing only.\n\nDuring startup, the eFuses are copied into RAM. This mode is useful for fast tests.",
+                        "id": "EFUSE_VIRTUAL",
+                        "name": "EFUSE_VIRTUAL",
+                        "range": null,
+                        "title": "Simulate eFuse operations in RAM",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "<choice EFUSE_CODE_SCHEME_SELECTOR>",
+                                "help": null,
+                                "id": "EFUSE_CODE_SCHEME_COMPAT_NONE",
+                                "name": "EFUSE_CODE_SCHEME_COMPAT_NONE",
+                                "range": null,
+                                "title": "None Only",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice EFUSE_CODE_SCHEME_SELECTOR>",
+                                "help": null,
+                                "id": "EFUSE_CODE_SCHEME_COMPAT_3_4",
+                                "name": "EFUSE_CODE_SCHEME_COMPAT_3_4",
+                                "range": null,
+                                "title": "3/4 and None",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice EFUSE_CODE_SCHEME_SELECTOR>",
+                                "help": null,
+                                "id": "EFUSE_CODE_SCHEME_COMPAT_REPEAT",
+                                "name": "EFUSE_CODE_SCHEME_COMPAT_REPEAT",
+                                "range": null,
+                                "title": "Repeat, 3/4 and None (common table does not support it)",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": "IDF_TARGET_ESP32",
+                        "help": "Selector eFuse code scheme.",
+                        "id": "component-config-efuse-bit-manager-coding-scheme-compatibility",
+                        "name": "EFUSE_CODE_SCHEME_SELECTOR",
+                        "title": "Coding Scheme Compatibility",
+                        "type": "choice"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": null,
+                        "id": "EFUSE_MAX_BLK_LEN",
+                        "name": "EFUSE_MAX_BLK_LEN",
+                        "range": null,
+                        "title": null,
+                        "type": "int"
+                    }
+                ],
+                "depends_on": null,
+                "id": "component-config-efuse-bit-manager",
+                "title": "eFuse Bit Manager",
+                "type": "menu"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": "Functions esp_err_to_name() and esp_err_to_name_r() return string representations of error codes from a\npre-generated lookup table. This option can be used to turn off the use of the look-up table in order to\nsave memory but this comes at the price of sacrificing distinguishable (meaningful) output string\nrepresentations.",
+                        "id": "ESP_ERR_TO_NAME_LOOKUP",
+                        "name": "ESP_ERR_TO_NAME_LOOKUP",
+                        "range": null,
+                        "title": "Enable lookup of error code strings",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": null,
+                        "id": "ESP_ALLOW_BSS_SEG_EXTERNAL_MEMORY",
+                        "name": "ESP_ALLOW_BSS_SEG_EXTERNAL_MEMORY",
+                        "range": null,
+                        "title": null,
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": null,
+                "id": "component-config-common-esp-related",
+                "title": "Common ESP-related",
+                "type": "menu"
+            },
+            {
+                "children": [
+                    {
+                        "children": [
+                            {
+                                "children": [
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice ESP32C3_REV_MIN>",
+                                        "help": null,
+                                        "id": "ESP32C3_REV_MIN_0",
+                                        "name": "ESP32C3_REV_MIN_0",
+                                        "range": null,
+                                        "title": "Rev v0.0 (ECO0)",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice ESP32C3_REV_MIN>",
+                                        "help": null,
+                                        "id": "ESP32C3_REV_MIN_1",
+                                        "name": "ESP32C3_REV_MIN_1",
+                                        "range": null,
+                                        "title": "Rev v0.1 (ECO1)",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice ESP32C3_REV_MIN>",
+                                        "help": null,
+                                        "id": "ESP32C3_REV_MIN_2",
+                                        "name": "ESP32C3_REV_MIN_2",
+                                        "range": null,
+                                        "title": "Rev v0.2 (ECO2)",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice ESP32C3_REV_MIN>",
+                                        "help": null,
+                                        "id": "ESP32C3_REV_MIN_3",
+                                        "name": "ESP32C3_REV_MIN_3",
+                                        "range": null,
+                                        "title": "Rev v0.3 (ECO3)",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice ESP32C3_REV_MIN>",
+                                        "help": null,
+                                        "id": "ESP32C3_REV_MIN_4",
+                                        "name": "ESP32C3_REV_MIN_4",
+                                        "range": null,
+                                        "title": "Rev v0.4 (ECO4)",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice ESP32C3_REV_MIN>",
+                                        "help": null,
+                                        "id": "ESP32C3_REV_MIN_101",
+                                        "name": "ESP32C3_REV_MIN_101",
+                                        "range": null,
+                                        "title": "Rev v1.1",
+                                        "type": "bool"
+                                    }
+                                ],
+                                "depends_on": null,
+                                "help": "Required minimum chip revision. ESP-IDF will check for it and\nreject to boot if the chip revision fails the check.\nThis ensures the chip used will have some modifications (features, or bugfixes).\n\nThe complied binary will only support chips above this revision,\nthis will also help to reduce binary size.",
+                                "id": "component-config-hardware-settings-chip-revision-minimum-supported-esp32-c3-revision",
+                                "name": "ESP32C3_REV_MIN",
+                                "title": "Minimum Supported ESP32-C3 Revision",
+                                "type": "choice"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "ESP32C3_REV_MIN_FULL",
+                                "name": "ESP32C3_REV_MIN_FULL",
+                                "range": null,
+                                "title": null,
+                                "type": "int"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "ESP_REV_MIN_FULL",
+                                "name": "ESP_REV_MIN_FULL",
+                                "range": null,
+                                "title": null,
+                                "type": "int"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "ESP32C3_REV_MAX_FULL",
+                                "name": "ESP32C3_REV_MAX_FULL",
+                                "range": null,
+                                "title": null,
+                                "type": "int"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "ESP_REV_MAX_FULL",
+                                "name": "ESP_REV_MAX_FULL",
+                                "range": null,
+                                "title": null,
+                                "type": "int"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "Required minimum eFuse Block revision. ESP-IDF will check it at the 2nd bootloader stage\nwhether the current image can work correctly for this eFuse Block revision.\nSo that to avoid running an incompatible image on a SoC that contains breaking change in the eFuse Block.\nIf you want to update this value to run the image that not compatible with the current eFuse Block revision,\nplease contact to Espressif's business team for details:\nhttps://www.espressif.com.cn/en/contact-us/sales-questions",
+                                "id": "ESP_EFUSE_BLOCK_REV_MIN_FULL",
+                                "name": "ESP_EFUSE_BLOCK_REV_MIN_FULL",
+                                "range": null,
+                                "title": "Minimum Supported ESP32-C3 eFuse Block Revision",
+                                "type": "int"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "ESP_EFUSE_BLOCK_REV_MAX_FULL",
+                                "name": "ESP_EFUSE_BLOCK_REV_MAX_FULL",
+                                "range": null,
+                                "title": null,
+                                "type": "int"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "IDF_CI_BUILD",
+                                "help": "For internal chip testing, a small number of new versions chips didn't\nupdate the version field in eFuse, you can enable this option to force the\nsoftware recognize the chip version based on the rev selected in menuconfig.",
+                                "id": "ESP_REV_NEW_CHIP_TEST",
+                                "name": "ESP_REV_NEW_CHIP_TEST",
+                                "range": null,
+                                "title": "Internal test mode",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": null,
+                        "id": "component-config-hardware-settings-chip-revision",
+                        "title": "Chip revision",
+                        "type": "menu"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "ESP_MAC_ADDR_UNIVERSE_WIFI_STA",
+                                "name": "ESP_MAC_ADDR_UNIVERSE_WIFI_STA",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "ESP_MAC_ADDR_UNIVERSE_WIFI_AP",
+                                "name": "ESP_MAC_ADDR_UNIVERSE_WIFI_AP",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "ESP_MAC_ADDR_UNIVERSE_BT",
+                                "name": "ESP_MAC_ADDR_UNIVERSE_BT",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "ESP_MAC_ADDR_UNIVERSE_ETH",
+                                "name": "ESP_MAC_ADDR_UNIVERSE_ETH",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "ESP_MAC_ADDR_UNIVERSE_IEEE802154",
+                                "name": "ESP_MAC_ADDR_UNIVERSE_IEEE802154",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "ESP_MAC_UNIVERSAL_MAC_ADDRESSES_ONE",
+                                "name": "ESP_MAC_UNIVERSAL_MAC_ADDRESSES_ONE",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "ESP_MAC_UNIVERSAL_MAC_ADDRESSES_TWO",
+                                "name": "ESP_MAC_UNIVERSAL_MAC_ADDRESSES_TWO",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR",
+                                "name": "ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "ESP_MAC_UNIVERSAL_MAC_ADDRESSES",
+                                "name": "ESP_MAC_UNIVERSAL_MAC_ADDRESSES",
+                                "range": null,
+                                "title": null,
+                                "type": "int"
+                            },
+                            {
+                                "children": [
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice ESP32C3_UNIVERSAL_MAC_ADDRESSES>",
+                                        "help": null,
+                                        "id": "ESP32C3_UNIVERSAL_MAC_ADDRESSES_TWO",
+                                        "name": "ESP32C3_UNIVERSAL_MAC_ADDRESSES_TWO",
+                                        "range": null,
+                                        "title": "Two",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice ESP32C3_UNIVERSAL_MAC_ADDRESSES>",
+                                        "help": null,
+                                        "id": "ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR",
+                                        "name": "ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR",
+                                        "range": null,
+                                        "title": "Four",
+                                        "type": "bool"
+                                    }
+                                ],
+                                "depends_on": null,
+                                "help": "Configure the number of universally administered (by IEEE) MAC addresses.\n\nDuring initialization, MAC addresses for each network interface are generated or derived from a\nsingle base MAC address.\n\nIf the number of universal MAC addresses is four, all four interfaces (WiFi station, WiFi softap,\nBluetooth and Ethernet) receive a universally administered MAC address. These are generated\nsequentially by adding 0, 1, 2 and 3 (respectively) to the final octet of the base MAC address.\n\nIf the number of universal MAC addresses is two, only two interfaces (WiFi station and Bluetooth)\nreceive a universally administered MAC address. These are generated sequentially by adding 0\nand 1 (respectively) to the base MAC address. The remaining two interfaces (WiFi softap and Ethernet)\nreceive local MAC addresses. These are derived from the universal WiFi station and Bluetooth MAC\naddresses, respectively.\n\nWhen using the default (Espressif-assigned) base MAC address, either setting can be used. When using\na custom universal MAC address range, the correct setting will depend on the allocation of MAC\naddresses in this range (either 2 or 4 per device.)\n\nNote that ESP32-C3 has no integrated Ethernet MAC. Although it's possible to use the esp_read_mac()\nAPI to return a MAC for Ethernet, this can only be used with an external MAC peripheral.",
+                                "id": "component-config-hardware-settings-mac-config-number-of-universally-administered-by-ieee-mac-address",
+                                "name": "ESP32C3_UNIVERSAL_MAC_ADDRESSES",
+                                "title": "Number of universally administered (by IEEE) MAC address",
+                                "type": "choice"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "ESP32C3_UNIVERSAL_MAC_ADDRESSES",
+                                "name": "ESP32C3_UNIVERSAL_MAC_ADDRESSES",
+                                "range": null,
+                                "title": null,
+                                "type": "int"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "IDF_TARGET_ESP32",
+                                "help": "If you have an invalid MAC CRC (ESP_ERR_INVALID_CRC) problem\nand you still want to use this chip, you can enable this option to bypass such an error.\nThis applies to both MAC_FACTORY and CUSTOM_MAC efuses.",
+                                "id": "ESP_MAC_IGNORE_MAC_CRC_ERROR",
+                                "name": "ESP_MAC_IGNORE_MAC_CRC_ERROR",
+                                "range": null,
+                                "title": "Ignore MAC CRC error (not recommended)",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "When this configuration is enabled, the user can invoke `esp_read_mac` to obtain the desired type of\nMAC using a custom MAC as the base MAC.",
+                                "id": "ESP_MAC_USE_CUSTOM_MAC_AS_BASE_MAC",
+                                "name": "ESP_MAC_USE_CUSTOM_MAC_AS_BASE_MAC",
+                                "range": null,
+                                "title": "Enable using custom mac as base mac",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": null,
+                        "id": "component-config-hardware-settings-mac-config",
+                        "title": "MAC Config",
+                        "type": "menu"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "(!SPIRAM || ESP_LDO_RESERVE_PSRAM) && !(IDF_TARGET_ESP32P4 && ESP32P4_REV_MIN_FULL < 100)",
+                                "help": "If enabled, chip will try to power down flash as part of esp_light_sleep_start(), which costs\nmore time when chip wakes up. Can only be enabled if there is no SPIRAM configured.\n\nThis option will power down flash under a strict but relatively safe condition. Also, it is possible to\npower down flash under a relaxed condition by using esp_sleep_pd_config() to set ESP_PD_DOMAIN_VDDSDIO\nto ESP_PD_OPTION_OFF. It should be noted that there is a risk in powering down flash, you can refer\n`ESP-IDF Programming Guide/API Reference/System API/Sleep Modes/Power-down of Flash` for more details.",
+                                "id": "ESP_SLEEP_POWER_DOWN_FLASH",
+                                "name": "ESP_SLEEP_POWER_DOWN_FLASH",
+                                "range": null,
+                                "title": "Power down flash in light sleep when there is no SPIRAM or SPIRAM has independent power supply",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": "All IOs will be set to isolate(floating) state by default during sleep.\nSince the power supply of SPI Flash is not lost during lightsleep, if its CS pin is recognized as\nlow level(selected state) in the floating state, there will be a large current leakage, and the\ndata in Flash may be corrupted by random signals on other SPI pins.\nSelect this option will set the CS pin of Flash to PULL-UP state during sleep, but this will\nincrease the sleep current about 10 uA.\nIf you are developing with esp32xx modules, you must select this option, but if you are developing\nwith chips, you can also pull up the CS pin of SPI Flash in the external circuit to save power\nconsumption caused by internal pull-up during sleep.\n(!!! Don't deselect this option if you don't have external SPI Flash CS pin pullups.)",
+                                "id": "ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND",
+                                "name": "ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND",
+                                "range": null,
+                                "title": "Pull-up Flash CS pin in light sleep",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "SPIRAM",
+                                "help": "All IOs will be set to isolate(floating) state by default during sleep.\nSince the power supply of PSRAM is not lost during lightsleep, if its CS pin is recognized as\nlow level(selected state) in the floating state, there will be a large current leakage, and the\ndata in PSRAM may be corrupted by random signals on other SPI pins.\nSelect this option will set the CS pin of PSRAM to PULL-UP state during sleep, but this will\nincrease the sleep current about 10 uA.\nIf you are developing with esp32xx modules, you must select this option, but if you are developing\nwith chips, you can also pull up the CS pin of PSRAM in the external circuit to save power\nconsumption caused by internal pull-up during sleep.\n(!!! Don't deselect this option if you don't have external PSRAM CS pin pullups.)",
+                                "id": "ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND",
+                                "name": "ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND",
+                                "range": null,
+                                "title": "Pull-up PSRAM CS pin in light sleep",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND || ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND",
+                                "help": "To reduce leakage current, some types of SPI Flash/RAM only need to pull up the CS pin\nduring light sleep. But there are also some kinds of SPI Flash/RAM that need to pull up\nall pins. It depends on the SPI Flash/RAM chip used.",
+                                "id": "ESP_SLEEP_MSPI_NEED_ALL_IO_PU",
+                                "name": "ESP_SLEEP_MSPI_NEED_ALL_IO_PU",
+                                "range": null,
+                                "title": "Pull-up all SPI pins in light sleep",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "ESP_SLEEP_RTC_BUS_ISO_WORKAROUND",
+                                "name": "ESP_SLEEP_RTC_BUS_ISO_WORKAROUND",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "esp32c2, esp32c3, esp32s3, esp32c5, esp32c6 and esp32h2 will reset at wake-up if GPIO is received\na small electrostatic pulse during light sleep, with specific condition\n\n- GPIO needs to be configured as input-mode only\n- The pin receives a small electrostatic pulse, and reset occurs when the pulse\n  voltage is higher than 6 V\n\nFor GPIO set to input mode only, it is not a good practice to leave it open/floating,\nThe hardware design needs to controlled it with determined supply or ground voltage\nis necessary.\n\nThis option provides a software workaround for this issue. Configure to isolate all\nGPIO pins in sleep state.",
+                                "id": "ESP_SLEEP_GPIO_RESET_WORKAROUND",
+                                "name": "ESP_SLEEP_GPIO_RESET_WORKAROUND",
+                                "range": null,
+                                "title": "light sleep GPIO reset workaround",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "When the chip exits sleep, the CPU and the flash chip are powered on at the same time.\nCPU will run rom code (deepsleep) or ram code (lightsleep) first, and then load or execute\ncode from flash.\n\nSome flash chips need sufficient time to pass between power on and first read operation.\nBy default, without any extra delay, this time is approximately 900us, although\nsome flash chip types need more than that.\n\n(!!! Please adjust this value according to the Data Sheet of SPI Flash used in your project.)\nIn Flash Data Sheet, the parameters that define the Flash ready timing after power-up (minimum\ntime from Vcc(min) to CS activeare) usually named tVSL in ELECTRICAL CHARACTERISTICS chapter,\nand the configuration value here should be:\nESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY = tVSL - 900\n\nFor esp32 and esp32s3, the default extra delay is set to 2000us. When optimizing startup time\nfor applications which require it, this value may be reduced.\n\nIf you are seeing \"flash read err, 1000\" message printed to the console after deep sleep reset\non esp32, or triggered RTC_WDT/LP_WDT after lightsleep wakeup, try increasing this value.\n(For esp32, the delay will be executed in both deep sleep and light sleep wake up flow.\nFor chips after esp32, the delay will be executed only in light sleep flow, the delay\ncontrolled by the EFUSE_FLASH_TPUW in ROM will be executed in deepsleep wake up flow.)",
+                                "id": "ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY",
+                                "name": "ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY",
+                                "range": [
+                                    0,
+                                    5000
+                                ],
+                                "title": "Extra delay (in us) after flash powerdown sleep wakeup to wait flash ready",
+                                "type": "int"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "Enabling it will check the cache safety of the code before the flash power is ready after\nlight sleep wakeup, and check PM_SLP_IRAM_OPT related code cache safety. This option is\nonly for code quality inspection. Enabling it will increase the time overhead of entering\nand exiting sleep. It is not recommended to enable it in the release version.",
+                                "id": "ESP_SLEEP_CACHE_SAFE_ASSERTION",
+                                "name": "ESP_SLEEP_CACHE_SAFE_ASSERTION",
+                                "range": null,
+                                "title": "Check the cache safety of the sleep wakeup code in sleep process",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "Enable esp sleep debug.",
+                                "id": "ESP_SLEEP_DEBUG",
+                                "name": "ESP_SLEEP_DEBUG",
+                                "range": null,
+                                "title": "esp sleep debug",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "When using rtc gpio wakeup source during deepsleep without external pull-up/downs, you may want to\nmake use of the internal ones.",
+                                "id": "ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS",
+                                "name": "ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS",
+                                "range": null,
+                                "title": "Allow to enable internal pull-up/downs for the Deep-Sleep wakeup IOs",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "FREERTOS_USE_TICKLESS_IDLE",
+                                "help": "If enabled, it allows user to register sleep event callbacks. It is primarily designed for internal\ndevelopers and customers can use PM_LIGHT_SLEEP_CALLBACKS as an alternative.\n\nNOTE: These callbacks are executed from the IDLE task context hence you cannot have any blocking calls\nin your callbacks.\n\nNOTE: Enabling these callbacks may change sleep duration calculations based on time spent in\ncallback and hence it is highly recommended to keep them as short as possible.",
+                                "id": "ESP_SLEEP_EVENT_CALLBACKS",
+                                "name": "ESP_SLEEP_EVENT_CALLBACKS",
+                                "range": null,
+                                "title": "Enable registration of sleep event callbacks",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": null,
+                        "id": "component-config-hardware-settings-sleep-config",
+                        "title": "Sleep Config",
+                        "type": "menu"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice RTC_CLK_SRC>",
+                                        "help": null,
+                                        "id": "RTC_CLK_SRC_INT_RC",
+                                        "name": "RTC_CLK_SRC_INT_RC",
+                                        "range": null,
+                                        "title": "Internal 136 kHz RC oscillator",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice RTC_CLK_SRC>",
+                                        "help": null,
+                                        "id": "RTC_CLK_SRC_EXT_CRYS",
+                                        "name": "RTC_CLK_SRC_EXT_CRYS",
+                                        "range": null,
+                                        "title": "External 32 kHz crystal",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice RTC_CLK_SRC>",
+                                        "help": null,
+                                        "id": "RTC_CLK_SRC_EXT_OSC",
+                                        "name": "RTC_CLK_SRC_EXT_OSC",
+                                        "range": null,
+                                        "title": "External 32 kHz oscillator at 32K_XP pin",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice RTC_CLK_SRC>",
+                                        "help": null,
+                                        "id": "RTC_CLK_SRC_INT_8MD256",
+                                        "name": "RTC_CLK_SRC_INT_8MD256",
+                                        "range": null,
+                                        "title": "Internal 17.5 MHz oscillator, divided by 256",
+                                        "type": "bool"
+                                    }
+                                ],
+                                "depends_on": null,
+                                "help": "Choose which clock is used as RTC clock source.",
+                                "id": "component-config-hardware-settings-rtc-clock-config-rtc-clock-source",
+                                "name": "RTC_CLK_SRC",
+                                "title": "RTC clock source",
+                                "type": "choice"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "When the startup code initializes RTC_SLOW_CLK, it can perform\ncalibration by comparing the RTC_SLOW_CLK frequency with main XTAL\nfrequency. This option sets the number of RTC_SLOW_CLK cycles measured\nby the calibration routine. Higher numbers increase calibration\nprecision, which may be important for applications which spend a lot of\ntime in deep sleep. Lower numbers reduce startup time.\n\nWhen this option is set to 0, clock calibration will not be performed at\nstartup, and approximate clock frequencies will be assumed:\n\n- 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024.\n- 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.\n    In case more value will help improve the definition of the launch of the crystal.\n    If the crystal could not start, it will be switched to internal RC.",
+                                "id": "RTC_CLK_CAL_CYCLES",
+                                "name": "RTC_CLK_CAL_CYCLES",
+                                "range": [
+                                    0,
+                                    32766
+                                ],
+                                "title": "Number of cycles for RTC_SLOW_CLK calibration",
+                                "type": "int"
+                            }
+                        ],
+                        "depends_on": null,
+                        "id": "component-config-hardware-settings-rtc-clock-config",
+                        "title": "RTC Clock Config",
+                        "type": "menu"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "Place peripheral control functions (e.g. periph_module_reset) into IRAM,\nso that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context.",
+                                "id": "PERIPH_CTRL_FUNC_IN_IRAM",
+                                "name": "PERIPH_CTRL_FUNC_IN_IRAM",
+                                "range": null,
+                                "title": "Place peripheral control functions into IRAM",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": null,
+                        "id": "component-config-hardware-settings-peripheral-control",
+                        "title": "Peripheral Control",
+                        "type": "menu"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "SOC_ETM_SUPPORTED",
+                                "help": "whether to enable the debug log message for ETM core driver.\nNote that, this option only controls the ETM related driver log, won't affect other drivers.",
+                                "id": "ETM_ENABLE_DEBUG_LOG",
+                                "name": "ETM_ENABLE_DEBUG_LOG",
+                                "range": null,
+                                "title": "Enable debug log",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": "SOC_ETM_SUPPORTED",
+                        "id": "component-config-hardware-settings-etm-configuration",
+                        "title": "ETM Configuration",
+                        "type": "menu"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "SOC_GDMA_SUPPORTED",
+                                "help": "Place GDMA control functions (like start/stop/append/reset) into IRAM,\nso that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context.",
+                                "id": "GDMA_CTRL_FUNC_IN_IRAM",
+                                "name": "GDMA_CTRL_FUNC_IN_IRAM",
+                                "range": null,
+                                "title": "Place GDMA control functions in IRAM",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "SOC_GDMA_SUPPORTED",
+                                "help": "This will ensure the GDMA interrupt handler is IRAM-Safe, allow to avoid flash\ncache misses, and also be able to run whilst the cache is disabled.\n(e.g. SPI Flash write).",
+                                "id": "GDMA_ISR_IRAM_SAFE",
+                                "name": "GDMA_ISR_IRAM_SAFE",
+                                "range": null,
+                                "title": "GDMA ISR IRAM-Safe",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "SOC_GDMA_SUPPORTED",
+                                "help": "Whether to enable the debug log message for GDMA driver.\nNote that, this option only controls the GDMA driver log, won't affect other drivers.",
+                                "id": "GDMA_ENABLE_DEBUG_LOG",
+                                "name": "GDMA_ENABLE_DEBUG_LOG",
+                                "range": null,
+                                "title": "Enable debug log",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": "SOC_GDMA_SUPPORTED",
+                        "id": "component-config-hardware-settings-gdma-configurations",
+                        "title": "GDMA Configurations",
+                        "type": "menu"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "SOC_DW_GDMA_SUPPORTED",
+                                "help": "Place DW_GDMA control functions (e.g. dw_gdma_channel_continue) into IRAM,\nso that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context.",
+                                "id": "DW_GDMA_CTRL_FUNC_IN_IRAM",
+                                "name": "DW_GDMA_CTRL_FUNC_IN_IRAM",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "SOC_DW_GDMA_SUPPORTED",
+                                "help": "Place DW_GDMA setter functions (e.g. dw_gdma_channel_set_block_markers) into IRAM,\nso that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context.",
+                                "id": "DW_GDMA_SETTER_FUNC_IN_IRAM",
+                                "name": "DW_GDMA_SETTER_FUNC_IN_IRAM",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "SOC_DW_GDMA_SUPPORTED",
+                                "help": "Place DW_GDMA getter functions (e.g. dw_gdma_link_list_get_item) into IRAM,\nso that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context.",
+                                "id": "DW_GDMA_GETTER_FUNC_IN_IRAM",
+                                "name": "DW_GDMA_GETTER_FUNC_IN_IRAM",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "SOC_DW_GDMA_SUPPORTED",
+                                "help": "This will ensure the DW_GDMA interrupt handler is IRAM-Safe, allow to avoid flash\ncache misses, and also be able to run whilst the cache is disabled.\n(e.g. SPI Flash write).",
+                                "id": "DW_GDMA_ISR_IRAM_SAFE",
+                                "name": "DW_GDMA_ISR_IRAM_SAFE",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "SOC_DW_GDMA_SUPPORTED",
+                                "help": "This will ensure the DW_GDMA object is DRAM-Safe, allow to avoid external memory\ncache misses, and also be accessible whilst the cache is disabled.",
+                                "id": "DW_GDMA_OBJ_DRAM_SAFE",
+                                "name": "DW_GDMA_OBJ_DRAM_SAFE",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "SOC_DW_GDMA_SUPPORTED",
+                                "help": "Whether to enable the debug log message for DW_GDMA driver.\nNote that, this option only controls the DW_GDMA driver log, won't affect other drivers.",
+                                "id": "DW_GDMA_ENABLE_DEBUG_LOG",
+                                "name": "DW_GDMA_ENABLE_DEBUG_LOG",
+                                "range": null,
+                                "title": "Enable debug log",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": "SOC_DW_GDMA_SUPPORTED",
+                        "id": "component-config-hardware-settings-dw_gdma-configurations",
+                        "title": "DW_GDMA Configurations",
+                        "type": "menu"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "SOC_DMA2D_SUPPORTED",
+                                "help": "Place 2D-DMA all operation functions, including control functions (e.g. start/stop/append/reset) and setter\nfunctions (e.g. connect/strategy/callback registration) into IRAM, so that these functions can be IRAM-safe\nand able to be called in the other IRAM interrupt context. It also helps optimizing the performance.",
+                                "id": "DMA2D_OPERATION_FUNC_IN_IRAM",
+                                "name": "DMA2D_OPERATION_FUNC_IN_IRAM",
+                                "range": null,
+                                "title": "Place 2D-DMA operation functions into IRAM",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "SOC_DMA2D_SUPPORTED",
+                                "help": "This will ensure the 2D-DMA interrupt handler is IRAM-Safe, allow to avoid flash\ncache misses, and also be able to run whilst the cache is disabled.\n(e.g. SPI Flash write).",
+                                "id": "DMA2D_ISR_IRAM_SAFE",
+                                "name": "DMA2D_ISR_IRAM_SAFE",
+                                "range": null,
+                                "title": "2D-DMA ISR IRAM-Safe",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": "SOC_DMA2D_SUPPORTED",
+                        "id": "component-config-hardware-settings-2d-dma-configurations",
+                        "title": "2D-DMA Configurations",
+                        "type": "menu"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice XTAL_FREQ>",
+                                        "help": null,
+                                        "id": "XTAL_FREQ_40",
+                                        "name": "XTAL_FREQ_40",
+                                        "range": null,
+                                        "title": "40 MHz",
+                                        "type": "bool"
+                                    }
+                                ],
+                                "depends_on": null,
+                                "help": "This option selects the operating frequency of the XTAL (crystal) clock used to drive the ESP target.\nThe selected value MUST reflect the frequency of the given hardware.",
+                                "id": "component-config-hardware-settings-main-xtal-config-main-xtal-frequency",
+                                "name": "XTAL_FREQ",
+                                "title": "Main XTAL frequency",
+                                "type": "choice"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "XTAL_FREQ",
+                                "name": "XTAL_FREQ",
+                                "range": null,
+                                "title": null,
+                                "type": "int"
+                            }
+                        ],
+                        "depends_on": null,
+                        "id": "component-config-hardware-settings-main-xtal-config",
+                        "title": "Main XTAL Config",
+                        "type": "menu"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": "This option is only used for new chip bringup, when\nclock support isn't done yet. So with this option,\nwe use xtal on FPGA as the clock source.",
+                        "id": "ESP_BRINGUP_BYPASS_CPU_CLK_SETTING",
+                        "name": "ESP_BRINGUP_BYPASS_CPU_CLK_SETTING",
+                        "range": null,
+                        "title": null,
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": "This option is only used for new chip bringup, when\nRNG isn't done yet. So with this option, we use 0x5A\nto fill the random buffers",
+                        "id": "ESP_BRINGUP_BYPASS_RANDOM_SETTING",
+                        "name": "ESP_BRINGUP_BYPASS_RANDOM_SETTING",
+                        "range": null,
+                        "title": null,
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": null,
+                        "id": "ESP_SPI_BUS_LOCK_ISR_FUNCS_IN_IRAM",
+                        "name": "ESP_SPI_BUS_LOCK_ISR_FUNCS_IN_IRAM",
+                        "range": null,
+                        "title": null,
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": null,
+                        "id": "ESP_SPI_BUS_LOCK_FUNCS_IN_IRAM",
+                        "name": "ESP_SPI_BUS_LOCK_FUNCS_IN_IRAM",
+                        "range": null,
+                        "title": null,
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": "Due to the poor low-temperature characteristics of\nRC32K (it cannot operate below -40 degrees Celsius),\nplease avoid using it whenever possible",
+                        "id": "ESP_CLK_RC32K_NOT_TO_USE",
+                        "name": "ESP_CLK_RC32K_NOT_TO_USE",
+                        "range": null,
+                        "title": null,
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": null,
+                "id": "component-config-hardware-settings",
+                "title": "Hardware Settings",
+                "type": "menu"
+            },
+            {
+                "children": [
+                    {
+                        "children": [
+                            {
+                                "children": [
+                                    {
+                                        "children": [
+                                            {
+                                                "children": [],
+                                                "depends_on": "<choice ESP_CRYPTO_DPA_PROTECTION_LEVEL>",
+                                                "help": null,
+                                                "id": "ESP_CRYPTO_DPA_PROTECTION_LEVEL_LOW",
+                                                "name": "ESP_CRYPTO_DPA_PROTECTION_LEVEL_LOW",
+                                                "range": null,
+                                                "title": "Security level low",
+                                                "type": "bool"
+                                            },
+                                            {
+                                                "children": [],
+                                                "depends_on": "<choice ESP_CRYPTO_DPA_PROTECTION_LEVEL>",
+                                                "help": null,
+                                                "id": "ESP_CRYPTO_DPA_PROTECTION_LEVEL_MEDIUM",
+                                                "name": "ESP_CRYPTO_DPA_PROTECTION_LEVEL_MEDIUM",
+                                                "range": null,
+                                                "title": "Security level medium",
+                                                "type": "bool"
+                                            },
+                                            {
+                                                "children": [],
+                                                "depends_on": "<choice ESP_CRYPTO_DPA_PROTECTION_LEVEL>",
+                                                "help": null,
+                                                "id": "ESP_CRYPTO_DPA_PROTECTION_LEVEL_HIGH",
+                                                "name": "ESP_CRYPTO_DPA_PROTECTION_LEVEL_HIGH",
+                                                "range": null,
+                                                "title": "Security level high",
+                                                "type": "bool"
+                                            }
+                                        ],
+                                        "depends_on": "ESP_CRYPTO_DPA_PROTECTION_AT_STARTUP && SOC_CRYPTO_DPA_PROTECTION_SUPPORTED",
+                                        "help": "Configure the DPA protection security level",
+                                        "id": "component-config-esp-security-specific-crypto-dpa-protection-enable-crypto-dpa-protection-at-startup-dpa-protection-level",
+                                        "name": "ESP_CRYPTO_DPA_PROTECTION_LEVEL",
+                                        "title": "DPA protection level",
+                                        "type": "choice"
+                                    }
+                                ],
+                                "depends_on": "SOC_CRYPTO_DPA_PROTECTION_SUPPORTED",
+                                "help": "This config controls the DPA (Differential Power Analysis) protection\nknob for the crypto peripherals. DPA protection dynamically adjusts\nclock frequency of the crypto peripheral. DPA protection helps to make it\ndifficult to perform SCA attacks on the crypto peripherals. However,\nthere is also associated performance impact based on the security level\nset. Please refer to the TRM for more details.",
+                                "id": "ESP_CRYPTO_DPA_PROTECTION_AT_STARTUP",
+                                "name": "ESP_CRYPTO_DPA_PROTECTION_AT_STARTUP",
+                                "range": null,
+                                "title": "Enable crypto DPA protection at startup",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "SOC_CRYPTO_DPA_PROTECTION_SUPPORTED",
+                                "help": null,
+                                "id": "ESP_CRYPTO_DPA_PROTECTION_LEVEL",
+                                "name": "ESP_CRYPTO_DPA_PROTECTION_LEVEL",
+                                "range": null,
+                                "title": null,
+                                "type": "int"
+                            }
+                        ],
+                        "depends_on": "SOC_CRYPTO_DPA_PROTECTION_SUPPORTED",
+                        "id": "component-config-esp-security-specific-crypto-dpa-protection",
+                        "title": "Crypto DPA Protection",
+                        "type": "menu"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "SOC_ECC_CONSTANT_TIME_POINT_MUL",
+                        "help": "If enabled, the app startup code will burn the ECC_FORCE_CONST_TIME efuse bit to force the\nECC peripheral to always perform constant time point multiplication operations,\nirrespective of the ECC_MULT_SECURITY_MODE status bit that is present in the ECC_MULT_CONF_REG\nregister. By default, ESP-IDF configures the ECC peripheral to perform constant time point\nmultiplication operations, so enabling this config would provide security enhancement only in\nthe cases when trusted boot is not enabled and the attacker tries carrying out non-constant\ntime point multiplication operations by changing the default ESP-IDF configurations.\nPerforming constant time operations protect the ECC multiplication operations from timing attacks.",
+                        "id": "ESP_CRYPTO_FORCE_ECC_CONSTANT_TIME_POINT_MUL",
+                        "name": "ESP_CRYPTO_FORCE_ECC_CONSTANT_TIME_POINT_MUL",
+                        "range": null,
+                        "title": "Forcefully enable ECC constant time point multiplication operations",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": null,
+                "id": "component-config-esp-security-specific",
+                "title": "ESP Security Specific",
+                "type": "menu"
+            },
+            {
+                "children": [
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "IDF_ENV_FPGA && <choice ESP_DEFAULT_CPU_FREQ_MHZ>",
+                                "help": null,
+                                "id": "ESP_DEFAULT_CPU_FREQ_MHZ_40",
+                                "name": "ESP_DEFAULT_CPU_FREQ_MHZ_40",
+                                "range": null,
+                                "title": "40 MHz",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice ESP_DEFAULT_CPU_FREQ_MHZ>",
+                                "help": null,
+                                "id": "ESP_DEFAULT_CPU_FREQ_MHZ_80",
+                                "name": "ESP_DEFAULT_CPU_FREQ_MHZ_80",
+                                "range": null,
+                                "title": "80 MHz",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice ESP_DEFAULT_CPU_FREQ_MHZ>",
+                                "help": null,
+                                "id": "ESP_DEFAULT_CPU_FREQ_MHZ_160",
+                                "name": "ESP_DEFAULT_CPU_FREQ_MHZ_160",
+                                "range": null,
+                                "title": "160 MHz",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": null,
+                        "help": "CPU frequency to be set on application startup.",
+                        "id": "component-config-esp-system-settings-cpu-frequency",
+                        "name": "ESP_DEFAULT_CPU_FREQ_MHZ",
+                        "title": "CPU frequency",
+                        "type": "choice"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": null,
+                        "id": "ESP_DEFAULT_CPU_FREQ_MHZ",
+                        "name": "ESP_DEFAULT_CPU_FREQ_MHZ",
+                        "range": null,
+                        "title": null,
+                        "type": "int"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "!ESP_SYSTEM_GDBSTUB_RUNTIME && <choice ESP_SYSTEM_PANIC>",
+                                "help": "Outputs the relevant registers over the serial port and halt the\nprocessor. Needs a manual reset to restart.",
+                                "id": "ESP_SYSTEM_PANIC_PRINT_HALT",
+                                "name": "ESP_SYSTEM_PANIC_PRINT_HALT",
+                                "range": null,
+                                "title": "Print registers and halt",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "!ESP_SYSTEM_GDBSTUB_RUNTIME && <choice ESP_SYSTEM_PANIC>",
+                                "help": "Outputs the relevant registers over the serial port and immediately\nreset the processor.",
+                                "id": "ESP_SYSTEM_PANIC_PRINT_REBOOT",
+                                "name": "ESP_SYSTEM_PANIC_PRINT_REBOOT",
+                                "range": null,
+                                "title": "Print registers and reboot",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "!ESP_SYSTEM_GDBSTUB_RUNTIME && <choice ESP_SYSTEM_PANIC>",
+                                "help": "Just resets the processor without outputting anything",
+                                "id": "ESP_SYSTEM_PANIC_SILENT_REBOOT",
+                                "name": "ESP_SYSTEM_PANIC_SILENT_REBOOT",
+                                "range": null,
+                                "title": "Silent reboot",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "ESP_GDBSTUB_ENABLED && <choice ESP_SYSTEM_PANIC>",
+                                "help": "Invoke gdbstub on the serial port, allowing for gdb to attach to it to do a postmortem\nof the crash.",
+                                "id": "ESP_SYSTEM_PANIC_GDBSTUB",
+                                "name": "ESP_SYSTEM_PANIC_GDBSTUB",
+                                "range": null,
+                                "title": "GDBStub on panic",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": null,
+                        "help": "If FreeRTOS detects unexpected behaviour or an unhandled exception, the panic handler is\ninvoked. Configure the panic handler's action here.",
+                        "id": "component-config-esp-system-settings-panic-handler-behaviour",
+                        "name": "ESP_SYSTEM_PANIC",
+                        "title": "Panic handler behaviour",
+                        "type": "choice"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "ESP_SYSTEM_PANIC_PRINT_REBOOT",
+                        "help": "After the panic handler executes, you can specify a number of seconds to\nwait before the device reboots.",
+                        "id": "ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS",
+                        "name": "ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS",
+                        "range": [
+                            0,
+                            99
+                        ],
+                        "title": "Panic reboot delay (Seconds)",
+                        "type": "int"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": "Only initialize and use the main core.",
+                        "id": "ESP_SYSTEM_SINGLE_CORE_MODE",
+                        "name": "ESP_SYSTEM_SINGLE_CORE_MODE",
+                        "range": null,
+                        "title": null,
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": null,
+                        "id": "ESP_SYSTEM_RTC_EXT_XTAL",
+                        "name": "ESP_SYSTEM_RTC_EXT_XTAL",
+                        "range": null,
+                        "title": null,
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": null,
+                        "id": "ESP_SYSTEM_RTC_EXT_OSC",
+                        "name": "ESP_SYSTEM_RTC_EXT_OSC",
+                        "range": null,
+                        "title": null,
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "ESP_SYSTEM_RTC_EXT_XTAL",
+                        "help": "To reduce the startup time of an external RTC crystal,\nwe bootstrap it with a 32kHz square wave for a fixed number of cycles.\nSetting 0 will disable bootstrapping (if disabled, the crystal may take\nlonger to start up or fail to oscillate under some conditions).\n\nIf this value is too high, a faulty crystal may initially start and then fail.\nIf this value is too low, an otherwise good crystal may not start.\n\nTo accurately determine if the crystal has started,\nset a larger \"Number of cycles for RTC_SLOW_CLK calibration\" (about 3000).",
+                        "id": "ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES",
+                        "name": "ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES",
+                        "range": null,
+                        "title": "Bootstrap cycles for external 32kHz crystal",
+                        "type": "int"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "SOC_RTC_FAST_MEM_SUPPORTED",
+                        "help": null,
+                        "id": "ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK",
+                        "name": "ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK",
+                        "range": null,
+                        "title": null,
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK",
+                        "help": "This config option allows to add RTC fast memory region to system heap with capability\nsimilar to that of DRAM region but without DMA. Speed wise RTC fast memory operates on\nAPB clock and hence does not have much performance impact.",
+                        "id": "ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP",
+                        "name": "ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP",
+                        "range": null,
+                        "title": "Enable RTC fast memory for dynamic allocations",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "IDF_TARGET_ARCH_RISCV",
+                        "help": "Generate DWARF information for each function of the project. These information will parsed and used to\nperform backtracing when panics occur. Activating this option will activate asynchronous frame unwinding\nand generation of both .eh_frame and .eh_frame_hdr sections, resulting in a bigger binary size (20% to\n100% larger). The main purpose of this option is to be able to have a backtrace parsed and printed by\nthe program itself, regardless of the serial monitor used.\nThis option shall NOT be used for production.",
+                        "id": "ESP_SYSTEM_USE_EH_FRAME",
+                        "name": "ESP_SYSTEM_USE_EH_FRAME",
+                        "range": null,
+                        "title": "Generate and use eh_frame for backtracing",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [
+                                    {
+                                        "children": [],
+                                        "depends_on": "IDF_TARGET_ARCH_RISCV && SOC_LP_CORE_SUPPORTED && ESP_SYSTEM_PMP_IDRAM_SPLIT",
+                                        "help": "If enabled, user can run code available in LP Core image.\n\nWarning: on ESP32-P4 this will also mark the memory area used for BOOTLOADER_RESERVE_RTC_MEM\nas executable. If you consider this a security risk then do not activate this option.",
+                                        "id": "ESP_SYSTEM_PMP_LP_CORE_RESERVE_MEM_EXECUTABLE",
+                                        "name": "ESP_SYSTEM_PMP_LP_CORE_RESERVE_MEM_EXECUTABLE",
+                                        "range": null,
+                                        "title": "Make LP core reserved memory executable from HP core",
+                                        "type": "bool"
+                                    }
+                                ],
+                                "depends_on": "SOC_CPU_IDRAM_SPLIT_USING_PMP",
+                                "help": "If enabled, the CPU watches all the memory access and raises an exception in case\nof any memory violation. This feature automatically splits\nthe SRAM memory, using PMP, into data and instruction segments and sets Read/Execute permissions\nfor the instruction part (below given splitting address) and Read/Write permissions\nfor the data part (above the splitting address). The memory protection is effective\non all access through the IRAM0 and DRAM0 buses.",
+                                "id": "ESP_SYSTEM_PMP_IDRAM_SPLIT",
+                                "name": "ESP_SYSTEM_PMP_IDRAM_SPLIT",
+                                "range": null,
+                                "title": "Enable IRAM/DRAM split protection",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [
+                                    {
+                                        "children": [],
+                                        "depends_on": "ESP_SYSTEM_MEMPROT_FEATURE",
+                                        "help": "Once locked, memory protection settings cannot be changed anymore.\nThe lock is reset only on the chip startup.",
+                                        "id": "ESP_SYSTEM_MEMPROT_FEATURE_LOCK",
+                                        "name": "ESP_SYSTEM_MEMPROT_FEATURE_LOCK",
+                                        "range": null,
+                                        "title": "Lock memory protection settings",
+                                        "type": "bool"
+                                    }
+                                ],
+                                "depends_on": "SOC_MEMPROT_SUPPORTED",
+                                "help": "If enabled, the permission control module watches all the memory access and fires the panic handler\nif a permission violation is detected. This feature automatically splits\nthe SRAM memory into data and instruction segments and sets Read/Execute permissions\nfor the instruction part (below given splitting address) and Read/Write permissions\nfor the data part (above the splitting address). The memory protection is effective\non all access through the IRAM0 and DRAM0 buses.",
+                                "id": "ESP_SYSTEM_MEMPROT_FEATURE",
+                                "name": "ESP_SYSTEM_MEMPROT_FEATURE",
+                                "range": null,
+                                "title": "Enable memory protection",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": null,
+                        "id": "component-config-esp-system-settings-memory-protection",
+                        "title": "Memory protection",
+                        "type": "menu"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": "Config system event queue size in different application.",
+                        "id": "ESP_SYSTEM_EVENT_QUEUE_SIZE",
+                        "name": "ESP_SYSTEM_EVENT_QUEUE_SIZE",
+                        "range": null,
+                        "title": "System event queue size",
+                        "type": "int"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": "Config system event task stack size in different application.",
+                        "id": "ESP_SYSTEM_EVENT_TASK_STACK_SIZE",
+                        "name": "ESP_SYSTEM_EVENT_TASK_STACK_SIZE",
+                        "range": null,
+                        "title": "Event loop task stack size",
+                        "type": "int"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": "Configure the \"main task\" stack size. This is the stack of the task\nwhich calls app_main(). If app_main() returns then this task is deleted\nand its stack memory is freed.",
+                        "id": "ESP_MAIN_TASK_STACK_SIZE",
+                        "name": "ESP_MAIN_TASK_STACK_SIZE",
+                        "range": null,
+                        "title": "Main task stack size",
+                        "type": "int"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "<choice ESP_MAIN_TASK_AFFINITY>",
+                                "help": null,
+                                "id": "ESP_MAIN_TASK_AFFINITY_CPU0",
+                                "name": "ESP_MAIN_TASK_AFFINITY_CPU0",
+                                "range": null,
+                                "title": "CPU0",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "!FREERTOS_UNICORE && <choice ESP_MAIN_TASK_AFFINITY>",
+                                "help": null,
+                                "id": "ESP_MAIN_TASK_AFFINITY_CPU1",
+                                "name": "ESP_MAIN_TASK_AFFINITY_CPU1",
+                                "range": null,
+                                "title": "CPU1",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice ESP_MAIN_TASK_AFFINITY>",
+                                "help": null,
+                                "id": "ESP_MAIN_TASK_AFFINITY_NO_AFFINITY",
+                                "name": "ESP_MAIN_TASK_AFFINITY_NO_AFFINITY",
+                                "range": null,
+                                "title": "No affinity",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": null,
+                        "help": "Configure the \"main task\" core affinity. This is the used core of the task\nwhich calls app_main(). If app_main() returns then this task is deleted.",
+                        "id": "component-config-esp-system-settings-main-task-core-affinity",
+                        "name": "ESP_MAIN_TASK_AFFINITY",
+                        "title": "Main task core affinity",
+                        "type": "choice"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": null,
+                        "id": "ESP_MAIN_TASK_AFFINITY",
+                        "name": "ESP_MAIN_TASK_AFFINITY",
+                        "range": null,
+                        "title": null,
+                        "type": "hex"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": "Minimal value of size, in bytes, accepted to execute a expression\nwith shared stack.",
+                        "id": "ESP_MINIMAL_SHARED_STACK_SIZE",
+                        "name": "ESP_MINIMAL_SHARED_STACK_SIZE",
+                        "range": null,
+                        "title": "Minimal allowed size for shared stack",
+                        "type": "int"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "<choice ESP_CONSOLE_UART>",
+                                "help": null,
+                                "id": "ESP_CONSOLE_UART_DEFAULT",
+                                "name": "ESP_CONSOLE_UART_DEFAULT",
+                                "range": null,
+                                "title": "Default: UART0",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "(IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3) && !TINY_USB && <choice ESP_CONSOLE_UART>",
+                                "help": null,
+                                "id": "ESP_CONSOLE_USB_CDC",
+                                "name": "ESP_CONSOLE_USB_CDC",
+                                "range": null,
+                                "title": "USB CDC",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "SOC_USB_SERIAL_JTAG_SUPPORTED && <choice ESP_CONSOLE_UART>",
+                                "help": null,
+                                "id": "ESP_CONSOLE_USB_SERIAL_JTAG",
+                                "name": "ESP_CONSOLE_USB_SERIAL_JTAG",
+                                "range": null,
+                                "title": "USB Serial/JTAG Controller",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice ESP_CONSOLE_UART>",
+                                "help": null,
+                                "id": "ESP_CONSOLE_UART_CUSTOM",
+                                "name": "ESP_CONSOLE_UART_CUSTOM",
+                                "range": null,
+                                "title": "Custom UART",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice ESP_CONSOLE_UART>",
+                                "help": null,
+                                "id": "ESP_CONSOLE_NONE",
+                                "name": "ESP_CONSOLE_NONE",
+                                "range": null,
+                                "title": "None",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": null,
+                        "help": "Select where to send console output (through stdout and stderr).\n\n- Default is to use UART0 on pre-defined GPIOs.\n- If \"Custom\" is selected, UART0 or UART1 can be chosen,\n  and any pins can be selected.\n- If \"None\" is selected, there will be no console output on any UART, except\n  for initial output from ROM bootloader. This ROM output can be suppressed by\n  GPIO strapping or EFUSE, refer to chip datasheet for details.\n- On chips with USB OTG peripheral, \"USB CDC\" option redirects output to the\n  CDC port. This option uses the CDC driver in the chip ROM.\n  This option is incompatible with TinyUSB stack.\n- On chips with an USB serial/JTAG debug controller, selecting the option\n  for that redirects output to the CDC/ACM (serial port emulation) component\n  of that device.",
+                        "id": "component-config-esp-system-settings-channel-for-console-output",
+                        "name": "ESP_CONSOLE_UART",
+                        "title": "Channel for console output",
+                        "type": "choice"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "<choice ESP_CONSOLE_SECONDARY>",
+                                "help": null,
+                                "id": "ESP_CONSOLE_SECONDARY_NONE",
+                                "name": "ESP_CONSOLE_SECONDARY_NONE",
+                                "range": null,
+                                "title": "No secondary console",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "!ESP_CONSOLE_USB_SERIAL_JTAG && <choice ESP_CONSOLE_SECONDARY>",
+                                "help": "This option supports output through USB_SERIAL_JTAG port when the UART0 port is not connected.\nThe output currently only supports non-blocking mode without using the console.\nIf you want to output in blocking mode with REPL or input through USB_SERIAL_JTAG port,\nplease change the primary config to ESP_CONSOLE_USB_SERIAL_JTAG above.",
+                                "id": "ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG",
+                                "name": "ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG",
+                                "range": null,
+                                "title": "USB_SERIAL_JTAG PORT",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": "SOC_USB_SERIAL_JTAG_SUPPORTED",
+                        "help": "This secondary option supports output through other specific port like USB_SERIAL_JTAG\nwhen UART0 port as a primary is selected but not connected. This secondary output currently only supports\nnon-blocking mode without using REPL. If you want to output in blocking mode with REPL or\ninput through this secondary port, please change the primary config to this port\nin `Channel for console output` menu.",
+                        "id": "component-config-esp-system-settings-channel-for-console-secondary-output",
+                        "name": "ESP_CONSOLE_SECONDARY",
+                        "title": "Channel for console secondary output",
+                        "type": "choice"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": null,
+                        "id": "ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED",
+                        "name": "ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED",
+                        "range": null,
+                        "title": null,
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": null,
+                        "id": "ESP_CONSOLE_UART",
+                        "name": "ESP_CONSOLE_UART",
+                        "range": null,
+                        "title": null,
+                        "type": "bool"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "<choice ESP_CONSOLE_UART_NUM>",
+                                "help": null,
+                                "id": "ESP_CONSOLE_UART_CUSTOM_NUM_0",
+                                "name": "ESP_CONSOLE_UART_CUSTOM_NUM_0",
+                                "range": null,
+                                "title": "UART0",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice ESP_CONSOLE_UART_NUM>",
+                                "help": null,
+                                "id": "ESP_CONSOLE_UART_CUSTOM_NUM_1",
+                                "name": "ESP_CONSOLE_UART_CUSTOM_NUM_1",
+                                "range": null,
+                                "title": "UART1",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": "ESP_CONSOLE_UART_CUSTOM",
+                        "help": "This UART peripheral is used for console output from the ESP-IDF Bootloader and the app.\n\nIf the configuration is different in the Bootloader binary compared to the app binary, UART\nis reconfigured after the bootloader exits and the app starts.\n\nDue to an ESP32 ROM bug, UART2 is not supported for console output\nvia esp_rom_printf.",
+                        "id": "component-config-esp-system-settings-uart-peripheral-to-use-for-console-output-0-1-",
+                        "name": "ESP_CONSOLE_UART_NUM",
+                        "title": "UART peripheral to use for console output (0-1)",
+                        "type": "choice"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": null,
+                        "id": "ESP_CONSOLE_UART_NUM",
+                        "name": "ESP_CONSOLE_UART_NUM",
+                        "range": null,
+                        "title": null,
+                        "type": "int"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": null,
+                        "id": "ESP_CONSOLE_ROM_SERIAL_PORT_NUM",
+                        "name": "ESP_CONSOLE_ROM_SERIAL_PORT_NUM",
+                        "range": null,
+                        "title": null,
+                        "type": "int"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "ESP_CONSOLE_UART_CUSTOM",
+                        "help": "This GPIO is used for console UART TX output in the ESP-IDF Bootloader and the app (including\nboot log output and default standard output and standard error of the app). Value -1 means to\ncontinue using the default console UART TX pin.\n\nIf the configuration is different in the Bootloader binary compared to the app binary, UART\nis reconfigured after the bootloader exits and the app starts.",
+                        "id": "ESP_CONSOLE_UART_TX_GPIO",
+                        "name": "ESP_CONSOLE_UART_TX_GPIO",
+                        "range": null,
+                        "title": "UART TX on GPIO<num>",
+                        "type": "int"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "ESP_CONSOLE_UART_CUSTOM",
+                        "help": "This GPIO is used for console UART RX input in the ESP-IDF Bootloader and the app (including\ndefault standard input of the app). Value -1 means to continue using the default console UART\nRX pin.\n\nNote: The default ESP-IDF Bootloader configures this pin but doesn't read anything from the UART.\n\nIf the configuration is different in the Bootloader binary compared to the app binary, UART\nis reconfigured after the bootloader exits and the app starts.",
+                        "id": "ESP_CONSOLE_UART_RX_GPIO",
+                        "name": "ESP_CONSOLE_UART_RX_GPIO",
+                        "range": null,
+                        "title": "UART RX on GPIO<num>",
+                        "type": "int"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "ESP_CONSOLE_UART",
+                        "help": "This baud rate is used by both the ESP-IDF Bootloader and the app (including\nboot log output and default standard input/output/error of the app).\n\nThe app's maximum baud rate depends on the UART clock source. If Power Management is disabled,\nthe UART clock source is the APB clock and all baud rates in the available range will be sufficiently\naccurate. If Power Management is enabled, REF_TICK clock source is used so the baud rate is divided\nfrom 1MHz. Baud rates above 1Mbps are not possible and values between 500Kbps and 1Mbps may not be\naccurate.\n\nIf the configuration is different in the Bootloader binary compared to the app binary, UART\nis reconfigured after the bootloader exits and the app starts.",
+                        "id": "ESP_CONSOLE_UART_BAUDRATE",
+                        "name": "ESP_CONSOLE_UART_BAUDRATE",
+                        "range": [
+                            1200,
+                            4000000
+                        ],
+                        "title": "UART console baud rate",
+                        "type": "int"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "ESP_CONSOLE_USB_CDC",
+                        "help": "Set the size of USB CDC RX buffer. Increase the buffer size if your application\nis often receiving data over USB CDC.",
+                        "id": "ESP_CONSOLE_USB_CDC_RX_BUF_SIZE",
+                        "name": "ESP_CONSOLE_USB_CDC_RX_BUF_SIZE",
+                        "range": null,
+                        "title": "Size of USB CDC RX buffer",
+                        "type": "int"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "ESP_CONSOLE_USB_CDC",
+                        "help": "If enabled, esp_rom_printf and ESP_EARLY_LOG output will also be sent over USB CDC.\nDisabling this option saves about 1kB or RAM.",
+                        "id": "ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF",
+                        "name": "ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF",
+                        "range": null,
+                        "title": "Enable esp_rom_printf / ESP_EARLY_LOG via USB CDC",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "ESP_INT_WDT",
+                                "help": "The timeout of the watchdog, in milliseconds. Make this higher than the FreeRTOS tick rate.",
+                                "id": "ESP_INT_WDT_TIMEOUT_MS",
+                                "name": "ESP_INT_WDT_TIMEOUT_MS",
+                                "range": [
+                                    10,
+                                    10000
+                                ],
+                                "title": "Interrupt watchdog timeout (ms)",
+                                "type": "int"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "ESP_INT_WDT && !FREERTOS_UNICORE",
+                                "help": "Also detect if interrupts on CPU 1 are disabled for too long.",
+                                "id": "ESP_INT_WDT_CHECK_CPU1",
+                                "name": "ESP_INT_WDT_CHECK_CPU1",
+                                "range": null,
+                                "title": "Also watch CPU1 tick interrupt",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": null,
+                        "help": "This watchdog timer can detect if the FreeRTOS tick interrupt has not been called for a certain time,\neither because a task turned off interrupts and did not turn them on for a long time, or because an\ninterrupt handler did not return. It will try to invoke the panic handler first and failing that\nreset the SoC.",
+                        "id": "ESP_INT_WDT",
+                        "name": "ESP_INT_WDT",
+                        "range": null,
+                        "title": "Interrupt watchdog",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "ESP_TASK_WDT_EN",
+                                "help": null,
+                                "id": "ESP_TASK_WDT_USE_ESP_TIMER",
+                                "name": "ESP_TASK_WDT_USE_ESP_TIMER",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [
+                                    {
+                                        "children": [],
+                                        "depends_on": "ESP_TASK_WDT_INIT",
+                                        "help": "If this option is enabled, the Task Watchdog Timer will be configured to\ntrigger the panic handler when it times out. This can also be configured\nat run time (see Task Watchdog Timer API Reference)",
+                                        "id": "ESP_TASK_WDT_PANIC",
+                                        "name": "ESP_TASK_WDT_PANIC",
+                                        "range": null,
+                                        "title": "Invoke panic handler on Task Watchdog timeout",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "ESP_TASK_WDT_INIT",
+                                        "help": "Timeout period configuration for the Task Watchdog Timer in seconds.\nThis is also configurable at run time (see Task Watchdog Timer API Reference)",
+                                        "id": "ESP_TASK_WDT_TIMEOUT_S",
+                                        "name": "ESP_TASK_WDT_TIMEOUT_S",
+                                        "range": [
+                                            1,
+                                            60
+                                        ],
+                                        "title": "Task Watchdog timeout period (seconds)",
+                                        "type": "int"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "ESP_TASK_WDT_INIT",
+                                        "help": "If this option is enabled, the Task Watchdog Timer will watch the CPU0\nIdle Task. Having the Task Watchdog watch the Idle Task allows for detection\nof CPU starvation as the Idle Task not being called is usually a symptom of\nCPU starvation. Starvation of the Idle Task is detrimental as FreeRTOS household\ntasks depend on the Idle Task getting some runtime every now and then.",
+                                        "id": "ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0",
+                                        "name": "ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0",
+                                        "range": null,
+                                        "title": "Watch CPU0 Idle Task",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "ESP_TASK_WDT_INIT && !FREERTOS_UNICORE",
+                                        "help": "If this option is enabled, the Task Watchdog Timer will wach the CPU1\nIdle Task.",
+                                        "id": "ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1",
+                                        "name": "ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1",
+                                        "range": null,
+                                        "title": "Watch CPU1 Idle Task",
+                                        "type": "bool"
+                                    }
+                                ],
+                                "depends_on": "ESP_TASK_WDT_EN",
+                                "help": "Enabling this option will cause the Task Watchdog Timer to be initialized\nautomatically at startup.",
+                                "id": "ESP_TASK_WDT_INIT",
+                                "name": "ESP_TASK_WDT_INIT",
+                                "range": null,
+                                "title": "Initialize Task Watchdog Timer on startup",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": null,
+                        "help": "The Task Watchdog Timer can be used to make sure individual tasks are still\nrunning. Enabling this option will enable the Task Watchdog Timer. It can be\neither initialized automatically at startup or initialized after startup\n(see Task Watchdog Timer API Reference)",
+                        "id": "ESP_TASK_WDT_EN",
+                        "name": "ESP_TASK_WDT_EN",
+                        "range": null,
+                        "title": "Enable Task Watchdog Timer",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "ESP_XT_WDT",
+                                "help": "Timeout period configuration for the XTAL32K watchdog timer based on RTC_CLK.",
+                                "id": "ESP_XT_WDT_TIMEOUT",
+                                "name": "ESP_XT_WDT_TIMEOUT",
+                                "range": null,
+                                "title": "XTAL32K watchdog timeout period",
+                                "type": "int"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "ESP_XT_WDT",
+                                "help": "Enable this to automatically switch to BACKUP32K_CLK as the source of RTC_SLOW_CLK when\nthe watchdog timer expires.",
+                                "id": "ESP_XT_WDT_BACKUP_CLK_ENABLE",
+                                "name": "ESP_XT_WDT_BACKUP_CLK_ENABLE",
+                                "range": null,
+                                "title": "Automatically switch to BACKUP32K_CLK when timer expires",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": "SOC_XT_WDT_SUPPORTED && (ESP_SYSTEM_RTC_EXT_OSC || ESP_SYSTEM_RTC_EXT_XTAL)",
+                        "help": "This watchdog timer can detect oscillation failure of the XTAL32K_CLK. When such a failure\nis detected the hardware can be set up to automatically switch to BACKUP32K_CLK and generate\nan interrupt.",
+                        "id": "ESP_XT_WDT",
+                        "name": "ESP_XT_WDT",
+                        "range": null,
+                        "title": "Initialize XTAL32K watchdog timer on startup",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": "If this option is disabled (default), the panic handler code is placed in flash not IRAM.\nThis means that if ESP-IDF crashes while flash cache is disabled, the panic handler will\nautomatically re-enable flash cache before running GDB Stub or Core Dump. This adds some minor\nrisk, if the flash cache status is also corrupted during the crash.\n\nIf this option is enabled, the panic handler code (including required UART functions) is placed\nin IRAM. This may be necessary to debug some complex issues with crashes while flash cache is\ndisabled (for example, when writing to SPI flash) or when flash cache is corrupted when an exception\nis triggered.",
+                        "id": "ESP_PANIC_HANDLER_IRAM",
+                        "name": "ESP_PANIC_HANDLER_IRAM",
+                        "range": null,
+                        "title": "Place panic handler code in IRAM",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "!ESP32_TRAX && !ESP32S2_TRAX && !ESP32S3_TRAX",
+                        "help": "Debug stubs are used by OpenOCD to execute pre-compiled onboard code\nwhich does some useful debugging stuff, e.g. GCOV data dump.",
+                        "id": "ESP_DEBUG_STUBS_ENABLE",
+                        "name": "ESP_DEBUG_STUBS_ENABLE",
+                        "range": null,
+                        "title": "OpenOCD debug stubs",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "SOC_DEBUG_HAVE_OCD_STUB_BINS",
+                        "help": "OpenOCD uses stub code to access flash during programming or when inserting and removing\nSW flash breakpoints.\nTo execute stub code, OpenOCD allocates memory on the target device, backs up the existing memory,\nloads the stub binary, runs the binary, and then restores the original memory.\nThis process can be time-consuming, especially when using USB serial JTAG.\nBy enabling this option, 8K of memory in RAM will be preallocated with the stub code,\neliminating the need to back up and restore the memory region.",
+                        "id": "ESP_DEBUG_INCLUDE_OCD_STUB_BINS",
+                        "name": "ESP_DEBUG_INCLUDE_OCD_STUB_BINS",
+                        "range": null,
+                        "title": "Preload OpenOCD stub binaries to speed up debugging. 8K memory will be reserved",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": "The FreeRTOS panic and unhandled exception handers can detect a JTAG OCD debugger and\ninstead of panicking, have the debugger stop on the offending instruction.",
+                        "id": "ESP_DEBUG_OCDAWARE",
+                        "name": "ESP_DEBUG_OCDAWARE",
+                        "range": null,
+                        "title": "Make exception and panic handlers JTAG/OCD aware",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "IDF_TARGET_ESP32 && <choice ESP_SYSTEM_CHECK_INT_LEVEL>",
+                                "help": "Using level 5 interrupt for Interrupt Watchdog, IPC_ISR and other system checks.",
+                                "id": "ESP_SYSTEM_CHECK_INT_LEVEL_5",
+                                "name": "ESP_SYSTEM_CHECK_INT_LEVEL_5",
+                                "range": null,
+                                "title": "Level 5 interrupt",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "!BTDM_CTRL_HLI && <choice ESP_SYSTEM_CHECK_INT_LEVEL>",
+                                "help": "Using level 4 interrupt for Interrupt Watchdog, IPC_ISR and other system checks.",
+                                "id": "ESP_SYSTEM_CHECK_INT_LEVEL_4",
+                                "name": "ESP_SYSTEM_CHECK_INT_LEVEL_4",
+                                "range": null,
+                                "title": "Level 4 interrupt",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": null,
+                        "help": "Interrupt level to use for Interrupt Watchdog, IPC_ISR and other system checks.",
+                        "id": "component-config-esp-system-settings-interrupt-level-to-use-for-interrupt-watchdog-and-other-system-checks",
+                        "name": "ESP_SYSTEM_CHECK_INT_LEVEL",
+                        "title": "Interrupt level to use for Interrupt Watchdog and other system checks",
+                        "type": "choice"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [
+                                    {
+                                        "children": [
+                                            {
+                                                "children": [],
+                                                "depends_on": "<choice ESP_BROWNOUT_DET_LVL_SEL>",
+                                                "help": null,
+                                                "id": "ESP_BROWNOUT_DET_LVL_SEL_7",
+                                                "name": "ESP_BROWNOUT_DET_LVL_SEL_7",
+                                                "range": null,
+                                                "title": "2.51V",
+                                                "type": "bool"
+                                            },
+                                            {
+                                                "children": [],
+                                                "depends_on": "<choice ESP_BROWNOUT_DET_LVL_SEL>",
+                                                "help": null,
+                                                "id": "ESP_BROWNOUT_DET_LVL_SEL_6",
+                                                "name": "ESP_BROWNOUT_DET_LVL_SEL_6",
+                                                "range": null,
+                                                "title": "2.64V",
+                                                "type": "bool"
+                                            },
+                                            {
+                                                "children": [],
+                                                "depends_on": "<choice ESP_BROWNOUT_DET_LVL_SEL>",
+                                                "help": null,
+                                                "id": "ESP_BROWNOUT_DET_LVL_SEL_5",
+                                                "name": "ESP_BROWNOUT_DET_LVL_SEL_5",
+                                                "range": null,
+                                                "title": "2.76V",
+                                                "type": "bool"
+                                            },
+                                            {
+                                                "children": [],
+                                                "depends_on": "<choice ESP_BROWNOUT_DET_LVL_SEL>",
+                                                "help": null,
+                                                "id": "ESP_BROWNOUT_DET_LVL_SEL_4",
+                                                "name": "ESP_BROWNOUT_DET_LVL_SEL_4",
+                                                "range": null,
+                                                "title": "2.92V",
+                                                "type": "bool"
+                                            },
+                                            {
+                                                "children": [],
+                                                "depends_on": "<choice ESP_BROWNOUT_DET_LVL_SEL>",
+                                                "help": null,
+                                                "id": "ESP_BROWNOUT_DET_LVL_SEL_3",
+                                                "name": "ESP_BROWNOUT_DET_LVL_SEL_3",
+                                                "range": null,
+                                                "title": "3.10V",
+                                                "type": "bool"
+                                            },
+                                            {
+                                                "children": [],
+                                                "depends_on": "<choice ESP_BROWNOUT_DET_LVL_SEL>",
+                                                "help": null,
+                                                "id": "ESP_BROWNOUT_DET_LVL_SEL_2",
+                                                "name": "ESP_BROWNOUT_DET_LVL_SEL_2",
+                                                "range": null,
+                                                "title": "3.27V",
+                                                "type": "bool"
+                                            }
+                                        ],
+                                        "depends_on": "ESP_BROWNOUT_DET",
+                                        "help": "The brownout detector will reset the chip when the supply voltage is approximately\nbelow this level. Note that there may be some variation of brownout voltage level\nbetween each chip.\n\n#The voltage levels here are estimates, more work needs to be done to figure out the exact voltages\n#of the brownout threshold levels.",
+                                        "id": "component-config-esp-system-settings-brownout-detector-hardware-brownout-detect-reset-brownout-voltage-level",
+                                        "name": "ESP_BROWNOUT_DET_LVL_SEL",
+                                        "title": "Brownout voltage level",
+                                        "type": "choice"
+                                    }
+                                ],
+                                "depends_on": "!IDF_ENV_FPGA",
+                                "help": "The ESP32-C3 has a built-in brownout detector which can detect if the voltage is lower than\na specific value. If this happens, it will reset the chip in order to prevent unintended\nbehaviour.",
+                                "id": "ESP_BROWNOUT_DET",
+                                "name": "ESP_BROWNOUT_DET",
+                                "range": null,
+                                "title": "Hardware brownout detect & reset",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "ESP_BROWNOUT_DET_LVL",
+                                "name": "ESP_BROWNOUT_DET_LVL",
+                                "range": null,
+                                "title": null,
+                                "type": "int"
+                            }
+                        ],
+                        "depends_on": null,
+                        "id": "component-config-esp-system-settings-brownout-detector",
+                        "title": "Brownout Detector",
+                        "type": "menu"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": "This config allows to trigger an interrupt when brownout detected. Software restart will be done\nat the end of the default callback.\nTwo occasions need to restart the chip with interrupt so far.\n(1). For ESP32 version 1, brown-out reset function doesn't work (see ESP32 errata 3.4).\n      So that we must restart from interrupt.\n(2). For special workflow, the chip needs do more things instead of restarting directly. This part\n     needs to be done in callback function of interrupt.",
+                        "id": "ESP_SYSTEM_BROWNOUT_INTR",
+                        "name": "ESP_SYSTEM_BROWNOUT_INTR",
+                        "range": null,
+                        "title": null,
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "SOC_ASSIST_DEBUG_SUPPORTED",
+                        "help": "This config allows to trigger a panic interrupt when Stack Pointer register goes out of allocated stack\nmemory bounds.",
+                        "id": "ESP_SYSTEM_HW_STACK_GUARD",
+                        "name": "ESP_SYSTEM_HW_STACK_GUARD",
+                        "range": null,
+                        "title": "Hardware stack guard",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32H2",
+                        "help": "This configuration helps to address an BBPLL inaccurate issue when boot from certain bootloader version,\nwhich may increase about the boot-up time by about 200 us. Disable this when your bootloader is built with\nESP-IDF version v5.2 and above.",
+                        "id": "ESP_SYSTEM_BBPLL_RECALIB",
+                        "name": "ESP_SYSTEM_BBPLL_RECALIB",
+                        "range": null,
+                        "title": "Re-calibration BBPLL at startup",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "SOC_ASSIST_DEBUG_SUPPORTED",
+                        "help": "This option will enable the PC recording function of assist_debug module. The PC value of the CPU will be\nrecorded to PC record register in assist_debug module in real time. When an exception occurs and the CPU\nis reset, this register will be kept, then we can use the recorded PC to debug the causes of the reset.",
+                        "id": "ESP_SYSTEM_HW_PC_RECORD",
+                        "name": "ESP_SYSTEM_HW_PC_RECORD",
+                        "range": null,
+                        "title": "Hardware PC recording",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": null,
+                "id": "component-config-esp-system-settings",
+                "title": "ESP System Settings",
+                "type": "menu"
+            },
+            {
+                "children": [
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": "Configure the IPC tasks stack size. An IPC task runs on each core (in dual core mode), and allows for\ncross-core function calls. See IPC documentation for more details. The default IPC stack size should be\nenough for most common simple use cases. However, users can increase/decrease the stack size to their\nneeds.",
+                        "id": "ESP_IPC_TASK_STACK_SIZE",
+                        "name": "ESP_IPC_TASK_STACK_SIZE",
+                        "range": [
+                            512,
+                            65536
+                        ],
+                        "title": "Inter-Processor Call (IPC) task stack size",
+                        "type": "int"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "!FREERTOS_UNICORE",
+                        "help": "If this option is not enabled then the IPC task will keep behavior same as prior to that of ESP-IDF v4.0,\nhence IPC task will run at (configMAX_PRIORITIES - 1) priority.",
+                        "id": "ESP_IPC_USES_CALLERS_PRIORITY",
+                        "name": "ESP_IPC_USES_CALLERS_PRIORITY",
+                        "range": null,
+                        "title": "IPC runs at caller's priority",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": "The IPC ISR feature is similar to the IPC feature except that the callback function is executed in the\ncontext of a High Priority Interrupt. The IPC ISR feature is intended for low latency execution of simple\ncallbacks written in assembly on another CPU. Due to being run in a High Priority Interrupt, the assembly\ncallbacks must be written with particular restrictions (see \"IPC\" and \"High-Level Interrupt\" docs for more\ndetails).",
+                        "id": "ESP_IPC_ISR_ENABLE",
+                        "name": "ESP_IPC_ISR_ENABLE",
+                        "range": null,
+                        "title": null,
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": null,
+                "id": "component-config-ipc-inter-processor-call-",
+                "title": "IPC (Inter-Processor Call)",
+                "type": "menu"
+            },
+            {
+                "children": [
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "!IDF_TARGET_ESP32P4",
+                                "help": "Amazon has released an SMP version of the FreeRTOS Kernel which can be found via the following link:\nhttps://github.com/FreeRTOS/FreeRTOS-Kernel/tree/smp\n\nIDF has added an experimental port of this SMP kernel located in\ncomponents/freertos/FreeRTOS-Kernel-SMP. Enabling this option will cause IDF to use the Amazon SMP\nkernel. Note that THIS FEATURE IS UNDER ACTIVE DEVELOPMENT, users use this at their own risk.\n\nLeaving this option disabled will mean the IDF FreeRTOS kernel is used instead, which is located in:\ncomponents/freertos/FreeRTOS-Kernel. Both kernel versions are SMP capable, but differ in\ntheir implementation and features.",
+                                "id": "FREERTOS_SMP",
+                                "name": "FREERTOS_SMP",
+                                "range": null,
+                                "title": "Run the Amazon SMP FreeRTOS kernel instead (FEATURE UNDER DEVELOPMENT)",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "This version of FreeRTOS normally takes control of all cores of the CPU. Select this if you only want\nto start it on the first core. This is needed when e.g. another process needs complete control over the\nsecond core.",
+                                "id": "FREERTOS_UNICORE",
+                                "name": "FREERTOS_UNICORE",
+                                "range": null,
+                                "title": "Run FreeRTOS only on first core",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "Sets the FreeRTOS tick interrupt frequency in Hz (see configTICK_RATE_HZ documentation for more\ndetails).",
+                                "id": "FREERTOS_HZ",
+                                "name": "FREERTOS_HZ",
+                                "range": [
+                                    1,
+                                    1000
+                                ],
+                                "title": "configTICK_RATE_HZ",
+                                "type": "int"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "FREERTOS_UNICORE && !FREERTOS_SMP",
+                                "help": "Enables port specific task selection method. This option can speed up the search of ready tasks\nwhen scheduling (see configUSE_PORT_OPTIMISED_TASK_SELECTION documentation for more details).",
+                                "id": "FREERTOS_OPTIMIZED_SCHEDULER",
+                                "name": "FREERTOS_OPTIMIZED_SCHEDULER",
+                                "range": null,
+                                "title": "configUSE_PORT_OPTIMISED_TASK_SELECTION",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice FREERTOS_CHECK_STACKOVERFLOW>",
+                                        "help": "Do not check for stack overflows (configCHECK_FOR_STACK_OVERFLOW = 0)",
+                                        "id": "FREERTOS_CHECK_STACKOVERFLOW_NONE",
+                                        "name": "FREERTOS_CHECK_STACKOVERFLOW_NONE",
+                                        "range": null,
+                                        "title": "No checking",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice FREERTOS_CHECK_STACKOVERFLOW>",
+                                        "help": "Check for stack overflows on each context switch by checking if the stack pointer is in a valid\nrange. Quick but does not detect stack overflows that happened between context switches\n(configCHECK_FOR_STACK_OVERFLOW = 1)",
+                                        "id": "FREERTOS_CHECK_STACKOVERFLOW_PTRVAL",
+                                        "name": "FREERTOS_CHECK_STACKOVERFLOW_PTRVAL",
+                                        "range": null,
+                                        "title": "Check by stack pointer value (Method 1)",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice FREERTOS_CHECK_STACKOVERFLOW>",
+                                        "help": "Places some magic bytes at the end of the stack area and on each context switch, check if these\nbytes are still intact. More thorough than just checking the pointer, but also slightly slower.\n(configCHECK_FOR_STACK_OVERFLOW = 2)",
+                                        "id": "FREERTOS_CHECK_STACKOVERFLOW_CANARY",
+                                        "name": "FREERTOS_CHECK_STACKOVERFLOW_CANARY",
+                                        "range": null,
+                                        "title": "Check using canary bytes (Method 2)",
+                                        "type": "bool"
+                                    }
+                                ],
+                                "depends_on": null,
+                                "help": "Enables FreeRTOS to check for stack overflows (see configCHECK_FOR_STACK_OVERFLOW documentation for\nmore details).\n\nNote: If users do not provide their own ``vApplicationStackOverflowHook()`` function, a default\nfunction will be provided by ESP-IDF.",
+                                "id": "component-config-freertos-kernel-configcheck_for_stack_overflow",
+                                "name": "FREERTOS_CHECK_STACKOVERFLOW",
+                                "title": "configCHECK_FOR_STACK_OVERFLOW",
+                                "type": "choice"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "Set the number of thread local storage pointers in each task (see\nconfigNUM_THREAD_LOCAL_STORAGE_POINTERS documentation for more details).\n\nNote: In ESP-IDF, this value must be at least 1. Index 0 is reserved for use by the pthreads API\nthread-local-storage. Other indexes can be used for any desired purpose.",
+                                "id": "FREERTOS_THREAD_LOCAL_STORAGE_POINTERS",
+                                "name": "FREERTOS_THREAD_LOCAL_STORAGE_POINTERS",
+                                "range": [
+                                    1,
+                                    256
+                                ],
+                                "title": "configNUM_THREAD_LOCAL_STORAGE_POINTERS",
+                                "type": "int"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "Sets the idle task stack size in bytes (see configMINIMAL_STACK_SIZE documentation for more details).\n\nNote:\n\n- ESP-IDF specifies stack sizes in bytes instead of words.\n- The default size is enough for most use cases.\n- The stack size may need to be increased above the default if the app installs idle or thread local\n  storage cleanup hooks that use a lot of stack memory.\n- Conversely, the stack size can be reduced to the minimum if non of the idle features are used.",
+                                "id": "FREERTOS_IDLE_TASK_STACKSIZE",
+                                "name": "FREERTOS_IDLE_TASK_STACKSIZE",
+                                "range": [
+                                    768,
+                                    32768
+                                ],
+                                "title": "configMINIMAL_STACK_SIZE (Idle task stack size)",
+                                "type": "int"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "Enables the idle task application hook (see configUSE_IDLE_HOOK documentation for more details).\n\nNote:\n\n- The application must provide the hook function ``void vApplicationIdleHook( void );``\n- ``vApplicationIdleHook()`` is called from FreeRTOS idle task(s)\n- The FreeRTOS idle hook is NOT the same as the ESP-IDF Idle Hook, but both can be enabled\n  simultaneously.",
+                                "id": "FREERTOS_USE_IDLE_HOOK",
+                                "name": "FREERTOS_USE_IDLE_HOOK",
+                                "range": null,
+                                "title": "configUSE_IDLE_HOOK",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "FREERTOS_SMP",
+                                "help": "Enables the minimal idle task application hook (see configUSE_IDLE_HOOK documentation for more\ndetails).\n\nNote:\n\n- The application must provide the hook function ``void vApplicationPassiveIdleHook( void );``\n- ``vApplicationPassiveIdleHook()`` is called from FreeRTOS minimal idle task(s)",
+                                "id": "FREERTOS_USE_PASSIVE_IDLE_HOOK",
+                                "name": "FREERTOS_USE_PASSIVE_IDLE_HOOK",
+                                "range": null,
+                                "title": "Use FreeRTOS minimal idle hook",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "Enables the tick hook (see configUSE_TICK_HOOK documentation for more details).\n\nNote:\n\n- The application must provide the hook function ``void vApplicationTickHook( void );``\n- ``vApplicationTickHook()`` is called from FreeRTOS's tick handling function ``xTaskIncrementTick()``\n- The FreeRTOS tick hook is NOT the same as the ESP-IDF Tick Interrupt Hook, but both can be enabled\n  simultaneously.",
+                                "id": "FREERTOS_USE_TICK_HOOK",
+                                "name": "FREERTOS_USE_TICK_HOOK",
+                                "range": null,
+                                "title": "configUSE_TICK_HOOK",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "Sets the maximum number of characters for task names (see configMAX_TASK_NAME_LEN documentation for\nmore details).\n\nNote: For most uses, the default of 16 characters is sufficient.",
+                                "id": "FREERTOS_MAX_TASK_NAME_LEN",
+                                "name": "FREERTOS_MAX_TASK_NAME_LEN",
+                                "range": [
+                                    1,
+                                    256
+                                ],
+                                "title": "configMAX_TASK_NAME_LEN",
+                                "type": "int"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "!IDF_TARGET_LINUX",
+                                "help": "Enable backward compatibility with APIs prior to FreeRTOS v8.0.0. (see\nconfigENABLE_BACKWARD_COMPATIBILITY documentation for more details).",
+                                "id": "FREERTOS_ENABLE_BACKWARD_COMPATIBILITY",
+                                "name": "FREERTOS_ENABLE_BACKWARD_COMPATIBILITY",
+                                "range": null,
+                                "title": "configENABLE_BACKWARD_COMPATIBILITY",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [
+                                    {
+                                        "children": [],
+                                        "depends_on": "FREERTOS_USE_TIMERS",
+                                        "help": "Sets the timer task's name (see configTIMER_SERVICE_TASK_NAME documentation for more details).",
+                                        "id": "FREERTOS_TIMER_SERVICE_TASK_NAME",
+                                        "name": "FREERTOS_TIMER_SERVICE_TASK_NAME",
+                                        "range": null,
+                                        "title": "configTIMER_SERVICE_TASK_NAME",
+                                        "type": "string"
+                                    },
+                                    {
+                                        "children": [
+                                            {
+                                                "children": [],
+                                                "depends_on": "<choice FREERTOS_TIMER_SERVICE_TASK_CORE_AFFINITY>",
+                                                "help": null,
+                                                "id": "FREERTOS_TIMER_TASK_AFFINITY_CPU0",
+                                                "name": "FREERTOS_TIMER_TASK_AFFINITY_CPU0",
+                                                "range": null,
+                                                "title": "CPU0",
+                                                "type": "bool"
+                                            },
+                                            {
+                                                "children": [],
+                                                "depends_on": "!FREERTOS_UNICORE && <choice FREERTOS_TIMER_SERVICE_TASK_CORE_AFFINITY>",
+                                                "help": null,
+                                                "id": "FREERTOS_TIMER_TASK_AFFINITY_CPU1",
+                                                "name": "FREERTOS_TIMER_TASK_AFFINITY_CPU1",
+                                                "range": null,
+                                                "title": "CPU1",
+                                                "type": "bool"
+                                            },
+                                            {
+                                                "children": [],
+                                                "depends_on": "<choice FREERTOS_TIMER_SERVICE_TASK_CORE_AFFINITY>",
+                                                "help": null,
+                                                "id": "FREERTOS_TIMER_TASK_NO_AFFINITY",
+                                                "name": "FREERTOS_TIMER_TASK_NO_AFFINITY",
+                                                "range": null,
+                                                "title": "No affinity",
+                                                "type": "bool"
+                                            }
+                                        ],
+                                        "depends_on": "FREERTOS_USE_TIMERS",
+                                        "help": "Sets the timer task's core affinity\n(see configTIMER_SERVICE_TASK_CORE_AFFINITY documentation for more details).",
+                                        "id": "component-config-freertos-kernel-configuse_timers-configtimer_service_task_core_affinity",
+                                        "name": "FREERTOS_TIMER_SERVICE_TASK_CORE_AFFINITY",
+                                        "title": "configTIMER_SERVICE_TASK_CORE_AFFINITY",
+                                        "type": "choice"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "FREERTOS_USE_TIMERS",
+                                        "help": null,
+                                        "id": "FREERTOS_TIMER_SERVICE_TASK_CORE_AFFINITY",
+                                        "name": "FREERTOS_TIMER_SERVICE_TASK_CORE_AFFINITY",
+                                        "range": null,
+                                        "title": null,
+                                        "type": "hex"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "FREERTOS_USE_TIMERS",
+                                        "help": "Sets the timer task's priority (see configTIMER_TASK_PRIORITY documentation for more details).",
+                                        "id": "FREERTOS_TIMER_TASK_PRIORITY",
+                                        "name": "FREERTOS_TIMER_TASK_PRIORITY",
+                                        "range": [
+                                            1,
+                                            25
+                                        ],
+                                        "title": "configTIMER_TASK_PRIORITY",
+                                        "type": "int"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "FREERTOS_USE_TIMERS",
+                                        "help": "Set the timer task's stack size (see configTIMER_TASK_STACK_DEPTH documentation for more details).",
+                                        "id": "FREERTOS_TIMER_TASK_STACK_DEPTH",
+                                        "name": "FREERTOS_TIMER_TASK_STACK_DEPTH",
+                                        "range": [
+                                            1536,
+                                            32768
+                                        ],
+                                        "title": "configTIMER_TASK_STACK_DEPTH",
+                                        "type": "int"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "FREERTOS_USE_TIMERS",
+                                        "help": "Set the timer task's command queue length (see configTIMER_QUEUE_LENGTH documentation for more\ndetails).",
+                                        "id": "FREERTOS_TIMER_QUEUE_LENGTH",
+                                        "name": "FREERTOS_TIMER_QUEUE_LENGTH",
+                                        "range": [
+                                            5,
+                                            20
+                                        ],
+                                        "title": "configTIMER_QUEUE_LENGTH",
+                                        "type": "int"
+                                    }
+                                ],
+                                "depends_on": null,
+                                "help": "Enable FreeRTOS Software Timers. Normally the timer task will only get pulled into the build\nand created if any software timer related functions are used. This is achieved through IDF\ndefining a weak empty function for xTimerCreateTimerTask, which should take effect if timers.c\nis not pulled into the build.\n\nIn certain special cases (if you use configUSE_TRACE_FACILITY=y and event groups) the linker will\nstill pull in the xTimerCreateTimerTask from timers.c even if the function that utilized it gets\ndiscarded due to not being used.\n\nIn these cases you can use this option to force the timer task to be disabled.",
+                                "id": "FREERTOS_USE_TIMERS",
+                                "name": "FREERTOS_USE_TIMERS",
+                                "range": null,
+                                "title": "configUSE_TIMERS",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "Set the size of the queue registry (see configQUEUE_REGISTRY_SIZE documentation for more details).\n\nNote: A value of 0 will disable queue registry functionality",
+                                "id": "FREERTOS_QUEUE_REGISTRY_SIZE",
+                                "name": "FREERTOS_QUEUE_REGISTRY_SIZE",
+                                "range": [
+                                    0,
+                                    20
+                                ],
+                                "title": "configQUEUE_REGISTRY_SIZE",
+                                "type": "int"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "Set the size of the task notification array of each task. When increasing this value, keep in\nmind that this means additional memory for each and every task on the system.\nHowever, task notifications in general are more light weight compared to alternatives\nsuch as semaphores.",
+                                "id": "FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES",
+                                "name": "FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES",
+                                "range": [
+                                    1,
+                                    32
+                                ],
+                                "title": "configTASK_NOTIFICATION_ARRAY_ENTRIES",
+                                "type": "int"
+                            },
+                            {
+                                "children": [
+                                    {
+                                        "children": [],
+                                        "depends_on": "FREERTOS_USE_TRACE_FACILITY",
+                                        "help": "Set configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS to 1 to include the\n``vTaskList()`` and ``vTaskGetRunTimeStats()`` functions in the build (see\nconfigUSE_STATS_FORMATTING_FUNCTIONS documentation for more details).",
+                                        "id": "FREERTOS_USE_STATS_FORMATTING_FUNCTIONS",
+                                        "name": "FREERTOS_USE_STATS_FORMATTING_FUNCTIONS",
+                                        "range": null,
+                                        "title": "configUSE_STATS_FORMATTING_FUNCTIONS",
+                                        "type": "bool"
+                                    }
+                                ],
+                                "depends_on": null,
+                                "help": "Enables additional structure members and functions to assist with execution visualization and tracing\n(see configUSE_TRACE_FACILITY documentation for more details).",
+                                "id": "FREERTOS_USE_TRACE_FACILITY",
+                                "name": "FREERTOS_USE_TRACE_FACILITY",
+                                "range": null,
+                                "title": "configUSE_TRACE_FACILITY",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "Enable list integrity checker\n(see configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES documentation for more details).",
+                                "id": "FREERTOS_USE_LIST_DATA_INTEGRITY_CHECK_BYTES",
+                                "name": "FREERTOS_USE_LIST_DATA_INTEGRITY_CHECK_BYTES",
+                                "range": null,
+                                "title": "configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "!FREERTOS_SMP && FREERTOS_USE_STATS_FORMATTING_FUNCTIONS",
+                                "help": "If enabled, this will include an extra column when vTaskList is called to display the CoreID the task\nis pinned to (0,1) or -1 if not pinned.",
+                                "id": "FREERTOS_VTASKLIST_INCLUDE_COREID",
+                                "name": "FREERTOS_VTASKLIST_INCLUDE_COREID",
+                                "range": null,
+                                "title": "Enable display of xCoreID in vTaskList",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [
+                                    {
+                                        "children": [
+                                            {
+                                                "children": [],
+                                                "depends_on": "<choice FREERTOS_RUN_TIME_COUNTER_TYPE>",
+                                                "help": "configRUN_TIME_COUNTER_TYPE is set to uint32_t",
+                                                "id": "FREERTOS_RUN_TIME_COUNTER_TYPE_U32",
+                                                "name": "FREERTOS_RUN_TIME_COUNTER_TYPE_U32",
+                                                "range": null,
+                                                "title": "uint32_t",
+                                                "type": "bool"
+                                            },
+                                            {
+                                                "children": [],
+                                                "depends_on": "<choice FREERTOS_RUN_TIME_COUNTER_TYPE>",
+                                                "help": "configRUN_TIME_COUNTER_TYPE is set to uint64_t",
+                                                "id": "FREERTOS_RUN_TIME_COUNTER_TYPE_U64",
+                                                "name": "FREERTOS_RUN_TIME_COUNTER_TYPE_U64",
+                                                "range": null,
+                                                "title": "uint64_t",
+                                                "type": "bool"
+                                            }
+                                        ],
+                                        "depends_on": "FREERTOS_GENERATE_RUN_TIME_STATS && !FREERTOS_SMP",
+                                        "help": "Sets the data type used for the FreeRTOS run time stats. A larger data type can be used to reduce the\nfrequency of the counter overflowing.",
+                                        "id": "component-config-freertos-kernel-configgenerate_run_time_stats-configrun_time_counter_type",
+                                        "name": "FREERTOS_RUN_TIME_COUNTER_TYPE",
+                                        "title": "configRUN_TIME_COUNTER_TYPE",
+                                        "type": "choice"
+                                    }
+                                ],
+                                "depends_on": null,
+                                "help": "Enables collection of run time statistics for each task (see configGENERATE_RUN_TIME_STATS\ndocumentation for more details).\n\nNote: The clock used for run time statistics can be configured in FREERTOS_RUN_TIME_STATS_CLK.",
+                                "id": "FREERTOS_GENERATE_RUN_TIME_STATS",
+                                "name": "FREERTOS_GENERATE_RUN_TIME_STATS",
+                                "range": null,
+                                "title": "configGENERATE_RUN_TIME_STATS",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [
+                                    {
+                                        "children": [],
+                                        "depends_on": "FREERTOS_USE_TICKLESS_IDLE",
+                                        "help": "FreeRTOS will enter light sleep mode if no tasks need to run for this number of ticks.\nYou can enable PM_PROFILING feature in esp_pm components and dump the sleep status with\nesp_pm_dump_locks, if the proportion of rejected sleeps is too high, please increase\nthis value to improve scheduling efficiency",
+                                        "id": "FREERTOS_IDLE_TIME_BEFORE_SLEEP",
+                                        "name": "FREERTOS_IDLE_TIME_BEFORE_SLEEP",
+                                        "range": null,
+                                        "title": "configEXPECTED_IDLE_TIME_BEFORE_SLEEP",
+                                        "type": "int"
+                                    }
+                                ],
+                                "depends_on": "PM_ENABLE",
+                                "help": "If power management support is enabled, FreeRTOS will be able to put the system into light sleep mode\nwhen no tasks need to run for a number of ticks. This number can be set using\nFREERTOS_IDLE_TIME_BEFORE_SLEEP option. This feature is also known as \"automatic light sleep\".\n\nNote that timers created using esp_timer APIs may prevent the system from entering sleep mode, even\nwhen no tasks need to run. To skip unnecessary wake-up initialize a timer with the\n\"skip_unhandled_events\" option as true.\n\nIf disabled, automatic light sleep support will be disabled.",
+                                "id": "FREERTOS_USE_TICKLESS_IDLE",
+                                "name": "FREERTOS_USE_TICKLESS_IDLE",
+                                "range": null,
+                                "title": "configUSE_TICKLESS_IDLE",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "Enables task tagging functionality and its associated API (see configUSE_APPLICATION_TASK_TAG\ndocumentation for more details).",
+                                "id": "FREERTOS_USE_APPLICATION_TASK_TAG",
+                                "name": "FREERTOS_USE_APPLICATION_TASK_TAG",
+                                "range": null,
+                                "title": "configUSE_APPLICATION_TASK_TAG",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": null,
+                        "id": "component-config-freertos-kernel",
+                        "title": "Kernel",
+                        "type": "menu"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "COMPILER_OPTIMIZATION_DEBUG || ESP_COREDUMP_ENABLE || ESP_SYSTEM_PANIC_GDBSTUB || ESP_SYSTEM_GDBSTUB_RUNTIME",
+                                "help": "If enabled, all FreeRTOS task functions will be enclosed in a wrapper function. If a task function\nmistakenly returns (i.e. does not delete), the call flow will return to the wrapper function. The\nwrapper function will then log an error and abort the application. This option is also required for GDB\nbacktraces and C++ exceptions to work correctly inside top-level task functions.",
+                                "id": "FREERTOS_TASK_FUNCTION_WRAPPER",
+                                "name": "FREERTOS_TASK_FUNCTION_WRAPPER",
+                                "range": null,
+                                "title": "Wrap task functions",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "FreeRTOS can check if a stack has overflown its bounds by checking either the value of the stack\npointer or by checking the integrity of canary bytes. (See FREERTOS_CHECK_STACKOVERFLOW for more\ninformation.) These checks only happen on a context switch, and the situation that caused the stack\noverflow may already be long gone by then. This option will use the last debug memory watchpoint to\nallow breaking into the debugger (or panic'ing) as soon as any of the last 32 bytes on the stack of a\ntask are overwritten. The side effect is that using gdb, you effectively have one hardware watchpoint\nless because the last one is overwritten as soon as a task switch happens.\n\nAnother consequence is that due to alignment requirements of the watchpoint, the usable stack size\ndecreases by up to 60 bytes. This is because the watchpoint region has to be aligned to its size and\nthe size for the stack watchpoint in IDF is 32 bytes.\n\nThis check only triggers if the stack overflow writes within 32 bytes near the end of the stack, rather\nthan overshooting further, so it is worth combining this approach with one of the other stack overflow\ncheck methods.\n\nWhen this watchpoint is hit, gdb will stop with a SIGTRAP message. When no JTAG OCD is attached,\nesp-idf will panic on an unhandled debug exception.",
+                                "id": "FREERTOS_WATCHPOINT_END_OF_STACK",
+                                "name": "FREERTOS_WATCHPOINT_END_OF_STACK",
+                                "range": null,
+                                "title": "Enable stack overflow debug watchpoint",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "FREERTOS_THREAD_LOCAL_STORAGE_POINTERS > 0",
+                                "help": "ESP-IDF provides users with the ability to free TLSP memory by registering TLSP deletion callbacks.\nThese callbacks are automatically called by FreeRTOS when a task is deleted. When this option is turned\non, the memory reserved for TLSPs in the TCB is doubled to make space for storing the deletion\ncallbacks. If the user does not wish to use TLSP deletion callbacks then this option could be turned\noff to save space in the TCB memory.",
+                                "id": "FREERTOS_TLSP_DELETION_CALLBACKS",
+                                "name": "FREERTOS_TLSP_DELETION_CALLBACKS",
+                                "range": null,
+                                "title": "Enable thread local storage pointers deletion callbacks",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "!FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP",
+                                "help": "Enable this option to make FreeRTOS call a user provided hook function right before it deletes a task\n(i.e., frees/releases a dynamically/statically allocated task's memory). This is useful if users want\nto know when a task is actually deleted (in case the task's deletion is delegated to the IDLE task).\n\nIf this config option is enabled, users must define a ``void vTaskPreDeletionHook( void * pxTCB )``\nhook function in their application.",
+                                "id": "FREERTOS_TASK_PRE_DELETION_HOOK",
+                                "name": "FREERTOS_TASK_PRE_DELETION_HOOK",
+                                "range": null,
+                                "title": "Enable task pre-deletion hook",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "THIS OPTION IS DEPRECATED. Use FREERTOS_TASK_PRE_DELETION_HOOK instead.\n\nEnable this option to make FreeRTOS call the static task clean up hook when a task is deleted.\n\nNote: Users will need to provide a ``void vPortCleanUpTCB ( void *pxTCB )`` callback",
+                                "id": "FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP",
+                                "name": "FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP",
+                                "range": null,
+                                "title": "Enable static task clean up hook (DEPRECATED)",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "!FREERTOS_SMP",
+                                "help": "If enabled, assert that when a mutex semaphore is given, the task giving the semaphore is the task\nwhich is currently holding the mutex.",
+                                "id": "FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER",
+                                "name": "FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER",
+                                "range": null,
+                                "title": "Check that mutex semaphore is given by owner task",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "The interrupt handlers have their own stack. The size of the stack can be defined here. Each processor\nhas its own stack, so the total size occupied will be twice this.",
+                                "id": "FREERTOS_ISR_STACKSIZE",
+                                "name": "FREERTOS_ISR_STACKSIZE",
+                                "range": [
+                                    1536,
+                                    32768
+                                ],
+                                "title": "ISR stack size",
+                                "type": "int"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "If this option is enabled, interrupt stack frame will be modified to point to the code of the\ninterrupted task as its return address. This helps the debugger (or the panic handler) show a backtrace\nfrom the interrupt to the task which was interrupted. This also works for nested interrupts: higher\nlevel interrupt stack can be traced back to the lower level interrupt. This option adds 4 instructions\nto the interrupt dispatching code.",
+                                "id": "FREERTOS_INTERRUPT_BACKTRACE",
+                                "name": "FREERTOS_INTERRUPT_BACKTRACE",
+                                "range": null,
+                                "title": "Enable backtrace from interrupt to task context",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "SOC_CPU_HAS_FPU && (IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3)",
+                                "help": "When enabled, the usage of float type is allowed inside Level 1 ISRs. Note that usage of float types in\nhigher level interrupts is still not permitted.",
+                                "id": "FREERTOS_FPU_IN_ISR",
+                                "name": "FREERTOS_FPU_IN_ISR",
+                                "range": null,
+                                "title": "Use float in Level 1 ISR",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "FREERTOS_TICK_SUPPORT_CORETIMER",
+                                "name": "FREERTOS_TICK_SUPPORT_CORETIMER",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "FREERTOS_TICK_SUPPORT_SYSTIMER",
+                                "name": "FREERTOS_TICK_SUPPORT_SYSTIMER",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [
+                                    {
+                                        "children": [],
+                                        "depends_on": "FREERTOS_TICK_SUPPORT_CORETIMER && <choice FREERTOS_CORETIMER>",
+                                        "help": "Select this to use timer 0",
+                                        "id": "FREERTOS_CORETIMER_0",
+                                        "name": "FREERTOS_CORETIMER_0",
+                                        "range": null,
+                                        "title": "Timer 0 (int 6, level 1)",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "FREERTOS_TICK_SUPPORT_CORETIMER && <choice FREERTOS_CORETIMER>",
+                                        "help": "Select this to use timer 1",
+                                        "id": "FREERTOS_CORETIMER_1",
+                                        "name": "FREERTOS_CORETIMER_1",
+                                        "range": null,
+                                        "title": "Timer 1 (int 15, level 3)",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "FREERTOS_TICK_SUPPORT_SYSTIMER && <choice FREERTOS_CORETIMER>",
+                                        "help": "Select this to use systimer with the 1 interrupt priority.",
+                                        "id": "FREERTOS_CORETIMER_SYSTIMER_LVL1",
+                                        "name": "FREERTOS_CORETIMER_SYSTIMER_LVL1",
+                                        "range": null,
+                                        "title": "SYSTIMER 0 (level 1)",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "FREERTOS_TICK_SUPPORT_SYSTIMER && <choice FREERTOS_CORETIMER>",
+                                        "help": "Select this to use systimer with the 3 interrupt priority.",
+                                        "id": "FREERTOS_CORETIMER_SYSTIMER_LVL3",
+                                        "name": "FREERTOS_CORETIMER_SYSTIMER_LVL3",
+                                        "range": null,
+                                        "title": "SYSTIMER 0 (level 3)",
+                                        "type": "bool"
+                                    }
+                                ],
+                                "depends_on": null,
+                                "help": "FreeRTOS needs a timer with an associated interrupt to use as the main tick source to increase\ncounters, run timers and do pre-emptive multitasking with. There are multiple timers available to do\nthis, with different interrupt priorities.",
+                                "id": "component-config-freertos-port-tick-timer-source-xtensa-only-",
+                                "name": "FREERTOS_CORETIMER",
+                                "title": "Tick timer source (Xtensa Only)",
+                                "type": "choice"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "FREERTOS_SYSTICK_USES_SYSTIMER",
+                                "name": "FREERTOS_SYSTICK_USES_SYSTIMER",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "FREERTOS_SYSTICK_USES_CCOUNT",
+                                "name": "FREERTOS_SYSTICK_USES_CCOUNT",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice FREERTOS_RUN_TIME_STATS_CLK>",
+                                        "help": "ESP Timer will be used as the clock source for FreeRTOS run time stats. The ESP Timer runs at a\nfrequency of 1MHz regardless of Dynamic Frequency Scaling. Therefore the ESP Timer will overflow in\napproximately 4290 seconds.",
+                                        "id": "FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER",
+                                        "name": "FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER",
+                                        "range": null,
+                                        "title": "Use ESP TIMER for run time stats",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "FREERTOS_SYSTICK_USES_CCOUNT && <choice FREERTOS_RUN_TIME_STATS_CLK>",
+                                        "help": "CPU Clock will be used as the clock source for the generation of run time stats. The CPU Clock has\na frequency dependent on ESP_DEFAULT_CPU_FREQ_MHZ and Dynamic Frequency Scaling (DFS). Therefore\nthe CPU Clock frequency can fluctuate between 80 to 240MHz. Run time stats generated using the CPU\nClock represents the number of CPU cycles each task is allocated and DOES NOT reflect the amount of\ntime each task runs for (as CPU clock frequency can change). If the CPU clock consistently runs at\nthe maximum frequency of 240MHz, it will overflow in approximately 17 seconds.",
+                                        "id": "FREERTOS_RUN_TIME_STATS_USING_CPU_CLK",
+                                        "name": "FREERTOS_RUN_TIME_STATS_USING_CPU_CLK",
+                                        "range": null,
+                                        "title": "Use CPU Clock for run time stats",
+                                        "type": "bool"
+                                    }
+                                ],
+                                "depends_on": "FREERTOS_GENERATE_RUN_TIME_STATS",
+                                "help": "Choose the clock source for FreeRTOS run time stats. Options are CPU0's CPU Clock or the ESP Timer.\nBoth clock sources are 32 bits. The CPU Clock can run at a higher frequency hence provide a finer\nresolution but will overflow much quicker. Note that run time stats are only valid until the clock\nsource overflows.",
+                                "id": "component-config-freertos-port-choose-the-clock-source-for-run-time-stats",
+                                "name": "FREERTOS_RUN_TIME_STATS_CLK",
+                                "title": "Choose the clock source for run time stats",
+                                "type": "choice"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "When enabled the selected Non-ISR FreeRTOS functions will be placed into Flash memory instead of IRAM.\nThis saves up to 8KB of IRAM depending on which functions are used.",
+                                "id": "FREERTOS_PLACE_FUNCTIONS_INTO_FLASH",
+                                "name": "FREERTOS_PLACE_FUNCTIONS_INTO_FLASH",
+                                "range": null,
+                                "title": "Place FreeRTOS functions into Flash",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "If enabled, context of port*_CRITICAL calls (ISR or Non-ISR) would be checked to be in compliance with\nVanilla FreeRTOS. e.g Calling port*_CRITICAL from ISR context would cause assert failure",
+                                "id": "FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE",
+                                "name": "FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE",
+                                "range": null,
+                                "title": "Tests compliance with Vanilla FreeRTOS port*_CRITICAL calls",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": null,
+                        "id": "component-config-freertos-port",
+                        "title": "Port",
+                        "type": "menu"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "SPIRAM && FREERTOS_SUPPORT_STATIC_ALLOCATION",
+                                "help": "Accessing memory in PSRAM has certain restrictions, so task stacks allocated by xTaskCreate\nare by default allocated from internal RAM.\n\nThis option allows for passing memory allocated from SPIRAM to be passed to xTaskCreateStatic.\nThis should only be used for tasks where the stack is never accessed while the cache is disabled.\n\nExtra notes for ESP32:\n\nBecause some bits of the ESP32 code environment cannot be recompiled with the cache workaround,\nnormally tasks cannot be safely run with their stack residing in external memory; for this reason\nxTaskCreate (and related task creation functions) always allocate stack in internal memory and\nxTaskCreateStatic will check if the memory passed to it is in internal memory.\nIf you have a task that needs a large amount of stack and does not call on ROM code in any way\n(no direct calls, but also no Bluetooth/WiFi), you can try enable this to\ncause xTaskCreateStatic to allow tasks stack in external memory.",
+                                "id": "FREERTOS_TASK_CREATE_ALLOW_EXT_MEM",
+                                "name": "FREERTOS_TASK_CREATE_ALLOW_EXT_MEM",
+                                "range": null,
+                                "title": "Allow external memory as an argument to xTaskCreateStatic (READ HELP)",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": null,
+                        "id": "component-config-freertos-extra",
+                        "title": "Extra",
+                        "type": "menu"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": null,
+                        "id": "FREERTOS_PORT",
+                        "name": "FREERTOS_PORT",
+                        "range": null,
+                        "title": null,
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": null,
+                        "id": "FREERTOS_NO_AFFINITY",
+                        "name": "FREERTOS_NO_AFFINITY",
+                        "range": null,
+                        "title": null,
+                        "type": "hex"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": null,
+                        "id": "FREERTOS_SUPPORT_STATIC_ALLOCATION",
+                        "name": "FREERTOS_SUPPORT_STATIC_ALLOCATION",
+                        "range": null,
+                        "title": null,
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": "Hidden option, gets selected by CONFIG_ESP_DEBUG_OCDAWARE",
+                        "id": "FREERTOS_DEBUG_OCDAWARE",
+                        "name": "FREERTOS_DEBUG_OCDAWARE",
+                        "range": null,
+                        "title": null,
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": null,
+                        "id": "FREERTOS_ENABLE_TASK_SNAPSHOT",
+                        "name": "FREERTOS_ENABLE_TASK_SNAPSHOT",
+                        "range": null,
+                        "title": null,
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "!ESP_PANIC_HANDLER_IRAM",
+                        "help": null,
+                        "id": "FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH",
+                        "name": "FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH",
+                        "range": null,
+                        "title": null,
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": null,
+                        "id": "FREERTOS_NUMBER_OF_CORES",
+                        "name": "FREERTOS_NUMBER_OF_CORES",
+                        "range": [
+                            1,
+                            2
+                        ],
+                        "title": null,
+                        "type": "int"
+                    }
+                ],
+                "depends_on": null,
+                "id": "component-config-freertos",
+                "title": "FreeRTOS",
+                "type": "menu"
+            },
+            {
+                "children": [
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "<choice HAL_DEFAULT_ASSERTION_LEVEL>",
+                                "help": null,
+                                "id": "HAL_ASSERTION_EQUALS_SYSTEM",
+                                "name": "HAL_ASSERTION_EQUALS_SYSTEM",
+                                "range": null,
+                                "title": "Same as system assertion level",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "COMPILER_OPTIMIZATION_ASSERTION_LEVEL >= 0 && <choice HAL_DEFAULT_ASSERTION_LEVEL>",
+                                "help": null,
+                                "id": "HAL_ASSERTION_DISABLE",
+                                "name": "HAL_ASSERTION_DISABLE",
+                                "range": null,
+                                "title": "Disabled",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "COMPILER_OPTIMIZATION_ASSERTION_LEVEL >= 1 && <choice HAL_DEFAULT_ASSERTION_LEVEL>",
+                                "help": null,
+                                "id": "HAL_ASSERTION_SILENT",
+                                "name": "HAL_ASSERTION_SILENT",
+                                "range": null,
+                                "title": "Silent",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "COMPILER_OPTIMIZATION_ASSERTION_LEVEL >= 2 && <choice HAL_DEFAULT_ASSERTION_LEVEL>",
+                                "help": null,
+                                "id": "HAL_ASSERTION_ENABLE",
+                                "name": "HAL_ASSERTION_ENABLE",
+                                "range": null,
+                                "title": "Enabled",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": null,
+                        "help": "Set the assert behavior / level for HAL component.\nHAL component assert level can be set separately,\nbut the level can't exceed the system assertion level.\ne.g. If the system assertion is disabled, then the HAL\nassertion can't be enabled either. If the system assertion\nis enable, then the HAL assertion can still be disabled\nby this Kconfig option.",
+                        "id": "component-config-hardware-abstraction-layer-hal-and-low-level-ll--default-hal-assertion-level",
+                        "name": "HAL_DEFAULT_ASSERTION_LEVEL",
+                        "title": "Default HAL assertion level",
+                        "type": "choice"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": null,
+                        "id": "HAL_DEFAULT_ASSERTION_LEVEL",
+                        "name": "HAL_DEFAULT_ASSERTION_LEVEL",
+                        "range": null,
+                        "title": null,
+                        "type": "int"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "<choice HAL_LOG_LEVEL>",
+                                "help": null,
+                                "id": "HAL_LOG_LEVEL_NONE",
+                                "name": "HAL_LOG_LEVEL_NONE",
+                                "range": null,
+                                "title": "No output",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice HAL_LOG_LEVEL>",
+                                "help": null,
+                                "id": "HAL_LOG_LEVEL_ERROR",
+                                "name": "HAL_LOG_LEVEL_ERROR",
+                                "range": null,
+                                "title": "Error",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice HAL_LOG_LEVEL>",
+                                "help": null,
+                                "id": "HAL_LOG_LEVEL_WARN",
+                                "name": "HAL_LOG_LEVEL_WARN",
+                                "range": null,
+                                "title": "Warning",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice HAL_LOG_LEVEL>",
+                                "help": null,
+                                "id": "HAL_LOG_LEVEL_INFO",
+                                "name": "HAL_LOG_LEVEL_INFO",
+                                "range": null,
+                                "title": "Info",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice HAL_LOG_LEVEL>",
+                                "help": null,
+                                "id": "HAL_LOG_LEVEL_DEBUG",
+                                "name": "HAL_LOG_LEVEL_DEBUG",
+                                "range": null,
+                                "title": "Debug",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice HAL_LOG_LEVEL>",
+                                "help": null,
+                                "id": "HAL_LOG_LEVEL_VERBOSE",
+                                "name": "HAL_LOG_LEVEL_VERBOSE",
+                                "range": null,
+                                "title": "Verbose",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": "!LOG_DEFAULT_LEVEL_NONE && !LOG_DEFAULT_LEVEL_ERROR && !LOG_DEFAULT_LEVEL_WARN && !LOG_DEFAULT_LEVEL_INFO && !LOG_DEFAULT_LEVEL_DEBUG && !LOG_DEFAULT_LEVEL_VERBOSE",
+                        "help": "Specify how much output to see in HAL logs.",
+                        "id": "component-config-hardware-abstraction-layer-hal-and-low-level-ll--hal-layer-log-verbosity",
+                        "name": "HAL_LOG_LEVEL",
+                        "title": "HAL layer log verbosity",
+                        "type": "choice"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": null,
+                        "id": "HAL_LOG_LEVEL",
+                        "name": "HAL_LOG_LEVEL",
+                        "range": null,
+                        "title": null,
+                        "type": "int"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "ESP_ROM_HAS_HAL_SYSTIMER",
+                        "help": "Enable this flag to use HAL functions from ROM instead of ESP-IDF.\n\nIf keeping this as \"n\" in your project, you will have less free IRAM.\nIf making this as \"y\" in your project, you will increase free IRAM,\nbut you will lose the possibility to debug this module, and some new\nfeatures will be added and bugs will be fixed in the IDF source\nbut cannot be synced to ROM.",
+                        "id": "HAL_SYSTIMER_USE_ROM_IMPL",
+                        "name": "HAL_SYSTIMER_USE_ROM_IMPL",
+                        "range": null,
+                        "title": "Use ROM implementation of SysTimer HAL driver",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "ESP_ROM_HAS_HAL_WDT",
+                        "help": "Enable this flag to use HAL functions from ROM instead of ESP-IDF.\n\nIf keeping this as \"n\" in your project, you will have less free IRAM.\nIf making this as \"y\" in your project, you will increase free IRAM,\nbut you will lose the possibility to debug this module, and some new\nfeatures will be added and bugs will be fixed in the IDF source\nbut cannot be synced to ROM.",
+                        "id": "HAL_WDT_USE_ROM_IMPL",
+                        "name": "HAL_WDT_USE_ROM_IMPL",
+                        "range": null,
+                        "title": "Use ROM implementation of WDT HAL driver",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "SPI_MASTER_ISR_IN_IRAM",
+                        "help": "Enable this option to place SPI master hal layer functions into IRAM.",
+                        "id": "HAL_SPI_MASTER_FUNC_IN_IRAM",
+                        "name": "HAL_SPI_MASTER_FUNC_IN_IRAM",
+                        "range": null,
+                        "title": null,
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "SPI_SLAVE_ISR_IN_IRAM",
+                        "help": "Enable this option to place SPI slave hal layer functions into IRAM.",
+                        "id": "HAL_SPI_SLAVE_FUNC_IN_IRAM",
+                        "name": "HAL_SPI_SLAVE_FUNC_IN_IRAM",
+                        "range": null,
+                        "title": null,
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "IDF_TARGET_ESP32H2",
+                        "help": "Enable this option to apply the countermeasure for ECDSA signature operation\nThis countermeasure masks the real ECDSA sign operation\nunder dummy sign operations to add randomness in the generated power signature.\nThis countermeasure is only necessary for ESP32-H2 < v1.2.",
+                        "id": "HAL_ECDSA_GEN_SIG_CM",
+                        "name": "HAL_ECDSA_GEN_SIG_CM",
+                        "range": null,
+                        "title": "Enable countermeasure for ECDSA signature generation",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": null,
+                "id": "component-config-hardware-abstraction-layer-hal-and-low-level-ll-",
+                "title": "Hardware Abstraction Layer (HAL) and Low Level (LL)",
+                "type": "menu"
+            },
+            {
+                "children": [
+                    {
+                        "children": [
+                            {
+                                "children": [
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice LOG_DEFAULT_LEVEL>",
+                                        "help": null,
+                                        "id": "LOG_DEFAULT_LEVEL_NONE",
+                                        "name": "LOG_DEFAULT_LEVEL_NONE",
+                                        "range": null,
+                                        "title": "No output",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice LOG_DEFAULT_LEVEL>",
+                                        "help": null,
+                                        "id": "LOG_DEFAULT_LEVEL_ERROR",
+                                        "name": "LOG_DEFAULT_LEVEL_ERROR",
+                                        "range": null,
+                                        "title": "Error",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice LOG_DEFAULT_LEVEL>",
+                                        "help": null,
+                                        "id": "LOG_DEFAULT_LEVEL_WARN",
+                                        "name": "LOG_DEFAULT_LEVEL_WARN",
+                                        "range": null,
+                                        "title": "Warning",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice LOG_DEFAULT_LEVEL>",
+                                        "help": null,
+                                        "id": "LOG_DEFAULT_LEVEL_INFO",
+                                        "name": "LOG_DEFAULT_LEVEL_INFO",
+                                        "range": null,
+                                        "title": "Info",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice LOG_DEFAULT_LEVEL>",
+                                        "help": null,
+                                        "id": "LOG_DEFAULT_LEVEL_DEBUG",
+                                        "name": "LOG_DEFAULT_LEVEL_DEBUG",
+                                        "range": null,
+                                        "title": "Debug",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice LOG_DEFAULT_LEVEL>",
+                                        "help": null,
+                                        "id": "LOG_DEFAULT_LEVEL_VERBOSE",
+                                        "name": "LOG_DEFAULT_LEVEL_VERBOSE",
+                                        "range": null,
+                                        "title": "Verbose",
+                                        "type": "bool"
+                                    }
+                                ],
+                                "depends_on": null,
+                                "help": "Specify how much output to see in logs by default.\nYou can set lower verbosity level at runtime using\nesp_log_level_set() function if LOG_DYNAMIC_LEVEL_CONTROL\nis enabled.\n\nBy default, this setting limits which log statements\nare compiled into the program. For example, selecting\n\"Warning\" would mean that changing log level to \"Debug\"\nat runtime will not be possible. To allow increasing log\nlevel above the default at runtime, see the next option.",
+                                "id": "component-config-log-log-level-default-log-verbosity",
+                                "name": "LOG_DEFAULT_LEVEL",
+                                "title": "Default log verbosity",
+                                "type": "choice"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "LOG_DEFAULT_LEVEL",
+                                "name": "LOG_DEFAULT_LEVEL",
+                                "range": null,
+                                "title": null,
+                                "type": "int"
+                            },
+                            {
+                                "children": [
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice LOG_MAXIMUM_LEVEL>",
+                                        "help": null,
+                                        "id": "LOG_MAXIMUM_EQUALS_DEFAULT",
+                                        "name": "LOG_MAXIMUM_EQUALS_DEFAULT",
+                                        "range": null,
+                                        "title": "Same as default",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "LOG_DEFAULT_LEVEL < 1 && <choice LOG_MAXIMUM_LEVEL>",
+                                        "help": null,
+                                        "id": "LOG_MAXIMUM_LEVEL_ERROR",
+                                        "name": "LOG_MAXIMUM_LEVEL_ERROR",
+                                        "range": null,
+                                        "title": "Error",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "LOG_DEFAULT_LEVEL < 2 && <choice LOG_MAXIMUM_LEVEL>",
+                                        "help": null,
+                                        "id": "LOG_MAXIMUM_LEVEL_WARN",
+                                        "name": "LOG_MAXIMUM_LEVEL_WARN",
+                                        "range": null,
+                                        "title": "Warning",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "LOG_DEFAULT_LEVEL < 3 && <choice LOG_MAXIMUM_LEVEL>",
+                                        "help": null,
+                                        "id": "LOG_MAXIMUM_LEVEL_INFO",
+                                        "name": "LOG_MAXIMUM_LEVEL_INFO",
+                                        "range": null,
+                                        "title": "Info",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "LOG_DEFAULT_LEVEL < 4 && <choice LOG_MAXIMUM_LEVEL>",
+                                        "help": null,
+                                        "id": "LOG_MAXIMUM_LEVEL_DEBUG",
+                                        "name": "LOG_MAXIMUM_LEVEL_DEBUG",
+                                        "range": null,
+                                        "title": "Debug",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "LOG_DEFAULT_LEVEL < 5 && <choice LOG_MAXIMUM_LEVEL>",
+                                        "help": null,
+                                        "id": "LOG_MAXIMUM_LEVEL_VERBOSE",
+                                        "name": "LOG_MAXIMUM_LEVEL_VERBOSE",
+                                        "range": null,
+                                        "title": "Verbose",
+                                        "type": "bool"
+                                    }
+                                ],
+                                "depends_on": null,
+                                "help": "This config option sets the highest log verbosity that it's possible to select\nat runtime by calling esp_log_level_set(). This level may be higher than\nthe default verbosity level which is set when the app starts up.\n\nThis can be used enable debugging output only at a critical point, for a particular\ntag, or to minimize startup time but then enable more logs once the firmware has\nloaded.\n\nNote that increasing the maximum available log level will increase the firmware\nbinary size.\n\nThis option only applies to logging from the app, the bootloader log level is\nfixed at compile time to the separate \"Bootloader log verbosity\" setting.",
+                                "id": "component-config-log-log-level-maximum-log-verbosity",
+                                "name": "LOG_MAXIMUM_LEVEL",
+                                "title": "Maximum log verbosity",
+                                "type": "choice"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "LOG_MAXIMUM_LEVEL",
+                                "name": "LOG_MAXIMUM_LEVEL",
+                                "range": null,
+                                "title": null,
+                                "type": "int"
+                            },
+                            {
+                                "children": [
+                                    {
+                                        "children": [],
+                                        "depends_on": null,
+                                        "help": "Enables an additional global \"master\" log level check that occurs before a log tag cache\nlookup. This is useful if you want to compile in a lot of logs that are selectable at\nruntime, but avoid the performance hit during periods where you don't want log output.\n\nExamples include remote log forwarding, or disabling logs during a time-critical or\nCPU-intensive section and re-enabling them later. Results in larger program size\ndepending on number of logs compiled in.\n\nIf enabled, defaults to LOG_DEFAULT_LEVEL and can be set using\nesp_log_set_level_master(). This check takes precedence over ESP_LOG_LEVEL_LOCAL.",
+                                        "id": "LOG_MASTER_LEVEL",
+                                        "name": "LOG_MASTER_LEVEL",
+                                        "range": null,
+                                        "title": "Enable global master log level",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": null,
+                                        "help": "Enabling this option allows dynamic changes to the log level at runtime\n(using esp_log_level_set()), providing the ability to increase or decrease\nthe log level during program execution.\nIf disabled, the log level remains static once set at compile-time and calling\nesp_log_level_set() will have no effect.\nIf binary size is a critical consideration and dynamic log level changes are not needed,\nconsider disabling this option when LOG_TAG_LEVEL_IMPL_NONE=y to minimize program size.",
+                                        "id": "LOG_DYNAMIC_LEVEL_CONTROL",
+                                        "name": "LOG_DYNAMIC_LEVEL_CONTROL",
+                                        "range": null,
+                                        "title": "Enable dynamic log level changes at runtime",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [
+                                            {
+                                                "children": [],
+                                                "depends_on": "<choice LOG_TAG_LEVEL_IMPL>",
+                                                "help": "This option disables the ability to set the log level per tag.\nThe ability to change the log level at runtime depends on LOG_DYNAMIC_LEVEL_CONTROL.\nIf LOG_DYNAMIC_LEVEL_CONTROL is disabled, then changing the log level at runtime\nusing `esp_log_level_set()` is not possible.\nThis implementation is suitable for highly constrained environments.",
+                                                "id": "LOG_TAG_LEVEL_IMPL_NONE",
+                                                "name": "LOG_TAG_LEVEL_IMPL_NONE",
+                                                "range": null,
+                                                "title": "None",
+                                                "type": "bool"
+                                            },
+                                            {
+                                                "children": [],
+                                                "depends_on": "<choice LOG_TAG_LEVEL_IMPL>",
+                                                "help": "Select this option to use the linked list-only implementation (no cache) for log level retrieval.\nThis approach searches the linked list of all tags for the log level, which may be slower\nfor a large number of tags but may have lower memory requirements than the CACHE approach.\nThe linked list approach compares the whole strings of log tags for finding the log level.",
+                                                "id": "LOG_TAG_LEVEL_IMPL_LINKED_LIST",
+                                                "name": "LOG_TAG_LEVEL_IMPL_LINKED_LIST",
+                                                "range": null,
+                                                "title": "Linked List",
+                                                "type": "bool"
+                                            },
+                                            {
+                                                "children": [],
+                                                "depends_on": "<choice LOG_TAG_LEVEL_IMPL>",
+                                                "help": "Select this option to use a hybrid mode: cache in combination with the linked list\nfor log tag level checks. This hybrid approach offers a balance between speed and memory usage.\n\nThe cache stores recently accessed log tags and their corresponding log levels, providing\nfaster lookups for frequently used tags. The cache approach compares the tag pointers, which is\nfaster than comparing the whole strings.\n\nFor less frequently used tags, the linked list is used to search for the log level, which may be\nslower for a large number of tags but has lower memory requirements compared to a full cache.\n\nThis hybrid approach aims to improve the efficiency of log level retrieval by combining the benefits\nof both cache and linked list implementations.",
+                                                "id": "LOG_TAG_LEVEL_IMPL_CACHE_AND_LINKED_LIST",
+                                                "name": "LOG_TAG_LEVEL_IMPL_CACHE_AND_LINKED_LIST",
+                                                "range": null,
+                                                "title": "Cache + Linked List",
+                                                "type": "bool"
+                                            }
+                                        ],
+                                        "depends_on": null,
+                                        "help": "Choose the per-tag log level implementation for the log library. This functionality is used\nto enable/disable logs for a particular tag at run time. Applicable only for\napplication logs (i.e., not bootloader logs).",
+                                        "id": "component-config-log-log-level-level-settings-method-of-tag-level-checks",
+                                        "name": "LOG_TAG_LEVEL_IMPL",
+                                        "title": "Method of tag level checks",
+                                        "type": "choice"
+                                    },
+                                    {
+                                        "children": [
+                                            {
+                                                "children": [],
+                                                "depends_on": "<choice LOG_TAG_LEVEL_CACHE_IMPL>",
+                                                "help": "This option enables the use of a simple array-based cache implementation for storing and\nretrieving log tag levels. There is no additional code that reorders the cache for fast lookups.\nSuitable for projects where memory usage optimization is crucial and the simplicity of implementation\nis preferred.",
+                                                "id": "LOG_TAG_LEVEL_CACHE_ARRAY",
+                                                "name": "LOG_TAG_LEVEL_CACHE_ARRAY",
+                                                "range": null,
+                                                "title": "Array",
+                                                "type": "bool"
+                                            },
+                                            {
+                                                "children": [],
+                                                "depends_on": "<choice LOG_TAG_LEVEL_CACHE_IMPL>",
+                                                "help": "This option enables the use of a binary min-heap-based cache implementation for efficient\nstorage and retrieval of log tag levels. It does automatically optimizing cache for fast lookups.\nSuitable for projects where speed of lookup is critical and memory usage can accommodate\nthe overhead of maintaining a binary min-heap structure.",
+                                                "id": "LOG_TAG_LEVEL_CACHE_BINARY_MIN_HEAP",
+                                                "name": "LOG_TAG_LEVEL_CACHE_BINARY_MIN_HEAP",
+                                                "range": null,
+                                                "title": "Binary Min-Heap",
+                                                "type": "bool"
+                                            }
+                                        ],
+                                        "depends_on": "LOG_TAG_LEVEL_IMPL_CACHE_AND_LINKED_LIST",
+                                        "help": "The cache stores recently accessed log tags (address of tag) and their corresponding log levels,\nproviding faster lookups for frequently used tags. Cache size can be configured using the\nLOG_TAG_LEVEL_IMPL_CACHE_SIZE option. The cache approach compares the tag pointers, which is\nfaster than comparing the whole strings.",
+                                        "id": "component-config-log-log-level-level-settings-cache-implementation",
+                                        "name": "LOG_TAG_LEVEL_CACHE_IMPL",
+                                        "title": "Cache implementation",
+                                        "type": "choice"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "LOG_TAG_LEVEL_CACHE_ARRAY || LOG_TAG_LEVEL_CACHE_BINARY_MIN_HEAP",
+                                        "help": "This option sets the size of the cache used for log tag entries. The cache stores recently accessed\nlog tags and their corresponding log levels, which helps improve the efficiency of log level retrieval.\nThe value must be a power of 2 minus 1 (e.g., 1, 3, 7, 15, 31, 63, 127, 255, ...)\nto ensure proper cache behavior. For LOG_TAG_LEVEL_CACHE_ARRAY option the value can be any,\nwithout restrictions.\n\nNote: A larger cache size can improve lookup performance for frequently used log tags but may consume\nmore memory. Conversely, a smaller cache size reduces memory usage but may lead to more frequent cache\nevictions for less frequently used log tags.",
+                                        "id": "LOG_TAG_LEVEL_IMPL_CACHE_SIZE",
+                                        "name": "LOG_TAG_LEVEL_IMPL_CACHE_SIZE",
+                                        "range": null,
+                                        "title": "Log Tag Cache Size",
+                                        "type": "int"
+                                    }
+                                ],
+                                "depends_on": null,
+                                "id": "component-config-log-log-level-level-settings",
+                                "title": "Level Settings",
+                                "type": "menu"
+                            }
+                        ],
+                        "depends_on": null,
+                        "id": "component-config-log-log-level",
+                        "title": "Log Level",
+                        "type": "menu"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": "Enable ANSI terminal color codes.\nIn order to view these, your terminal program must support ANSI color codes.",
+                                "id": "LOG_COLORS",
+                                "name": "LOG_COLORS",
+                                "range": null,
+                                "title": "Color",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [
+                                    {
+                                        "children": [],
+                                        "depends_on": "NO_SYMBOL && <choice LOG_TIMESTAMP_SOURCE>",
+                                        "help": null,
+                                        "id": "LOG_TIMESTAMP_SOURCE_NONE",
+                                        "name": "LOG_TIMESTAMP_SOURCE_NONE",
+                                        "range": null,
+                                        "title": "None",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice LOG_TIMESTAMP_SOURCE>",
+                                        "help": null,
+                                        "id": "LOG_TIMESTAMP_SOURCE_RTOS",
+                                        "name": "LOG_TIMESTAMP_SOURCE_RTOS",
+                                        "range": null,
+                                        "title": "Milliseconds Since Boot",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice LOG_TIMESTAMP_SOURCE>",
+                                        "help": null,
+                                        "id": "LOG_TIMESTAMP_SOURCE_SYSTEM",
+                                        "name": "LOG_TIMESTAMP_SOURCE_SYSTEM",
+                                        "range": null,
+                                        "title": "System Time (HH:MM:SS.sss)",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "NO_SYMBOL && <choice LOG_TIMESTAMP_SOURCE>",
+                                        "help": null,
+                                        "id": "LOG_TIMESTAMP_SOURCE_SYSTEM_FULL",
+                                        "name": "LOG_TIMESTAMP_SOURCE_SYSTEM_FULL",
+                                        "range": null,
+                                        "title": "System Time (YY-MM-DD HH:MM:SS.sss)",
+                                        "type": "bool"
+                                    }
+                                ],
+                                "depends_on": null,
+                                "help": "Choose what sort of timestamp is displayed in the log output:\n\n- \"None\" - The log will only contain the actual log messages themselves\n  without any time-related information. Avoiding timestamps can help conserve\n  processing power and memory. It might useful when you\n  perform log analysis or debugging, sometimes it's more straightforward\n  to work with logs that lack timestamps, especially if the time of occurrence\n  is not critical for understanding the issues.\n\n- \"Milliseconds since boot\" is calculated from the RTOS tick count multiplied\n  by the tick period. This time will reset after a software reboot.\n  e.g. (90000)\n\n- \"System time (HH:MM:SS.sss)\" is taken from POSIX time functions which use the chip's\n  RTC and high resolution timers to maintain an accurate time. The system time is\n  initialized to 0 on startup, it can be set with an SNTP sync, or with\n  POSIX time functions. This time will not reset after a software reboot.\n  e.g. (00:01:30.000)\n\n- \"System time (YY-MM-DD HH:MM:SS.sss)\" it is the same as the above,\n  but also prints the date as well.\n\n- NOTE: Currently this will not get used in logging from binary blobs\n  (i.e WiFi & Bluetooth libraries), these will always print\n  milliseconds since boot.",
+                                "id": "component-config-log-format-timestamp",
+                                "name": "LOG_TIMESTAMP_SOURCE",
+                                "title": "Timestamp",
+                                "type": "choice"
+                            }
+                        ],
+                        "depends_on": null,
+                        "id": "component-config-log-format",
+                        "title": "Format",
+                        "type": "menu"
+                    }
+                ],
+                "depends_on": null,
+                "id": "component-config-log",
+                "title": "Log",
+                "type": "menu"
+            },
+            {
+                "children": [
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "<choice NEWLIB_STDOUT_LINE_ENDING>",
+                                "help": null,
+                                "id": "NEWLIB_STDOUT_LINE_ENDING_CRLF",
+                                "name": "NEWLIB_STDOUT_LINE_ENDING_CRLF",
+                                "range": null,
+                                "title": "CRLF",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice NEWLIB_STDOUT_LINE_ENDING>",
+                                "help": null,
+                                "id": "NEWLIB_STDOUT_LINE_ENDING_LF",
+                                "name": "NEWLIB_STDOUT_LINE_ENDING_LF",
+                                "range": null,
+                                "title": "LF",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice NEWLIB_STDOUT_LINE_ENDING>",
+                                "help": null,
+                                "id": "NEWLIB_STDOUT_LINE_ENDING_CR",
+                                "name": "NEWLIB_STDOUT_LINE_ENDING_CR",
+                                "range": null,
+                                "title": "CR",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": null,
+                        "help": "This option allows configuring the desired line endings sent to UART\nwhen a newline ('\\n', LF) appears on stdout.\nThree options are possible:\n\nCRLF: whenever LF is encountered, prepend it with CR\n\nLF: no modification is applied, stdout is sent as is\n\nCR: each occurrence of LF is replaced with CR\n\nThis option doesn't affect behavior of the UART driver (drivers/uart.h).",
+                        "id": "component-config-newlib-line-ending-for-uart-output",
+                        "name": "NEWLIB_STDOUT_LINE_ENDING",
+                        "title": "Line ending for UART output",
+                        "type": "choice"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "<choice NEWLIB_STDIN_LINE_ENDING>",
+                                "help": null,
+                                "id": "NEWLIB_STDIN_LINE_ENDING_CRLF",
+                                "name": "NEWLIB_STDIN_LINE_ENDING_CRLF",
+                                "range": null,
+                                "title": "CRLF",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice NEWLIB_STDIN_LINE_ENDING>",
+                                "help": null,
+                                "id": "NEWLIB_STDIN_LINE_ENDING_LF",
+                                "name": "NEWLIB_STDIN_LINE_ENDING_LF",
+                                "range": null,
+                                "title": "LF",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice NEWLIB_STDIN_LINE_ENDING>",
+                                "help": null,
+                                "id": "NEWLIB_STDIN_LINE_ENDING_CR",
+                                "name": "NEWLIB_STDIN_LINE_ENDING_CR",
+                                "range": null,
+                                "title": "CR",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": null,
+                        "help": "This option allows configuring which input sequence on UART produces\na newline ('\\n', LF) on stdin.\nThree options are possible:\n\nCRLF: CRLF is converted to LF\n\nLF: no modification is applied, input is sent to stdin as is\n\nCR: each occurrence of CR is replaced with LF\n\nThis option doesn't affect behavior of the UART driver (drivers/uart.h).",
+                        "id": "component-config-newlib-line-ending-for-uart-input",
+                        "name": "NEWLIB_STDIN_LINE_ENDING",
+                        "title": "Line ending for UART input",
+                        "type": "choice"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": null,
+                        "help": "In most chips the ROM contains parts of newlib C library, including printf/scanf family\nof functions. These functions have been compiled with so-called \"nano\"\nformatting option. This option doesn't support 64-bit integer formats and C99\nfeatures, such as positional arguments.\n\nFor more details about \"nano\" formatting option, please see newlib readme file,\nsearch for '--enable-newlib-nano-formatted-io':\nhttps://sourceware.org/git/?p=newlib-cygwin.git;a=blob_plain;f=newlib/README;hb=HEAD\n\nIf this option is enabled and the ROM contains functions from newlib-nano, the build system\nwill use functions available in ROM, reducing the application binary size.\nFunctions available in ROM run faster than functions which run from flash. Functions available\nin ROM can also run when flash instruction cache is disabled.\n\nSome chips (e.g. ESP32-C6) has the full formatting versions of printf/scanf in ROM instead of\nthe nano versions and in this building with newlib nano might actually increase the size of\nthe binary. Which functions are present in ROM can be seen from ROM caps:\nESP_ROM_HAS_NEWLIB_NANO_FORMAT and ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT.\n\nIf you need 64-bit integer formatting support or C99 features, keep this\noption disabled.",
+                        "id": "NEWLIB_NANO_FORMAT",
+                        "name": "NEWLIB_NANO_FORMAT",
+                        "range": null,
+                        "title": "Enable 'nano' formatting options for printf/scanf family",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "<choice NEWLIB_TIME_SYSCALL>",
+                                "help": null,
+                                "id": "NEWLIB_TIME_SYSCALL_USE_RTC_HRT",
+                                "name": "NEWLIB_TIME_SYSCALL_USE_RTC_HRT",
+                                "range": null,
+                                "title": "RTC and high-resolution timer",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice NEWLIB_TIME_SYSCALL>",
+                                "help": null,
+                                "id": "NEWLIB_TIME_SYSCALL_USE_RTC",
+                                "name": "NEWLIB_TIME_SYSCALL_USE_RTC",
+                                "range": null,
+                                "title": "RTC",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice NEWLIB_TIME_SYSCALL>",
+                                "help": null,
+                                "id": "NEWLIB_TIME_SYSCALL_USE_HRT",
+                                "name": "NEWLIB_TIME_SYSCALL_USE_HRT",
+                                "range": null,
+                                "title": "High-resolution timer",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice NEWLIB_TIME_SYSCALL>",
+                                "help": null,
+                                "id": "NEWLIB_TIME_SYSCALL_USE_NONE",
+                                "name": "NEWLIB_TIME_SYSCALL_USE_NONE",
+                                "range": null,
+                                "title": "None",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": null,
+                        "help": "This setting defines which hardware timers are used to\nimplement 'gettimeofday' and 'time' functions in C library.\n\n- If both high-resolution (systimer for all targets except ESP32)\n    and RTC timers are used, timekeeping will continue in deep sleep.\n    Time will be reported at 1 microsecond resolution.\n    This is the default, and the recommended option.\n- If only high-resolution timer (systimer) is used, gettimeofday will\n    provide time at microsecond resolution.\n    Time will not be preserved when going into deep sleep mode.\n- If only RTC timer is used, timekeeping will continue in\n    deep sleep, but time will be measured at 6.(6) microsecond\n    resolution. Also the gettimeofday function itself may take\n    longer to run.\n- If no timers are used, gettimeofday and time functions\n    return -1 and set errno to ENOSYS; they are defined as weak,\n    so they could be overridden.\n    If you want to customize gettimeofday() and other time functions,\n    please choose this option and refer to the 'time.c' source file\n    for the exact prototypes of these functions.\n\n- When RTC is used for timekeeping, two RTC_STORE registers are\n    used to keep time in deep sleep mode.",
+                        "id": "component-config-newlib-timers-used-for-gettimeofday-function",
+                        "name": "NEWLIB_TIME_SYSCALL",
+                        "title": "Timers used for gettimeofday function",
+                        "type": "choice"
+                    }
+                ],
+                "depends_on": null,
+                "id": "component-config-newlib",
+                "title": "Newlib",
+                "type": "menu"
+            },
+            {
+                "children": [],
+                "depends_on": null,
+                "help": null,
+                "id": "STDATOMIC_S32C1I_SPIRAM_WORKAROUND",
+                "name": "STDATOMIC_S32C1I_SPIRAM_WORKAROUND",
+                "range": null,
+                "title": null,
+                "type": "bool"
+            },
+            {
+                "children": [
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "SOC_MMU_PAGE_SIZE_8KB_SUPPORTED",
+                                "help": null,
+                                "id": "MMU_PAGE_SIZE_8KB",
+                                "name": "MMU_PAGE_SIZE_8KB",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "MMU_PAGE_SIZE_16KB",
+                                "name": "MMU_PAGE_SIZE_16KB",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "MMU_PAGE_SIZE_32KB",
+                                "name": "MMU_PAGE_SIZE_32KB",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "MMU_PAGE_SIZE_64KB",
+                                "name": "MMU_PAGE_SIZE_64KB",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "MMU_PAGE_MODE",
+                                "name": "MMU_PAGE_MODE",
+                                "range": null,
+                                "title": null,
+                                "type": "string"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": null,
+                                "help": null,
+                                "id": "MMU_PAGE_SIZE",
+                                "name": "MMU_PAGE_SIZE",
+                                "range": null,
+                                "title": null,
+                                "type": "hex"
+                            }
+                        ],
+                        "depends_on": null,
+                        "id": "component-config-soc-settings-mmu-config",
+                        "title": "MMU Config",
+                        "type": "menu"
+                    }
+                ],
+                "depends_on": null,
+                "id": "component-config-soc-settings",
+                "title": "SoC Settings",
+                "type": "menu"
+            },
+            {
+                "children": [
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": "When this option is selected, the patch will be enabled for XMC.\nFollow the recommended flow by XMC for better stability.\n\nDO NOT DISABLE UNLESS YOU KNOW WHAT YOU ARE DOING.",
+                                "id": "SPI_FLASH_BROWNOUT_RESET_XMC",
+                                "name": "SPI_FLASH_BROWNOUT_RESET_XMC",
+                                "range": null,
+                                "title": "Enable sending reset when brownout for XMC flash chips",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": "When brownout happens during flash erase/write operations,\nsend reset command to stop the flash operations to improve stability.",
+                                "id": "SPI_FLASH_BROWNOUT_RESET",
+                                "name": "SPI_FLASH_BROWNOUT_RESET",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                        "id": "component-config-main-flash-configuration-spi-flash-behavior-when-brownout",
+                        "title": "SPI Flash behavior when brownout",
+                        "type": "menu"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": "This is a helper config for HPM. Invisible for users.",
+                                "id": "SPI_FLASH_UNDER_HIGH_FREQ",
+                                "name": "SPI_FLASH_UNDER_HIGH_FREQ",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice SPI_FLASH_HPM>",
+                                        "help": null,
+                                        "id": "SPI_FLASH_HPM_ENA",
+                                        "name": "SPI_FLASH_HPM_ENA",
+                                        "range": null,
+                                        "title": "Enable",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice SPI_FLASH_HPM>",
+                                        "help": null,
+                                        "id": "SPI_FLASH_HPM_AUTO",
+                                        "name": "SPI_FLASH_HPM_AUTO",
+                                        "range": null,
+                                        "title": "Auto (Not recommended)",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice SPI_FLASH_HPM>",
+                                        "help": null,
+                                        "id": "SPI_FLASH_HPM_DIS",
+                                        "name": "SPI_FLASH_HPM_DIS",
+                                        "range": null,
+                                        "title": "Disabled",
+                                        "type": "bool"
+                                    }
+                                ],
+                                "depends_on": "IDF_TARGET_ESP32S3 && !ESPTOOLPY_OCT_FLASH && !APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": "Whether the High Performance Mode of Flash is enabled. As an optional feature, user needs to manually\nenable this option as a confirmation. To be back-compatible with earlier IDF version, this option is\nautomatically enabled with warning when Flash running > 80Mhz.",
+                                "id": "component-config-main-flash-configuration-optional-and-experimental-features-read-docs-first--high-performance-mode-read-docs-first-80mhz-",
+                                "name": "SPI_FLASH_HPM",
+                                "title": "High Performance Mode (READ DOCS FIRST, > 80MHz)",
+                                "type": "choice"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": "This option is invisible, and will be selected automatically\nwhen ``ESPTOOLPY_FLASHFREQ_120M`` is selected.",
+                                "id": "SPI_FLASH_HPM_ON",
+                                "name": "SPI_FLASH_HPM_ON",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice SPI_FLASH_HPM_DC>",
+                                        "help": null,
+                                        "id": "SPI_FLASH_HPM_DC_AUTO",
+                                        "name": "SPI_FLASH_HPM_DC_AUTO",
+                                        "range": null,
+                                        "title": "Auto (Enable when bootloader support enabled (BOOTLOADER_FLASH_DC_AWARE))",
+                                        "type": "bool"
+                                    },
+                                    {
+                                        "children": [],
+                                        "depends_on": "<choice SPI_FLASH_HPM_DC>",
+                                        "help": null,
+                                        "id": "SPI_FLASH_HPM_DC_DISABLE",
+                                        "name": "SPI_FLASH_HPM_DC_DISABLE",
+                                        "range": null,
+                                        "title": "Disable (READ DOCS FIRST)",
+                                        "type": "bool"
+                                    }
+                                ],
+                                "depends_on": "SPI_FLASH_HPM_ON && !APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": "This feature needs your bootloader to be compiled DC-aware (BOOTLOADER_FLASH_DC_AWARE=y). Otherwise the\nchip will not be able to boot after a reset.",
+                                "id": "component-config-main-flash-configuration-optional-and-experimental-features-read-docs-first--support-hpm-using-dc-read-docs-first-",
+                                "name": "SPI_FLASH_HPM_DC",
+                                "title": "Support HPM using DC (READ DOCS FIRST)",
+                                "type": "choice"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": "This is a helper config for HPM. Whether HPM-DC is enabled is also determined by bootloader.\nInvisible for users.",
+                                "id": "SPI_FLASH_HPM_DC_ON",
+                                "name": "SPI_FLASH_HPM_DC_ON",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND && !SPI_FLASH_ROM_IMPL && !APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": "This option is disabled by default because it is supported only\nfor specific flash chips and for specific Espressif chips.\nTo evaluate if you can use this feature refer to\n`Optional Features for Flash` > `Auto Suspend & Resume` of the `ESP-IDF Programming Guide`.\n\nCAUTION: If you want to OTA to an app with this feature turned on, please make\nsure the bootloader has the support for it. (later than IDF v4.3)\n\nIf you are using an official Espressif module, please contact Espressif Business support\nto check if the module has the flash that support this feature installed.\nAlso refer to `Concurrency Constraints for Flash on SPI1` > `Flash Auto Suspend Feature`\nbefore enabling this option.",
+                                "id": "SPI_FLASH_AUTO_SUSPEND",
+                                "name": "SPI_FLASH_AUTO_SUSPEND",
+                                "range": null,
+                                "title": "Auto suspend long erase/write operations (READ DOCS FIRST)",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": "This config is used for setting Tsus parameter. Tsus means CS# high to next command after\nsuspend. You can refer to the chapter of AC CHARACTERISTICS of flash datasheet.",
+                                "id": "SPI_FLASH_SUSPEND_TSUS_VAL_US",
+                                "name": "SPI_FLASH_SUSPEND_TSUS_VAL_US",
+                                "range": [
+                                    20,
+                                    100
+                                ],
+                                "title": "SPI flash tSUS value (refer to chapter AC CHARACTERISTICS)",
+                                "type": "int"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": "XMC-C series is regarded as not qualified for the Suspend feature, since its specification\nhas a tRS >= 1ms restriction. We strongly do not suggest using it for the Suspend feature.\nHowever, if your product in field has enabled this feature, you may still enable this\nconfig option to keep the legacy behavior.\n\nFor new users, DO NOT enable this config.",
+                                "id": "SPI_FLASH_FORCE_ENABLE_XMC_C_SUSPEND",
+                                "name": "SPI_FLASH_FORCE_ENABLE_XMC_C_SUSPEND",
+                                "range": null,
+                                "title": "Enable XMC-C series flash chip suspend feature anyway",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "SPI_FLASH_AUTO_SUSPEND && FREERTOS_UNICORE && IDF_EXPERIMENTAL_FEATURES && !APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": "Enable this config will disable auto-resume from hardware. Thus the software will resume the chip\nafter any higher priority task/interrupt which suspend the chip. The benefit is that the suspend-resume\nwill not disturb the higher priority task and interrupt.\n\nThis currently is only valid on single core chip.",
+                                "id": "SPI_FLASH_SOFTWARE_RESUME",
+                                "name": "SPI_FLASH_SOFTWARE_RESUME",
+                                "range": null,
+                                "title": "Resume flash program/erase form suspend state by software control",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "SPI_FLASH_AUTO_SUSPEND && FREERTOS_UNICORE && !APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": "Disable freertos task scheduler when CONFIG_SPI_FLASH_AUTO_SUSPEND is enabled.\nThus only interrupt can trigger a suspend. When SPI_FLASH_AUTO_SUSPEND is enabled,\ndefault behavior is not disable the task scheduler, so both interrupt and high priority\ntask can suspend the erase/program operation. When this option is enabled, task\nscheduler is disabled, only interrupt can suspend erase/program operation.",
+                                "id": "SPI_FLASH_DISABLE_SCHEDULER_IN_SUSPEND",
+                                "name": "SPI_FLASH_DISABLE_SCHEDULER_IN_SUSPEND",
+                                "range": null,
+                                "title": "Disable task scheduler when suspend is enabled when SPI1 operation is ongoing",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "SPI_FLASH_AUTO_SUSPEND && !APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": "Majority flash supports to use flash register to judge if flash suspend status is\ndone or not. So enable this config, the behavior would use flash register WIP bit to judge\nwhether suspend is valid instead of waiting for a specific long time, which can save a\nlot of time and benefit for performance improvement.",
+                                "id": "SPI_FLASH_AUTO_CHECK_SUSPEND_STATUS",
+                                "name": "SPI_FLASH_AUTO_CHECK_SUSPEND_STATUS",
+                                "range": null,
+                                "title": "Check flash status automatically after flash suspend",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                        "id": "component-config-main-flash-configuration-optional-and-experimental-features-read-docs-first-",
+                        "title": "Optional and Experimental Features (READ DOCS FIRST)",
+                        "type": "menu"
+                    }
+                ],
+                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                "id": "component-config-main-flash-configuration",
+                "title": "Main Flash configuration",
+                "type": "menu"
+            },
+            {
+                "children": [
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "SPI_FLASH_VERIFY_WRITE && !APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": "If this option is enabled, if SPI flash write verification fails then a log error line\nwill be written with the address, expected & actual values. This can be useful when\ndebugging hardware SPI flash problems.",
+                                "id": "SPI_FLASH_LOG_FAILED_WRITE",
+                                "name": "SPI_FLASH_LOG_FAILED_WRITE",
+                                "range": null,
+                                "title": "Log errors if verification fails",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "SPI_FLASH_VERIFY_WRITE && !APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": "If this option is enabled, any SPI flash write which tries to set zero bits in the flash to\nones will log a warning. Such writes will not result in the requested data appearing identically\nin flash once written, as SPI NOR flash can only set bits to one when an entire sector is erased.\nAfter erasing, individual bits can only be written from one to zero.\n\nNote that some software (such as SPIFFS) which is aware of SPI NOR flash may write one bits as an\noptimisation, relying on the data in flash becoming a bitwise AND of the new data and any existing data.\nSuch software will log spurious warnings if this option is enabled.",
+                                "id": "SPI_FLASH_WARN_SETTING_ZERO_TO_ONE",
+                                "name": "SPI_FLASH_WARN_SETTING_ZERO_TO_ONE",
+                                "range": null,
+                                "title": "Log warning if writing zero bits to ones",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": "!SPI_FLASH_ROM_IMPL && !APP_BUILD_TYPE_PURE_RAM_APP",
+                        "help": "If this option is enabled, any time SPI flash is written then the data will be read\nback and verified. This can catch hardware problems with SPI flash, or flash which\nwas not erased before verification.",
+                        "id": "SPI_FLASH_VERIFY_WRITE",
+                        "name": "SPI_FLASH_VERIFY_WRITE",
+                        "range": null,
+                        "title": "Verify SPI flash writes",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                        "help": "This option enables the following APIs:\n\n- esp_flash_reset_counters\n- esp_flash_dump_counters\n- esp_flash_get_counters\n\nThese APIs may be used to collect performance data for spi_flash APIs\nand to help understand behaviour of libraries which use SPI flash.",
+                        "id": "SPI_FLASH_ENABLE_COUNTERS",
+                        "name": "SPI_FLASH_ENABLE_COUNTERS",
+                        "range": null,
+                        "title": "Enable operation counters",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                        "help": "Enable this flag to use patched versions of SPI flash ROM driver functions.\nThis option should be enabled, if any one of the following is true: (1) need to write\nto flash on ESP32-D2WD; (2) main SPI flash is connected to non-default pins; (3) main\nSPI flash chip is manufactured by ISSI.",
+                        "id": "SPI_FLASH_ROM_DRIVER_PATCH",
+                        "name": "SPI_FLASH_ROM_DRIVER_PATCH",
+                        "range": null,
+                        "title": "Enable SPI flash ROM driver patched functions",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "ESP_ROM_HAS_SPI_FLASH && !APP_BUILD_TYPE_PURE_RAM_APP",
+                        "help": "Enable this flag to use new SPI flash driver functions from ROM instead of ESP-IDF.\n\nIf keeping this as \"n\" in your project, you will have less free IRAM.\nBut you can use all of our flash features.\n\nIf making this as \"y\" in your project, you will increase free IRAM.\nBut you may miss out on some flash features and support for new flash chips.\n\nCurrently the ROM cannot support the following features:\n\n- SPI_FLASH_AUTO_SUSPEND (C3, S3)",
+                        "id": "SPI_FLASH_ROM_IMPL",
+                        "name": "SPI_FLASH_ROM_IMPL",
+                        "range": null,
+                        "title": "Use esp_flash implementation in ROM",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "<choice SPI_FLASH_DANGEROUS_WRITE>",
+                                "help": null,
+                                "id": "SPI_FLASH_DANGEROUS_WRITE_ABORTS",
+                                "name": "SPI_FLASH_DANGEROUS_WRITE_ABORTS",
+                                "range": null,
+                                "title": "Aborts",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice SPI_FLASH_DANGEROUS_WRITE>",
+                                "help": null,
+                                "id": "SPI_FLASH_DANGEROUS_WRITE_FAILS",
+                                "name": "SPI_FLASH_DANGEROUS_WRITE_FAILS",
+                                "range": null,
+                                "title": "Fails",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "<choice SPI_FLASH_DANGEROUS_WRITE>",
+                                "help": null,
+                                "id": "SPI_FLASH_DANGEROUS_WRITE_ALLOWED",
+                                "name": "SPI_FLASH_DANGEROUS_WRITE_ALLOWED",
+                                "range": null,
+                                "title": "Allowed",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                        "help": "SPI flash APIs can optionally abort or return a failure code\nif erasing or writing addresses that fall at the beginning\nof flash (covering the bootloader and partition table) or that\noverlap the app partition that contains the running app.\n\nIt is not recommended to ever write to these regions from an IDF app,\nand this check prevents logic errors or corrupted firmware memory from\ndamaging these regions.\n\nNote that this feature *does not* check calls to the esp_rom_xxx SPI flash\nROM functions. These functions should not be called directly from IDF\napplications.",
+                        "id": "component-config-spi-flash-driver-writing-to-dangerous-flash-regions",
+                        "name": "SPI_FLASH_DANGEROUS_WRITE",
+                        "title": "Writing to dangerous flash regions",
+                        "type": "choice"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "IDF_TARGET_ESP32 && !APP_BUILD_TYPE_PURE_RAM_APP",
+                        "help": "Each SPI bus needs a lock for arbitration among devices. This allows multiple\ndevices on a same bus, but may reduce the speed of esp_flash driver access to the\nmain flash chip.\n\nIf you only need to use esp_flash driver to access the main flash chip, disable\nthis option, and the lock will be bypassed on SPI1 bus. Otherwise if extra devices\nare needed to attach to SPI1 bus, enable this option.",
+                        "id": "SPI_FLASH_SHARE_SPI1_BUS",
+                        "name": "SPI_FLASH_SHARE_SPI1_BUS",
+                        "range": null,
+                        "title": "Support other devices attached to SPI1 bus",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                        "help": "Some flash chips can have very high \"max\" erase times, especially for block erase (32KB or 64KB).\nThis option allows to bypass \"block erase\" and always do sector erase commands.\nThis will be much slower overall in most cases, but improves latency for other code to run.",
+                        "id": "SPI_FLASH_BYPASS_BLOCK_ERASE",
+                        "name": "SPI_FLASH_BYPASS_BLOCK_ERASE",
+                        "range": null,
+                        "title": "Bypass a block erase and always do sector erase",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "SPI_FLASH_YIELD_DURING_ERASE && !APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": "If a duration of one erase command is large\nthen it will yield CPUs after finishing a current command.",
+                                "id": "SPI_FLASH_ERASE_YIELD_DURATION_MS",
+                                "name": "SPI_FLASH_ERASE_YIELD_DURATION_MS",
+                                "range": null,
+                                "title": "Duration of erasing to yield CPUs (ms)",
+                                "type": "int"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "SPI_FLASH_YIELD_DURING_ERASE && !APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": "Defines how many ticks will be before returning to continue a erasing.",
+                                "id": "SPI_FLASH_ERASE_YIELD_TICKS",
+                                "name": "SPI_FLASH_ERASE_YIELD_TICKS",
+                                "range": null,
+                                "title": "CPU release time (tick) for an erase operation",
+                                "type": "int"
+                            }
+                        ],
+                        "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                        "help": "This allows to yield the CPUs between erase commands.\nPrevents starvation of other tasks.\nPlease use this configuration together with ``SPI_FLASH_ERASE_YIELD_DURATION_MS`` and\n``SPI_FLASH_ERASE_YIELD_TICKS`` after carefully checking flash datasheet to avoid a\nwatchdog timeout.\nFor more information, please check `SPI Flash API` reference documentation\nunder section `OS Function`.",
+                        "id": "SPI_FLASH_YIELD_DURING_ERASE",
+                        "name": "SPI_FLASH_YIELD_DURING_ERASE",
+                        "range": null,
+                        "title": "Enables yield operation during flash erase",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                        "help": "Flash write is broken down in terms of multiple (smaller) write operations.\nThis configuration options helps to set individual write chunk size, smaller\nvalue here ensures that cache (and non-IRAM resident interrupts) remains\ndisabled for shorter duration.",
+                        "id": "SPI_FLASH_WRITE_CHUNK_SIZE",
+                        "name": "SPI_FLASH_WRITE_CHUNK_SIZE",
+                        "range": [
+                            256,
+                            8192
+                        ],
+                        "title": "Flash write chunk size",
+                        "type": "int"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                        "help": "SPI Flash driver uses the flash size configured in bootloader header by default.\nEnable this option to override flash size with latest ESPTOOLPY_FLASHSIZE value from\nthe app header if the size in the bootloader header is incorrect.",
+                        "id": "SPI_FLASH_SIZE_OVERRIDE",
+                        "name": "SPI_FLASH_SIZE_OVERRIDE",
+                        "range": null,
+                        "title": "Override flash size in bootloader header by ESPTOOLPY_FLASHSIZE",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                        "help": "This option is helpful if you are using a flash chip whose timeout is quite large or unpredictable.",
+                        "id": "SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED",
+                        "name": "SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED",
+                        "range": null,
+                        "title": "Flash timeout checkout disabled",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                        "help": "This option allows the chip driver list to be customized, instead of using the default list provided by\nESP-IDF.\n\nWhen this option is enabled, the default list is no longer compiled or linked. Instead, the\n`default_registered_chips` structure must be provided by the user.\n\nSee example: custom_chip_driver under examples/storage for more details.",
+                        "id": "SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST",
+                        "name": "SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST",
+                        "range": null,
+                        "title": "Override default chip driver list",
+                        "type": "bool"
+                    },
+                    {
+                        "children": [
+                            {
+                                "children": [],
+                                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": null,
+                                "id": "SPI_FLASH_VENDOR_XMC_SUPPORTED",
+                                "name": "SPI_FLASH_VENDOR_XMC_SUPPORTED",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": null,
+                                "id": "SPI_FLASH_VENDOR_GD_SUPPORTED",
+                                "name": "SPI_FLASH_VENDOR_GD_SUPPORTED",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": null,
+                                "id": "SPI_FLASH_VENDOR_ISSI_SUPPORTED",
+                                "name": "SPI_FLASH_VENDOR_ISSI_SUPPORTED",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": null,
+                                "id": "SPI_FLASH_VENDOR_MXIC_SUPPORTED",
+                                "name": "SPI_FLASH_VENDOR_MXIC_SUPPORTED",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": null,
+                                "id": "SPI_FLASH_VENDOR_WINBOND_SUPPORTED",
+                                "name": "SPI_FLASH_VENDOR_WINBOND_SUPPORTED",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": null,
+                                "id": "SPI_FLASH_VENDOR_BOYA_SUPPORTED",
+                                "name": "SPI_FLASH_VENDOR_BOYA_SUPPORTED",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": null,
+                                "id": "SPI_FLASH_VENDOR_TH_SUPPORTED",
+                                "name": "SPI_FLASH_VENDOR_TH_SUPPORTED",
+                                "range": null,
+                                "title": null,
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": "Enable this to support auto detection of ISSI chips if chip vendor not directly\ngiven by ``chip_drv`` member of the chip struct. This adds support for variant\nchips, however will extend detecting time.",
+                                "id": "SPI_FLASH_SUPPORT_ISSI_CHIP",
+                                "name": "SPI_FLASH_SUPPORT_ISSI_CHIP",
+                                "range": null,
+                                "title": "ISSI",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": "Enable this to support auto detection of MXIC chips if chip vendor not directly\ngiven by ``chip_drv`` member of the chip struct. This adds support for variant\nchips, however will extend detecting time.",
+                                "id": "SPI_FLASH_SUPPORT_MXIC_CHIP",
+                                "name": "SPI_FLASH_SUPPORT_MXIC_CHIP",
+                                "range": null,
+                                "title": "MXIC",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": "Enable this to support auto detection of GD (GigaDevice) chips if chip vendor not\ndirectly given by ``chip_drv`` member of the chip struct. If you are using Wrover\nmodules, please don't disable this, otherwise your flash may not work in 4-bit\nmode.\n\nThis adds support for variant chips, however will extend detecting time and image\nsize. Note that the default chip driver supports the GD chips with product ID\n60H.",
+                                "id": "SPI_FLASH_SUPPORT_GD_CHIP",
+                                "name": "SPI_FLASH_SUPPORT_GD_CHIP",
+                                "range": null,
+                                "title": "GigaDevice",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": "Enable this to support auto detection of Winbond chips if chip vendor not directly\ngiven by ``chip_drv`` member of the chip struct. This adds support for variant\nchips, however will extend detecting time.",
+                                "id": "SPI_FLASH_SUPPORT_WINBOND_CHIP",
+                                "name": "SPI_FLASH_SUPPORT_WINBOND_CHIP",
+                                "range": null,
+                                "title": "Winbond",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": "Enable this to support auto detection of BOYA chips if chip vendor not directly\ngiven by ``chip_drv`` member of the chip struct. This adds support for variant\nchips, however will extend detecting time.",
+                                "id": "SPI_FLASH_SUPPORT_BOYA_CHIP",
+                                "name": "SPI_FLASH_SUPPORT_BOYA_CHIP",
+                                "range": null,
+                                "title": "BOYA",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": "Enable this to support auto detection of TH chips if chip vendor not directly\ngiven by ``chip_drv`` member of the chip struct. This adds support for variant\nchips, however will extend detecting time.",
+                                "id": "SPI_FLASH_SUPPORT_TH_CHIP",
+                                "name": "SPI_FLASH_SUPPORT_TH_CHIP",
+                                "range": null,
+                                "title": "TH",
+                                "type": "bool"
+                            },
+                            {
+                                "children": [],
+                                "depends_on": "IDF_TARGET_ESP32S3 && !APP_BUILD_TYPE_PURE_RAM_APP",
+                                "help": "Enable this to support auto detection of Octal MXIC chips if chip vendor not directly\ngiven by ``chip_drv`` member of the chip struct. This adds support for variant\nchips, however will extend detecting time.",
+                                "id": "SPI_FLASH_SUPPORT_MXIC_OPI_CHIP",
+                                "name": "SPI_FLASH_SUPPORT_MXIC_OPI_CHIP",
+                                "range": null,
+                                "title": "mxic (opi)",
+                                "type": "bool"
+                            }
+                        ],
+                        "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                        "id": "component-config-spi-flash-driver-auto-detect-flash-chips",
+                        "title": "Auto-detect flash chips",
+                        "type": "menu"
+                    },
+                    {
+                        "children": [],
+                        "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                        "help": "This option enables flash read/write operations to encrypted partition/s. This option\nis kept enabled irrespective of state of flash encryption feature. However, in case\napplication is not using flash encryption feature and is in need of some additional\nmemory from IRAM region (~1KB) then this config can be disabled.",
+                        "id": "SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE",
+                        "name": "SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE",
+                        "range": null,
+                        "title": "Enable encrypted partition read/write operations",
+                        "type": "bool"
+                    }
+                ],
+                "depends_on": "!APP_BUILD_TYPE_PURE_RAM_APP",
+                "id": "component-config-spi-flash-driver",
+                "title": "SPI Flash driver",
+                "type": "menu"
+            }
+        ],
+        "depends_on": null,
+        "id": "component-config",
+        "title": "Component config",
+        "type": "menu"
+    },
+    {
+        "children": [],
+        "depends_on": null,
+        "help": "By enabling this option, ESP-IDF experimental feature options will be visible.\n\nNote you should still enable a certain experimental feature option to use it, and you\nshould read the corresponding risk warning and known issue list carefully.\n\nCurrent experimental feature list:\n\n- CONFIG_ESPTOOLPY_FLASHFREQ_120M && CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR\n- CONFIG_SPIRAM_SPEED_120M && CONFIG_SPIRAM_MODE_OCT\n- CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH\n- CONFIG_ESP_WIFI_EAP_TLS1_3\n- CONFIG_ESP_WIFI_ENABLE_ROAMING_APP\n- CONFIG_USB_HOST_EXT_PORT_SUPPORT_LS\n- CONFIG_USB_HOST_EXT_PORT_RESET_ATTEMPTS",
+        "id": "IDF_EXPERIMENTAL_FEATURES",
+        "name": "IDF_EXPERIMENTAL_FEATURES",
+        "range": null,
+        "title": "Make experimental features visible",
+        "type": "bool"
+    }
+]
\ No newline at end of file
diff --git a/ESP32-IDF_ESPNOW-Receiver/build/bootloader/config/sdkconfig.cmake b/ESP32-IDF_ESPNOW-Receiver/build/bootloader/config/sdkconfig.cmake
new file mode 100644
index 000000000..a1a64f08e
--- /dev/null
+++ b/ESP32-IDF_ESPNOW-Receiver/build/bootloader/config/sdkconfig.cmake
@@ -0,0 +1,754 @@
+#
+                # Automatically generated file. DO NOT EDIT.
+                # Espressif IoT Development Framework (ESP-IDF) Configuration cmake include file
+                #
+set(CONFIG_SOC_ADC_SUPPORTED "y")
+set(CONFIG_SOC_DEDICATED_GPIO_SUPPORTED "y")
+set(CONFIG_SOC_UART_SUPPORTED "y")
+set(CONFIG_SOC_GDMA_SUPPORTED "y")
+set(CONFIG_SOC_AHB_GDMA_SUPPORTED "y")
+set(CONFIG_SOC_GPTIMER_SUPPORTED "y")
+set(CONFIG_SOC_TWAI_SUPPORTED "y")
+set(CONFIG_SOC_BT_SUPPORTED "y")
+set(CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED "y")
+set(CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED "y")
+set(CONFIG_SOC_TEMP_SENSOR_SUPPORTED "y")
+set(CONFIG_SOC_XT_WDT_SUPPORTED "y")
+set(CONFIG_SOC_PHY_SUPPORTED "y")
+set(CONFIG_SOC_WIFI_SUPPORTED "y")
+set(CONFIG_SOC_SUPPORTS_SECURE_DL_MODE "y")
+set(CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD "y")
+set(CONFIG_SOC_EFUSE_HAS_EFUSE_RST_BUG "y")
+set(CONFIG_SOC_EFUSE_SUPPORTED "y")
+set(CONFIG_SOC_RTC_FAST_MEM_SUPPORTED "y")
+set(CONFIG_SOC_RTC_MEM_SUPPORTED "y")
+set(CONFIG_SOC_I2S_SUPPORTED "y")
+set(CONFIG_SOC_RMT_SUPPORTED "y")
+set(CONFIG_SOC_SDM_SUPPORTED "y")
+set(CONFIG_SOC_GPSPI_SUPPORTED "y")
+set(CONFIG_SOC_LEDC_SUPPORTED "y")
+set(CONFIG_SOC_I2C_SUPPORTED "y")
+set(CONFIG_SOC_SYSTIMER_SUPPORTED "y")
+set(CONFIG_SOC_SUPPORT_COEXISTENCE "y")
+set(CONFIG_SOC_AES_SUPPORTED "y")
+set(CONFIG_SOC_MPI_SUPPORTED "y")
+set(CONFIG_SOC_SHA_SUPPORTED "y")
+set(CONFIG_SOC_HMAC_SUPPORTED "y")
+set(CONFIG_SOC_DIG_SIGN_SUPPORTED "y")
+set(CONFIG_SOC_FLASH_ENC_SUPPORTED "y")
+set(CONFIG_SOC_SECURE_BOOT_SUPPORTED "y")
+set(CONFIG_SOC_MEMPROT_SUPPORTED "y")
+set(CONFIG_SOC_BOD_SUPPORTED "y")
+set(CONFIG_SOC_CLK_TREE_SUPPORTED "y")
+set(CONFIG_SOC_ASSIST_DEBUG_SUPPORTED "y")
+set(CONFIG_SOC_WDT_SUPPORTED "y")
+set(CONFIG_SOC_SPI_FLASH_SUPPORTED "y")
+set(CONFIG_SOC_RNG_SUPPORTED "y")
+set(CONFIG_SOC_LIGHT_SLEEP_SUPPORTED "y")
+set(CONFIG_SOC_DEEP_SLEEP_SUPPORTED "y")
+set(CONFIG_SOC_LP_PERIPH_SHARE_INTERRUPT "y")
+set(CONFIG_SOC_PM_SUPPORTED "y")
+set(CONFIG_SOC_XTAL_SUPPORT_40M "y")
+set(CONFIG_SOC_AES_SUPPORT_DMA "y")
+set(CONFIG_SOC_AES_GDMA "y")
+set(CONFIG_SOC_AES_SUPPORT_AES_128 "y")
+set(CONFIG_SOC_AES_SUPPORT_AES_256 "y")
+set(CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED "y")
+set(CONFIG_SOC_ADC_ARBITER_SUPPORTED "y")
+set(CONFIG_SOC_ADC_DIG_IIR_FILTER_SUPPORTED "y")
+set(CONFIG_SOC_ADC_MONITOR_SUPPORTED "y")
+set(CONFIG_SOC_ADC_DMA_SUPPORTED "y")
+set(CONFIG_SOC_ADC_PERIPH_NUM "2")
+set(CONFIG_SOC_ADC_MAX_CHANNEL_NUM "5")
+set(CONFIG_SOC_ADC_ATTEN_NUM "4")
+set(CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM "1")
+set(CONFIG_SOC_ADC_PATT_LEN_MAX "8")
+set(CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH "12")
+set(CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH "12")
+set(CONFIG_SOC_ADC_DIGI_RESULT_BYTES "4")
+set(CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV "4")
+set(CONFIG_SOC_ADC_DIGI_IIR_FILTER_NUM "2")
+set(CONFIG_SOC_ADC_DIGI_MONITOR_NUM "2")
+set(CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH "83333")
+set(CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW "611")
+set(CONFIG_SOC_ADC_RTC_MIN_BITWIDTH "12")
+set(CONFIG_SOC_ADC_RTC_MAX_BITWIDTH "12")
+set(CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED "y")
+set(CONFIG_SOC_ADC_SELF_HW_CALI_SUPPORTED "y")
+set(CONFIG_SOC_ADC_SHARED_POWER "y")
+set(CONFIG_SOC_APB_BACKUP_DMA "y")
+set(CONFIG_SOC_BROWNOUT_RESET_SUPPORTED "y")
+set(CONFIG_SOC_SHARED_IDCACHE_SUPPORTED "y")
+set(CONFIG_SOC_CACHE_MEMORY_IBANK_SIZE "0x4000")
+set(CONFIG_SOC_CPU_CORES_NUM "1")
+set(CONFIG_SOC_CPU_INTR_NUM "32")
+set(CONFIG_SOC_CPU_HAS_FLEXIBLE_INTC "y")
+set(CONFIG_SOC_CPU_HAS_CSR_PC "y")
+set(CONFIG_SOC_CPU_BREAKPOINTS_NUM "8")
+set(CONFIG_SOC_CPU_WATCHPOINTS_NUM "8")
+set(CONFIG_SOC_CPU_WATCHPOINT_MAX_REGION_SIZE "0x80000000")
+set(CONFIG_SOC_DS_SIGNATURE_MAX_BIT_LEN "3072")
+set(CONFIG_SOC_DS_KEY_PARAM_MD_IV_LENGTH "16")
+set(CONFIG_SOC_DS_KEY_CHECK_MAX_WAIT_US "1100")
+set(CONFIG_SOC_AHB_GDMA_VERSION "1")
+set(CONFIG_SOC_GDMA_NUM_GROUPS_MAX "1")
+set(CONFIG_SOC_GDMA_PAIRS_PER_GROUP_MAX "3")
+set(CONFIG_SOC_GPIO_PORT "1")
+set(CONFIG_SOC_GPIO_PIN_COUNT "22")
+set(CONFIG_SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER "y")
+set(CONFIG_SOC_GPIO_FILTER_CLK_SUPPORT_APB "y")
+set(CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD "y")
+set(CONFIG_SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP "y")
+set(CONFIG_SOC_GPIO_IN_RANGE_MAX "21")
+set(CONFIG_SOC_GPIO_OUT_RANGE_MAX "21")
+set(CONFIG_SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK "0")
+set(CONFIG_SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT "6")
+set(CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK "0x3fffc0")
+set(CONFIG_SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX "y")
+set(CONFIG_SOC_GPIO_CLOCKOUT_CHANNEL_NUM "3")
+set(CONFIG_SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP "y")
+set(CONFIG_SOC_DEDIC_GPIO_OUT_CHANNELS_NUM "8")
+set(CONFIG_SOC_DEDIC_GPIO_IN_CHANNELS_NUM "8")
+set(CONFIG_SOC_DEDIC_PERIPH_ALWAYS_ENABLE "y")
+set(CONFIG_SOC_I2C_NUM "1")
+set(CONFIG_SOC_HP_I2C_NUM "1")
+set(CONFIG_SOC_I2C_FIFO_LEN "32")
+set(CONFIG_SOC_I2C_CMD_REG_NUM "8")
+set(CONFIG_SOC_I2C_SUPPORT_SLAVE "y")
+set(CONFIG_SOC_I2C_SUPPORT_HW_CLR_BUS "y")
+set(CONFIG_SOC_I2C_SUPPORT_XTAL "y")
+set(CONFIG_SOC_I2C_SUPPORT_RTC "y")
+set(CONFIG_SOC_I2C_SUPPORT_10BIT_ADDR "y")
+set(CONFIG_SOC_I2C_SLAVE_SUPPORT_BROADCAST "y")
+set(CONFIG_SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE "y")
+set(CONFIG_SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS "y")
+set(CONFIG_SOC_I2S_NUM "1")
+set(CONFIG_SOC_I2S_HW_VERSION_2 "y")
+set(CONFIG_SOC_I2S_SUPPORTS_XTAL "y")
+set(CONFIG_SOC_I2S_SUPPORTS_PLL_F160M "y")
+set(CONFIG_SOC_I2S_SUPPORTS_PCM "y")
+set(CONFIG_SOC_I2S_SUPPORTS_PDM "y")
+set(CONFIG_SOC_I2S_SUPPORTS_PDM_TX "y")
+set(CONFIG_SOC_I2S_PDM_MAX_TX_LINES "2")
+set(CONFIG_SOC_I2S_SUPPORTS_TDM "y")
+set(CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK "y")
+set(CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK "y")
+set(CONFIG_SOC_LEDC_TIMER_NUM "4")
+set(CONFIG_SOC_LEDC_CHANNEL_NUM "6")
+set(CONFIG_SOC_LEDC_TIMER_BIT_WIDTH "14")
+set(CONFIG_SOC_LEDC_SUPPORT_FADE_STOP "y")
+set(CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM "1")
+set(CONFIG_SOC_MMU_PERIPH_NUM "1")
+set(CONFIG_SOC_MPU_MIN_REGION_SIZE "0x20000000")
+set(CONFIG_SOC_MPU_REGIONS_MAX_NUM "8")
+set(CONFIG_SOC_RMT_GROUPS "1")
+set(CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP "2")
+set(CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP "2")
+set(CONFIG_SOC_RMT_CHANNELS_PER_GROUP "4")
+set(CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL "48")
+set(CONFIG_SOC_RMT_SUPPORT_RX_PINGPONG "y")
+set(CONFIG_SOC_RMT_SUPPORT_RX_DEMODULATION "y")
+set(CONFIG_SOC_RMT_SUPPORT_TX_ASYNC_STOP "y")
+set(CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT "y")
+set(CONFIG_SOC_RMT_SUPPORT_TX_SYNCHRO "y")
+set(CONFIG_SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY "y")
+set(CONFIG_SOC_RMT_SUPPORT_XTAL "y")
+set(CONFIG_SOC_RMT_SUPPORT_APB "y")
+set(CONFIG_SOC_RMT_SUPPORT_RC_FAST "y")
+set(CONFIG_SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH "128")
+set(CONFIG_SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM "108")
+set(CONFIG_SOC_SLEEP_SYSTIMER_STALL_WORKAROUND "y")
+set(CONFIG_SOC_SLEEP_TGWDT_STOP_WORKAROUND "y")
+set(CONFIG_SOC_RTCIO_PIN_COUNT "0")
+set(CONFIG_SOC_MPI_MEM_BLOCKS_NUM "4")
+set(CONFIG_SOC_MPI_OPERATIONS_NUM "3")
+set(CONFIG_SOC_RSA_MAX_BIT_LEN "3072")
+set(CONFIG_SOC_SHA_DMA_MAX_BUFFER_SIZE "3968")
+set(CONFIG_SOC_SHA_SUPPORT_DMA "y")
+set(CONFIG_SOC_SHA_SUPPORT_RESUME "y")
+set(CONFIG_SOC_SHA_GDMA "y")
+set(CONFIG_SOC_SHA_SUPPORT_SHA1 "y")
+set(CONFIG_SOC_SHA_SUPPORT_SHA224 "y")
+set(CONFIG_SOC_SHA_SUPPORT_SHA256 "y")
+set(CONFIG_SOC_SDM_GROUPS "1")
+set(CONFIG_SOC_SDM_CHANNELS_PER_GROUP "4")
+set(CONFIG_SOC_SDM_CLK_SUPPORT_APB "y")
+set(CONFIG_SOC_SPI_PERIPH_NUM "2")
+set(CONFIG_SOC_SPI_MAX_CS_NUM "6")
+set(CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE "64")
+set(CONFIG_SOC_SPI_SUPPORT_DDRCLK "y")
+set(CONFIG_SOC_SPI_SLAVE_SUPPORT_SEG_TRANS "y")
+set(CONFIG_SOC_SPI_SUPPORT_CD_SIG "y")
+set(CONFIG_SOC_SPI_SUPPORT_CONTINUOUS_TRANS "y")
+set(CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2 "y")
+set(CONFIG_SOC_SPI_SUPPORT_CLK_APB "y")
+set(CONFIG_SOC_SPI_SUPPORT_CLK_XTAL "y")
+set(CONFIG_SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT "y")
+set(CONFIG_SOC_SPI_SCT_SUPPORTED "y")
+set(CONFIG_SOC_SPI_SCT_REG_NUM "14")
+set(CONFIG_SOC_SPI_SCT_BUFFER_NUM_MAX "y")
+set(CONFIG_SOC_SPI_SCT_CONF_BITLEN_MAX "0x3fffa")
+set(CONFIG_SOC_MEMSPI_IS_INDEPENDENT "y")
+set(CONFIG_SOC_SPI_MAX_PRE_DIVIDER "16")
+set(CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE "y")
+set(CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND "y")
+set(CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_RESUME "y")
+set(CONFIG_SOC_SPI_MEM_SUPPORT_IDLE_INTR "y")
+set(CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND "y")
+set(CONFIG_SOC_SPI_MEM_SUPPORT_CHECK_SUS "y")
+set(CONFIG_SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE "y")
+set(CONFIG_SOC_SPI_MEM_SUPPORT_WRAP "y")
+set(CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED "y")
+set(CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED "y")
+set(CONFIG_SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED "y")
+set(CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED "y")
+set(CONFIG_SOC_SYSTIMER_COUNTER_NUM "2")
+set(CONFIG_SOC_SYSTIMER_ALARM_NUM "3")
+set(CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO "32")
+set(CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI "20")
+set(CONFIG_SOC_SYSTIMER_FIXED_DIVIDER "y")
+set(CONFIG_SOC_SYSTIMER_INT_LEVEL "y")
+set(CONFIG_SOC_SYSTIMER_ALARM_MISS_COMPENSATE "y")
+set(CONFIG_SOC_TIMER_GROUPS "2")
+set(CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP "1")
+set(CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH "54")
+set(CONFIG_SOC_TIMER_GROUP_SUPPORT_XTAL "y")
+set(CONFIG_SOC_TIMER_GROUP_SUPPORT_APB "y")
+set(CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS "2")
+set(CONFIG_SOC_LP_TIMER_BIT_WIDTH_LO "32")
+set(CONFIG_SOC_LP_TIMER_BIT_WIDTH_HI "16")
+set(CONFIG_SOC_MWDT_SUPPORT_XTAL "y")
+set(CONFIG_SOC_TWAI_CONTROLLER_NUM "1")
+set(CONFIG_SOC_TWAI_CLK_SUPPORT_APB "y")
+set(CONFIG_SOC_TWAI_BRP_MIN "2")
+set(CONFIG_SOC_TWAI_BRP_MAX "16384")
+set(CONFIG_SOC_TWAI_SUPPORTS_RX_STATUS "y")
+set(CONFIG_SOC_EFUSE_DIS_DOWNLOAD_ICACHE "y")
+set(CONFIG_SOC_EFUSE_DIS_PAD_JTAG "y")
+set(CONFIG_SOC_EFUSE_DIS_USB_JTAG "y")
+set(CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT "y")
+set(CONFIG_SOC_EFUSE_SOFT_DIS_JTAG "y")
+set(CONFIG_SOC_EFUSE_DIS_ICACHE "y")
+set(CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK "y")
+set(CONFIG_SOC_SECURE_BOOT_V2_RSA "y")
+set(CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS "3")
+set(CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS "y")
+set(CONFIG_SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY "y")
+set(CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX "32")
+set(CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES "y")
+set(CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128 "y")
+set(CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE "16")
+set(CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE "512")
+set(CONFIG_SOC_UART_NUM "2")
+set(CONFIG_SOC_UART_HP_NUM "2")
+set(CONFIG_SOC_UART_FIFO_LEN "128")
+set(CONFIG_SOC_UART_BITRATE_MAX "5000000")
+set(CONFIG_SOC_UART_SUPPORT_APB_CLK "y")
+set(CONFIG_SOC_UART_SUPPORT_RTC_CLK "y")
+set(CONFIG_SOC_UART_SUPPORT_XTAL_CLK "y")
+set(CONFIG_SOC_UART_SUPPORT_WAKEUP_INT "y")
+set(CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND "y")
+set(CONFIG_SOC_COEX_HW_PTI "y")
+set(CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE "21")
+set(CONFIG_SOC_MAC_BB_PD_MEM_SIZE "192")
+set(CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH "12")
+set(CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP "y")
+set(CONFIG_SOC_PM_SUPPORT_BT_WAKEUP "y")
+set(CONFIG_SOC_PM_SUPPORT_CPU_PD "y")
+set(CONFIG_SOC_PM_SUPPORT_WIFI_PD "y")
+set(CONFIG_SOC_PM_SUPPORT_BT_PD "y")
+set(CONFIG_SOC_PM_SUPPORT_RC_FAST_PD "y")
+set(CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD "y")
+set(CONFIG_SOC_PM_SUPPORT_MAC_BB_PD "y")
+set(CONFIG_SOC_PM_CPU_RETENTION_BY_RTCCNTL "y")
+set(CONFIG_SOC_PM_MODEM_RETENTION_BY_BACKUPDMA "y")
+set(CONFIG_SOC_PM_MODEM_PD_BY_SW "y")
+set(CONFIG_SOC_CLK_RC_FAST_D256_SUPPORTED "y")
+set(CONFIG_SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256 "y")
+set(CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION "y")
+set(CONFIG_SOC_CLK_XTAL32K_SUPPORTED "y")
+set(CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC "y")
+set(CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL "y")
+set(CONFIG_SOC_WIFI_HW_TSF "y")
+set(CONFIG_SOC_WIFI_FTM_SUPPORT "y")
+set(CONFIG_SOC_WIFI_GCMP_SUPPORT "y")
+set(CONFIG_SOC_WIFI_WAPI_SUPPORT "y")
+set(CONFIG_SOC_WIFI_CSI_SUPPORT "y")
+set(CONFIG_SOC_WIFI_MESH_SUPPORT "y")
+set(CONFIG_SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW "y")
+set(CONFIG_SOC_WIFI_PHY_NEEDS_USB_WORKAROUND "y")
+set(CONFIG_SOC_BLE_SUPPORTED "y")
+set(CONFIG_SOC_BLE_MESH_SUPPORTED "y")
+set(CONFIG_SOC_BLE_50_SUPPORTED "y")
+set(CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED "y")
+set(CONFIG_SOC_BLUFI_SUPPORTED "y")
+set(CONFIG_SOC_PHY_COMBO_MODULE "y")
+set(CONFIG_IDF_CMAKE "y")
+set(CONFIG_IDF_TOOLCHAIN "gcc")
+set(CONFIG_IDF_TOOLCHAIN_GCC "y")
+set(CONFIG_IDF_TARGET_ARCH_RISCV "y")
+set(CONFIG_IDF_TARGET_ARCH "riscv")
+set(CONFIG_IDF_TARGET "esp32c3")
+set(CONFIG_IDF_INIT_VERSION "5.4.1")
+set(CONFIG_IDF_TARGET_ESP32C3 "y")
+set(CONFIG_IDF_FIRMWARE_CHIP_ID "0x5")
+set(CONFIG_APP_BUILD_TYPE_APP_2NDBOOT "y")
+set(CONFIG_APP_BUILD_TYPE_RAM "")
+set(CONFIG_APP_BUILD_GENERATE_BINARIES "y")
+set(CONFIG_APP_BUILD_BOOTLOADER "y")
+set(CONFIG_APP_BUILD_USE_FLASH_SECTIONS "y")
+set(CONFIG_APP_REPRODUCIBLE_BUILD "")
+set(CONFIG_APP_NO_BLOBS "")
+set(CONFIG_BOOTLOADER_COMPILE_TIME_DATE "y")
+set(CONFIG_BOOTLOADER_PROJECT_VER "1")
+set(CONFIG_BOOTLOADER_OFFSET_IN_FLASH "0x0")
+set(CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE "y")
+set(CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG "")
+set(CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF "")
+set(CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_NONE "")
+set(CONFIG_BOOTLOADER_LOG_LEVEL_NONE "")
+set(CONFIG_BOOTLOADER_LOG_LEVEL_ERROR "")
+set(CONFIG_BOOTLOADER_LOG_LEVEL_WARN "")
+set(CONFIG_BOOTLOADER_LOG_LEVEL_INFO "y")
+set(CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG "")
+set(CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE "")
+set(CONFIG_BOOTLOADER_LOG_LEVEL "3")
+set(CONFIG_BOOTLOADER_LOG_COLORS "")
+set(CONFIG_BOOTLOADER_LOG_TIMESTAMP_SOURCE_CPU_TICKS "y")
+set(CONFIG_BOOTLOADER_FLASH_DC_AWARE "")
+set(CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT "y")
+set(CONFIG_BOOTLOADER_FACTORY_RESET "")
+set(CONFIG_BOOTLOADER_APP_TEST "")
+set(CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE "y")
+set(CONFIG_BOOTLOADER_WDT_ENABLE "y")
+set(CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE "")
+set(CONFIG_BOOTLOADER_WDT_TIME_MS "9000")
+set(CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE "")
+set(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP "")
+set(CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON "")
+set(CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS "")
+set(CONFIG_BOOTLOADER_RESERVE_RTC_SIZE "0x0")
+set(CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC "")
+set(CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED "y")
+set(CONFIG_SECURE_BOOT_V2_PREFERRED "y")
+set(CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT "")
+set(CONFIG_SECURE_BOOT "")
+set(CONFIG_SECURE_FLASH_ENC_ENABLED "")
+set(CONFIG_SECURE_ROM_DL_MODE_ENABLED "y")
+set(CONFIG_APP_COMPILE_TIME_DATE "y")
+set(CONFIG_APP_EXCLUDE_PROJECT_VER_VAR "")
+set(CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR "")
+set(CONFIG_APP_PROJECT_VER_FROM_CONFIG "")
+set(CONFIG_APP_RETRIEVE_LEN_ELF_SHA "9")
+set(CONFIG_ESP_ROM_HAS_CRC_LE "y")
+set(CONFIG_ESP_ROM_HAS_CRC_BE "y")
+set(CONFIG_ESP_ROM_HAS_MZ_CRC32 "y")
+set(CONFIG_ESP_ROM_HAS_JPEG_DECODE "y")
+set(CONFIG_ESP_ROM_UART_CLK_IS_XTAL "y")
+set(CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM "3")
+set(CONFIG_ESP_ROM_HAS_RETARGETABLE_LOCKING "y")
+set(CONFIG_ESP_ROM_HAS_ERASE_0_REGION_BUG "y")
+set(CONFIG_ESP_ROM_HAS_ENCRYPTED_WRITES_USING_LEGACY_DRV "y")
+set(CONFIG_ESP_ROM_GET_CLK_FREQ "y")
+set(CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND "y")
+set(CONFIG_ESP_ROM_HAS_LAYOUT_TABLE "y")
+set(CONFIG_ESP_ROM_HAS_SPI_FLASH "y")
+set(CONFIG_ESP_ROM_HAS_ETS_PRINTF_BUG "y")
+set(CONFIG_ESP_ROM_HAS_NEWLIB "y")
+set(CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT "y")
+set(CONFIG_ESP_ROM_HAS_NEWLIB_32BIT_TIME "y")
+set(CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE "y")
+set(CONFIG_ESP_ROM_RAM_APP_NEEDS_MMU_INIT "y")
+set(CONFIG_ESP_ROM_HAS_SW_FLOAT "y")
+set(CONFIG_ESP_ROM_USB_OTG_NUM "-1")
+set(CONFIG_ESP_ROM_HAS_VERSION "y")
+set(CONFIG_ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB "y")
+set(CONFIG_BOOT_ROM_LOG_ALWAYS_ON "y")
+set(CONFIG_BOOT_ROM_LOG_ALWAYS_OFF "")
+set(CONFIG_BOOT_ROM_LOG_ON_GPIO_HIGH "")
+set(CONFIG_BOOT_ROM_LOG_ON_GPIO_LOW "")
+set(CONFIG_ESPTOOLPY_NO_STUB "")
+set(CONFIG_ESPTOOLPY_FLASHMODE_QIO "")
+set(CONFIG_ESPTOOLPY_FLASHMODE_QOUT "")
+set(CONFIG_ESPTOOLPY_FLASHMODE_DIO "y")
+set(CONFIG_ESPTOOLPY_FLASHMODE_DOUT "")
+set(CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR "y")
+set(CONFIG_ESPTOOLPY_FLASHMODE "dio")
+set(CONFIG_ESPTOOLPY_FLASHFREQ_80M "y")
+set(CONFIG_ESPTOOLPY_FLASHFREQ_40M "")
+set(CONFIG_ESPTOOLPY_FLASHFREQ_26M "")
+set(CONFIG_ESPTOOLPY_FLASHFREQ_20M "")
+set(CONFIG_ESPTOOLPY_FLASHFREQ "80m")
+set(CONFIG_ESPTOOLPY_FLASHSIZE_1MB "")
+set(CONFIG_ESPTOOLPY_FLASHSIZE_2MB "y")
+set(CONFIG_ESPTOOLPY_FLASHSIZE_4MB "")
+set(CONFIG_ESPTOOLPY_FLASHSIZE_8MB "")
+set(CONFIG_ESPTOOLPY_FLASHSIZE_16MB "")
+set(CONFIG_ESPTOOLPY_FLASHSIZE_32MB "")
+set(CONFIG_ESPTOOLPY_FLASHSIZE_64MB "")
+set(CONFIG_ESPTOOLPY_FLASHSIZE_128MB "")
+set(CONFIG_ESPTOOLPY_FLASHSIZE "2MB")
+set(CONFIG_ESPTOOLPY_HEADER_FLASHSIZE_UPDATE "")
+set(CONFIG_ESPTOOLPY_BEFORE_RESET "y")
+set(CONFIG_ESPTOOLPY_BEFORE_NORESET "")
+set(CONFIG_ESPTOOLPY_BEFORE "default_reset")
+set(CONFIG_ESPTOOLPY_AFTER_RESET "y")
+set(CONFIG_ESPTOOLPY_AFTER_NORESET "")
+set(CONFIG_ESPTOOLPY_AFTER "hard_reset")
+set(CONFIG_ESPTOOLPY_MONITOR_BAUD "115200")
+set(CONFIG_PARTITION_TABLE_SINGLE_APP "y")
+set(CONFIG_PARTITION_TABLE_SINGLE_APP_LARGE "")
+set(CONFIG_PARTITION_TABLE_TWO_OTA "")
+set(CONFIG_PARTITION_TABLE_TWO_OTA_LARGE "")
+set(CONFIG_PARTITION_TABLE_CUSTOM "")
+set(CONFIG_PARTITION_TABLE_CUSTOM_FILENAME "partitions.csv")
+set(CONFIG_PARTITION_TABLE_FILENAME "partitions_singleapp.csv")
+set(CONFIG_PARTITION_TABLE_OFFSET "0x8000")
+set(CONFIG_PARTITION_TABLE_MD5 "y")
+set(CONFIG_COMPILER_OPTIMIZATION_DEBUG "y")
+set(CONFIG_COMPILER_OPTIMIZATION_SIZE "")
+set(CONFIG_COMPILER_OPTIMIZATION_PERF "")
+set(CONFIG_COMPILER_OPTIMIZATION_NONE "")
+set(CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE "y")
+set(CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT "")
+set(CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE "")
+set(CONFIG_COMPILER_ASSERT_NDEBUG_EVALUATE "y")
+set(CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB "y")
+set(CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL "2")
+set(CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT "")
+set(CONFIG_COMPILER_HIDE_PATHS_MACROS "y")
+set(CONFIG_COMPILER_CXX_EXCEPTIONS "")
+set(CONFIG_COMPILER_CXX_RTTI "")
+set(CONFIG_COMPILER_STACK_CHECK_MODE_NONE "y")
+set(CONFIG_COMPILER_STACK_CHECK_MODE_NORM "")
+set(CONFIG_COMPILER_STACK_CHECK_MODE_STRONG "")
+set(CONFIG_COMPILER_STACK_CHECK_MODE_ALL "")
+set(CONFIG_COMPILER_NO_MERGE_CONSTANTS "")
+set(CONFIG_COMPILER_WARN_WRITE_STRINGS "")
+set(CONFIG_COMPILER_SAVE_RESTORE_LIBCALLS "")
+set(CONFIG_COMPILER_DISABLE_DEFAULT_ERRORS "y")
+set(CONFIG_COMPILER_DISABLE_GCC12_WARNINGS "")
+set(CONFIG_COMPILER_DISABLE_GCC13_WARNINGS "")
+set(CONFIG_COMPILER_DISABLE_GCC14_WARNINGS "")
+set(CONFIG_COMPILER_DUMP_RTL_FILES "")
+set(CONFIG_COMPILER_RT_LIB_GCCLIB "y")
+set(CONFIG_COMPILER_RT_LIB_NAME "gcc")
+set(CONFIG_COMPILER_ORPHAN_SECTIONS_WARNING "y")
+set(CONFIG_COMPILER_ORPHAN_SECTIONS_PLACE "")
+set(CONFIG_COMPILER_STATIC_ANALYZER "")
+set(CONFIG_EFUSE_CUSTOM_TABLE "")
+set(CONFIG_EFUSE_VIRTUAL "")
+set(CONFIG_EFUSE_MAX_BLK_LEN "256")
+set(CONFIG_ESP_ERR_TO_NAME_LOOKUP "y")
+set(CONFIG_ESP32C3_REV_MIN_0 "")
+set(CONFIG_ESP32C3_REV_MIN_1 "")
+set(CONFIG_ESP32C3_REV_MIN_2 "")
+set(CONFIG_ESP32C3_REV_MIN_3 "y")
+set(CONFIG_ESP32C3_REV_MIN_4 "")
+set(CONFIG_ESP32C3_REV_MIN_101 "")
+set(CONFIG_ESP32C3_REV_MIN_FULL "3")
+set(CONFIG_ESP_REV_MIN_FULL "3")
+set(CONFIG_ESP32C3_REV_MAX_FULL "199")
+set(CONFIG_ESP_REV_MAX_FULL "199")
+set(CONFIG_ESP_EFUSE_BLOCK_REV_MIN_FULL "0")
+set(CONFIG_ESP_EFUSE_BLOCK_REV_MAX_FULL "199")
+set(CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA "y")
+set(CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP "y")
+set(CONFIG_ESP_MAC_ADDR_UNIVERSE_BT "y")
+set(CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH "y")
+set(CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR "y")
+set(CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES "4")
+set(CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES_TWO "")
+set(CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR "y")
+set(CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES "4")
+set(CONFIG_ESP_MAC_USE_CUSTOM_MAC_AS_BASE_MAC "")
+set(CONFIG_ESP_SLEEP_POWER_DOWN_FLASH "")
+set(CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND "y")
+set(CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU "")
+set(CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND "y")
+set(CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY "0")
+set(CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION "")
+set(CONFIG_ESP_SLEEP_DEBUG "")
+set(CONFIG_ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS "y")
+set(CONFIG_RTC_CLK_SRC_INT_RC "y")
+set(CONFIG_RTC_CLK_SRC_EXT_CRYS "")
+set(CONFIG_RTC_CLK_SRC_EXT_OSC "")
+set(CONFIG_RTC_CLK_SRC_INT_8MD256 "")
+set(CONFIG_RTC_CLK_CAL_CYCLES "1024")
+set(CONFIG_PERIPH_CTRL_FUNC_IN_IRAM "y")
+set(CONFIG_GDMA_CTRL_FUNC_IN_IRAM "y")
+set(CONFIG_GDMA_ISR_IRAM_SAFE "")
+set(CONFIG_GDMA_ENABLE_DEBUG_LOG "")
+set(CONFIG_XTAL_FREQ_40 "y")
+set(CONFIG_XTAL_FREQ "40")
+set(CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80 "")
+set(CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160 "y")
+set(CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ "160")
+set(CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT "")
+set(CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT "y")
+set(CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT "")
+set(CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS "0")
+set(CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE "y")
+set(CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK "y")
+set(CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP "y")
+set(CONFIG_ESP_SYSTEM_USE_EH_FRAME "")
+set(CONFIG_ESP_SYSTEM_MEMPROT_FEATURE "y")
+set(CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK "y")
+set(CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE "32")
+set(CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE "2304")
+set(CONFIG_ESP_MAIN_TASK_STACK_SIZE "3584")
+set(CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0 "y")
+set(CONFIG_ESP_MAIN_TASK_AFFINITY_NO_AFFINITY "")
+set(CONFIG_ESP_MAIN_TASK_AFFINITY "0x0")
+set(CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE "2048")
+set(CONFIG_ESP_CONSOLE_UART_DEFAULT "y")
+set(CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG "")
+set(CONFIG_ESP_CONSOLE_UART_CUSTOM "")
+set(CONFIG_ESP_CONSOLE_NONE "")
+set(CONFIG_ESP_CONSOLE_SECONDARY_NONE "")
+set(CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG "y")
+set(CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED "y")
+set(CONFIG_ESP_CONSOLE_UART "y")
+set(CONFIG_ESP_CONSOLE_UART_NUM "0")
+set(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM "0")
+set(CONFIG_ESP_CONSOLE_UART_BAUDRATE "115200")
+set(CONFIG_ESP_INT_WDT "y")
+set(CONFIG_ESP_INT_WDT_TIMEOUT_MS "300")
+set(CONFIG_ESP_TASK_WDT_EN "y")
+set(CONFIG_ESP_TASK_WDT_INIT "y")
+set(CONFIG_ESP_TASK_WDT_PANIC "")
+set(CONFIG_ESP_TASK_WDT_TIMEOUT_S "5")
+set(CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 "y")
+set(CONFIG_ESP_PANIC_HANDLER_IRAM "")
+set(CONFIG_ESP_DEBUG_STUBS_ENABLE "")
+set(CONFIG_ESP_DEBUG_OCDAWARE "y")
+set(CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 "y")
+set(CONFIG_ESP_BROWNOUT_DET "y")
+set(CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7 "y")
+set(CONFIG_ESP_BROWNOUT_DET_LVL_SEL_6 "")
+set(CONFIG_ESP_BROWNOUT_DET_LVL_SEL_5 "")
+set(CONFIG_ESP_BROWNOUT_DET_LVL_SEL_4 "")
+set(CONFIG_ESP_BROWNOUT_DET_LVL_SEL_3 "")
+set(CONFIG_ESP_BROWNOUT_DET_LVL_SEL_2 "")
+set(CONFIG_ESP_BROWNOUT_DET_LVL "7")
+set(CONFIG_ESP_SYSTEM_BROWNOUT_INTR "y")
+set(CONFIG_ESP_SYSTEM_HW_STACK_GUARD "y")
+set(CONFIG_ESP_SYSTEM_HW_PC_RECORD "y")
+set(CONFIG_ESP_IPC_TASK_STACK_SIZE "1024")
+set(CONFIG_FREERTOS_SMP "")
+set(CONFIG_FREERTOS_UNICORE "y")
+set(CONFIG_FREERTOS_HZ "100")
+set(CONFIG_FREERTOS_OPTIMIZED_SCHEDULER "y")
+set(CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE "")
+set(CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL "")
+set(CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY "y")
+set(CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS "1")
+set(CONFIG_FREERTOS_IDLE_TASK_STACKSIZE "1536")
+set(CONFIG_FREERTOS_USE_IDLE_HOOK "")
+set(CONFIG_FREERTOS_USE_TICK_HOOK "")
+set(CONFIG_FREERTOS_MAX_TASK_NAME_LEN "16")
+set(CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY "")
+set(CONFIG_FREERTOS_USE_TIMERS "y")
+set(CONFIG_FREERTOS_TIMER_SERVICE_TASK_NAME "Tmr Svc")
+set(CONFIG_FREERTOS_TIMER_TASK_AFFINITY_CPU0 "")
+set(CONFIG_FREERTOS_TIMER_TASK_NO_AFFINITY "y")
+set(CONFIG_FREERTOS_TIMER_SERVICE_TASK_CORE_AFFINITY "0x7fffffff")
+set(CONFIG_FREERTOS_TIMER_TASK_PRIORITY "1")
+set(CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH "2048")
+set(CONFIG_FREERTOS_TIMER_QUEUE_LENGTH "10")
+set(CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE "0")
+set(CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES "1")
+set(CONFIG_FREERTOS_USE_TRACE_FACILITY "")
+set(CONFIG_FREERTOS_USE_LIST_DATA_INTEGRITY_CHECK_BYTES "")
+set(CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS "")
+set(CONFIG_FREERTOS_USE_APPLICATION_TASK_TAG "")
+set(CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER "y")
+set(CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK "")
+set(CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS "y")
+set(CONFIG_FREERTOS_TASK_PRE_DELETION_HOOK "")
+set(CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP "")
+set(CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER "y")
+set(CONFIG_FREERTOS_ISR_STACKSIZE "1536")
+set(CONFIG_FREERTOS_INTERRUPT_BACKTRACE "y")
+set(CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER "y")
+set(CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1 "y")
+set(CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3 "")
+set(CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER "y")
+set(CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH "")
+set(CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE "")
+set(CONFIG_FREERTOS_PORT "y")
+set(CONFIG_FREERTOS_NO_AFFINITY "0x7fffffff")
+set(CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION "y")
+set(CONFIG_FREERTOS_DEBUG_OCDAWARE "y")
+set(CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT "y")
+set(CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH "y")
+set(CONFIG_FREERTOS_NUMBER_OF_CORES "1")
+set(CONFIG_HAL_ASSERTION_EQUALS_SYSTEM "y")
+set(CONFIG_HAL_ASSERTION_DISABLE "")
+set(CONFIG_HAL_ASSERTION_SILENT "")
+set(CONFIG_HAL_ASSERTION_ENABLE "")
+set(CONFIG_HAL_DEFAULT_ASSERTION_LEVEL "2")
+set(CONFIG_LOG_DEFAULT_LEVEL_NONE "")
+set(CONFIG_LOG_DEFAULT_LEVEL_ERROR "")
+set(CONFIG_LOG_DEFAULT_LEVEL_WARN "")
+set(CONFIG_LOG_DEFAULT_LEVEL_INFO "y")
+set(CONFIG_LOG_DEFAULT_LEVEL_DEBUG "")
+set(CONFIG_LOG_DEFAULT_LEVEL_VERBOSE "")
+set(CONFIG_LOG_DEFAULT_LEVEL "3")
+set(CONFIG_LOG_MAXIMUM_EQUALS_DEFAULT "y")
+set(CONFIG_LOG_MAXIMUM_LEVEL_DEBUG "")
+set(CONFIG_LOG_MAXIMUM_LEVEL_VERBOSE "")
+set(CONFIG_LOG_MAXIMUM_LEVEL "3")
+set(CONFIG_LOG_MASTER_LEVEL "")
+set(CONFIG_LOG_DYNAMIC_LEVEL_CONTROL "y")
+set(CONFIG_LOG_TAG_LEVEL_IMPL_NONE "")
+set(CONFIG_LOG_TAG_LEVEL_IMPL_LINKED_LIST "")
+set(CONFIG_LOG_TAG_LEVEL_IMPL_CACHE_AND_LINKED_LIST "y")
+set(CONFIG_LOG_TAG_LEVEL_CACHE_ARRAY "")
+set(CONFIG_LOG_TAG_LEVEL_CACHE_BINARY_MIN_HEAP "y")
+set(CONFIG_LOG_TAG_LEVEL_IMPL_CACHE_SIZE "31")
+set(CONFIG_LOG_COLORS "")
+set(CONFIG_LOG_TIMESTAMP_SOURCE_RTOS "y")
+set(CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM "")
+set(CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF "y")
+set(CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF "")
+set(CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR "")
+set(CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF "")
+set(CONFIG_NEWLIB_STDIN_LINE_ENDING_LF "")
+set(CONFIG_NEWLIB_STDIN_LINE_ENDING_CR "y")
+set(CONFIG_NEWLIB_NANO_FORMAT "")
+set(CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT "y")
+set(CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC "")
+set(CONFIG_NEWLIB_TIME_SYSCALL_USE_HRT "")
+set(CONFIG_NEWLIB_TIME_SYSCALL_USE_NONE "")
+set(CONFIG_MMU_PAGE_SIZE_64KB "y")
+set(CONFIG_MMU_PAGE_MODE "64KB")
+set(CONFIG_MMU_PAGE_SIZE "0x10000")
+set(CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC "y")
+set(CONFIG_SPI_FLASH_BROWNOUT_RESET "y")
+set(CONFIG_SPI_FLASH_AUTO_SUSPEND "")
+set(CONFIG_SPI_FLASH_SUSPEND_TSUS_VAL_US "50")
+set(CONFIG_SPI_FLASH_FORCE_ENABLE_XMC_C_SUSPEND "")
+set(CONFIG_SPI_FLASH_VERIFY_WRITE "")
+set(CONFIG_SPI_FLASH_ENABLE_COUNTERS "")
+set(CONFIG_SPI_FLASH_ROM_DRIVER_PATCH "y")
+set(CONFIG_SPI_FLASH_ROM_IMPL "")
+set(CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS "y")
+set(CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS "")
+set(CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED "")
+set(CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE "")
+set(CONFIG_SPI_FLASH_YIELD_DURING_ERASE "y")
+set(CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS "20")
+set(CONFIG_SPI_FLASH_ERASE_YIELD_TICKS "1")
+set(CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE "8192")
+set(CONFIG_SPI_FLASH_SIZE_OVERRIDE "")
+set(CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED "")
+set(CONFIG_SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST "")
+set(CONFIG_SPI_FLASH_VENDOR_XMC_SUPPORTED "y")
+set(CONFIG_SPI_FLASH_VENDOR_GD_SUPPORTED "y")
+set(CONFIG_SPI_FLASH_VENDOR_ISSI_SUPPORTED "y")
+set(CONFIG_SPI_FLASH_VENDOR_MXIC_SUPPORTED "y")
+set(CONFIG_SPI_FLASH_VENDOR_WINBOND_SUPPORTED "y")
+set(CONFIG_SPI_FLASH_VENDOR_BOYA_SUPPORTED "y")
+set(CONFIG_SPI_FLASH_VENDOR_TH_SUPPORTED "y")
+set(CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP "y")
+set(CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP "y")
+set(CONFIG_SPI_FLASH_SUPPORT_GD_CHIP "y")
+set(CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP "y")
+set(CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP "y")
+set(CONFIG_SPI_FLASH_SUPPORT_TH_CHIP "y")
+set(CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE "y")
+set(CONFIG_IDF_EXPERIMENTAL_FEATURES "")
+set(CONFIGS_LIST CONFIG_SOC_ADC_SUPPORTED;CONFIG_SOC_DEDICATED_GPIO_SUPPORTED;CONFIG_SOC_UART_SUPPORTED;CONFIG_SOC_GDMA_SUPPORTED;CONFIG_SOC_AHB_GDMA_SUPPORTED;CONFIG_SOC_GPTIMER_SUPPORTED;CONFIG_SOC_TWAI_SUPPORTED;CONFIG_SOC_BT_SUPPORTED;CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED;CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED;CONFIG_SOC_TEMP_SENSOR_SUPPORTED;CONFIG_SOC_XT_WDT_SUPPORTED;CONFIG_SOC_PHY_SUPPORTED;CONFIG_SOC_WIFI_SUPPORTED;CONFIG_SOC_SUPPORTS_SECURE_DL_MODE;CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD;CONFIG_SOC_EFUSE_HAS_EFUSE_RST_BUG;CONFIG_SOC_EFUSE_SUPPORTED;CONFIG_SOC_RTC_FAST_MEM_SUPPORTED;CONFIG_SOC_RTC_MEM_SUPPORTED;CONFIG_SOC_I2S_SUPPORTED;CONFIG_SOC_RMT_SUPPORTED;CONFIG_SOC_SDM_SUPPORTED;CONFIG_SOC_GPSPI_SUPPORTED;CONFIG_SOC_LEDC_SUPPORTED;CONFIG_SOC_I2C_SUPPORTED;CONFIG_SOC_SYSTIMER_SUPPORTED;CONFIG_SOC_SUPPORT_COEXISTENCE;CONFIG_SOC_AES_SUPPORTED;CONFIG_SOC_MPI_SUPPORTED;CONFIG_SOC_SHA_SUPPORTED;CONFIG_SOC_HMAC_SUPPORTED;CONFIG_SOC_DIG_SIGN_SUPPORTED;CONFIG_SOC_FLASH_ENC_SUPPORTED;CONFIG_SOC_SECURE_BOOT_SUPPORTED;CONFIG_SOC_MEMPROT_SUPPORTED;CONFIG_SOC_BOD_SUPPORTED;CONFIG_SOC_CLK_TREE_SUPPORTED;CONFIG_SOC_ASSIST_DEBUG_SUPPORTED;CONFIG_SOC_WDT_SUPPORTED;CONFIG_SOC_SPI_FLASH_SUPPORTED;CONFIG_SOC_RNG_SUPPORTED;CONFIG_SOC_LIGHT_SLEEP_SUPPORTED;CONFIG_SOC_DEEP_SLEEP_SUPPORTED;CONFIG_SOC_LP_PERIPH_SHARE_INTERRUPT;CONFIG_SOC_PM_SUPPORTED;CONFIG_SOC_XTAL_SUPPORT_40M;CONFIG_SOC_AES_SUPPORT_DMA;CONFIG_SOC_AES_GDMA;CONFIG_SOC_AES_SUPPORT_AES_128;CONFIG_SOC_AES_SUPPORT_AES_256;CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED;CONFIG_SOC_ADC_ARBITER_SUPPORTED;CONFIG_SOC_ADC_DIG_IIR_FILTER_SUPPORTED;CONFIG_SOC_ADC_MONITOR_SUPPORTED;CONFIG_SOC_ADC_DMA_SUPPORTED;CONFIG_SOC_ADC_PERIPH_NUM;CONFIG_SOC_ADC_MAX_CHANNEL_NUM;CONFIG_SOC_ADC_ATTEN_NUM;CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM;CONFIG_SOC_ADC_PATT_LEN_MAX;CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH;CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH;CONFIG_SOC_ADC_DIGI_RESULT_BYTES;CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV;CONFIG_SOC_ADC_DIGI_IIR_FILTER_NUM;CONFIG_SOC_ADC_DIGI_MONITOR_NUM;CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH;CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW;CONFIG_SOC_ADC_RTC_MIN_BITWIDTH;CONFIG_SOC_ADC_RTC_MAX_BITWIDTH;CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED;CONFIG_SOC_ADC_SELF_HW_CALI_SUPPORTED;CONFIG_SOC_ADC_SHARED_POWER;CONFIG_SOC_APB_BACKUP_DMA;CONFIG_SOC_BROWNOUT_RESET_SUPPORTED;CONFIG_SOC_SHARED_IDCACHE_SUPPORTED;CONFIG_SOC_CACHE_MEMORY_IBANK_SIZE;CONFIG_SOC_CPU_CORES_NUM;CONFIG_SOC_CPU_INTR_NUM;CONFIG_SOC_CPU_HAS_FLEXIBLE_INTC;CONFIG_SOC_CPU_HAS_CSR_PC;CONFIG_SOC_CPU_BREAKPOINTS_NUM;CONFIG_SOC_CPU_WATCHPOINTS_NUM;CONFIG_SOC_CPU_WATCHPOINT_MAX_REGION_SIZE;CONFIG_SOC_DS_SIGNATURE_MAX_BIT_LEN;CONFIG_SOC_DS_KEY_PARAM_MD_IV_LENGTH;CONFIG_SOC_DS_KEY_CHECK_MAX_WAIT_US;CONFIG_SOC_AHB_GDMA_VERSION;CONFIG_SOC_GDMA_NUM_GROUPS_MAX;CONFIG_SOC_GDMA_PAIRS_PER_GROUP_MAX;CONFIG_SOC_GPIO_PORT;CONFIG_SOC_GPIO_PIN_COUNT;CONFIG_SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER;CONFIG_SOC_GPIO_FILTER_CLK_SUPPORT_APB;CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD;CONFIG_SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP;CONFIG_SOC_GPIO_IN_RANGE_MAX;CONFIG_SOC_GPIO_OUT_RANGE_MAX;CONFIG_SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK;CONFIG_SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT;CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK;CONFIG_SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX;CONFIG_SOC_GPIO_CLOCKOUT_CHANNEL_NUM;CONFIG_SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP;CONFIG_SOC_DEDIC_GPIO_OUT_CHANNELS_NUM;CONFIG_SOC_DEDIC_GPIO_IN_CHANNELS_NUM;CONFIG_SOC_DEDIC_PERIPH_ALWAYS_ENABLE;CONFIG_SOC_I2C_NUM;CONFIG_SOC_HP_I2C_NUM;CONFIG_SOC_I2C_FIFO_LEN;CONFIG_SOC_I2C_CMD_REG_NUM;CONFIG_SOC_I2C_SUPPORT_SLAVE;CONFIG_SOC_I2C_SUPPORT_HW_CLR_BUS;CONFIG_SOC_I2C_SUPPORT_XTAL;CONFIG_SOC_I2C_SUPPORT_RTC;CONFIG_SOC_I2C_SUPPORT_10BIT_ADDR;CONFIG_SOC_I2C_SLAVE_SUPPORT_BROADCAST;CONFIG_SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE;CONFIG_SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS;CONFIG_SOC_I2S_NUM;CONFIG_SOC_I2S_HW_VERSION_2;CONFIG_SOC_I2S_SUPPORTS_XTAL;CONFIG_SOC_I2S_SUPPORTS_PLL_F160M;CONFIG_SOC_I2S_SUPPORTS_PCM;CONFIG_SOC_I2S_SUPPORTS_PDM;CONFIG_SOC_I2S_SUPPORTS_PDM_TX;CONFIG_SOC_I2S_PDM_MAX_TX_LINES;CONFIG_SOC_I2S_SUPPORTS_TDM;CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK;CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK;CONFIG_SOC_LEDC_TIMER_NUM;CONFIG_SOC_LEDC_CHANNEL_NUM;CONFIG_SOC_LEDC_TIMER_BIT_WIDTH;CONFIG_SOC_LEDC_SUPPORT_FADE_STOP;CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM;CONFIG_SOC_MMU_PERIPH_NUM;CONFIG_SOC_MPU_MIN_REGION_SIZE;CONFIG_SOC_MPU_REGIONS_MAX_NUM;CONFIG_SOC_RMT_GROUPS;CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP;CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP;CONFIG_SOC_RMT_CHANNELS_PER_GROUP;CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL;CONFIG_SOC_RMT_SUPPORT_RX_PINGPONG;CONFIG_SOC_RMT_SUPPORT_RX_DEMODULATION;CONFIG_SOC_RMT_SUPPORT_TX_ASYNC_STOP;CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT;CONFIG_SOC_RMT_SUPPORT_TX_SYNCHRO;CONFIG_SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY;CONFIG_SOC_RMT_SUPPORT_XTAL;CONFIG_SOC_RMT_SUPPORT_APB;CONFIG_SOC_RMT_SUPPORT_RC_FAST;CONFIG_SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH;CONFIG_SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM;CONFIG_SOC_SLEEP_SYSTIMER_STALL_WORKAROUND;CONFIG_SOC_SLEEP_TGWDT_STOP_WORKAROUND;CONFIG_SOC_RTCIO_PIN_COUNT;CONFIG_SOC_MPI_MEM_BLOCKS_NUM;CONFIG_SOC_MPI_OPERATIONS_NUM;CONFIG_SOC_RSA_MAX_BIT_LEN;CONFIG_SOC_SHA_DMA_MAX_BUFFER_SIZE;CONFIG_SOC_SHA_SUPPORT_DMA;CONFIG_SOC_SHA_SUPPORT_RESUME;CONFIG_SOC_SHA_GDMA;CONFIG_SOC_SHA_SUPPORT_SHA1;CONFIG_SOC_SHA_SUPPORT_SHA224;CONFIG_SOC_SHA_SUPPORT_SHA256;CONFIG_SOC_SDM_GROUPS;CONFIG_SOC_SDM_CHANNELS_PER_GROUP;CONFIG_SOC_SDM_CLK_SUPPORT_APB;CONFIG_SOC_SPI_PERIPH_NUM;CONFIG_SOC_SPI_MAX_CS_NUM;CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE;CONFIG_SOC_SPI_SUPPORT_DDRCLK;CONFIG_SOC_SPI_SLAVE_SUPPORT_SEG_TRANS;CONFIG_SOC_SPI_SUPPORT_CD_SIG;CONFIG_SOC_SPI_SUPPORT_CONTINUOUS_TRANS;CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2;CONFIG_SOC_SPI_SUPPORT_CLK_APB;CONFIG_SOC_SPI_SUPPORT_CLK_XTAL;CONFIG_SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT;CONFIG_SOC_SPI_SCT_SUPPORTED;CONFIG_SOC_SPI_SCT_REG_NUM;CONFIG_SOC_SPI_SCT_BUFFER_NUM_MAX;CONFIG_SOC_SPI_SCT_CONF_BITLEN_MAX;CONFIG_SOC_MEMSPI_IS_INDEPENDENT;CONFIG_SOC_SPI_MAX_PRE_DIVIDER;CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE;CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND;CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_RESUME;CONFIG_SOC_SPI_MEM_SUPPORT_IDLE_INTR;CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND;CONFIG_SOC_SPI_MEM_SUPPORT_CHECK_SUS;CONFIG_SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE;CONFIG_SOC_SPI_MEM_SUPPORT_WRAP;CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED;CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED;CONFIG_SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED;CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED;CONFIG_SOC_SYSTIMER_COUNTER_NUM;CONFIG_SOC_SYSTIMER_ALARM_NUM;CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO;CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI;CONFIG_SOC_SYSTIMER_FIXED_DIVIDER;CONFIG_SOC_SYSTIMER_INT_LEVEL;CONFIG_SOC_SYSTIMER_ALARM_MISS_COMPENSATE;CONFIG_SOC_TIMER_GROUPS;CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP;CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH;CONFIG_SOC_TIMER_GROUP_SUPPORT_XTAL;CONFIG_SOC_TIMER_GROUP_SUPPORT_APB;CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS;CONFIG_SOC_LP_TIMER_BIT_WIDTH_LO;CONFIG_SOC_LP_TIMER_BIT_WIDTH_HI;CONFIG_SOC_MWDT_SUPPORT_XTAL;CONFIG_SOC_TWAI_CONTROLLER_NUM;CONFIG_SOC_TWAI_CLK_SUPPORT_APB;CONFIG_SOC_TWAI_BRP_MIN;CONFIG_SOC_TWAI_BRP_MAX;CONFIG_SOC_TWAI_SUPPORTS_RX_STATUS;CONFIG_SOC_EFUSE_DIS_DOWNLOAD_ICACHE;CONFIG_SOC_EFUSE_DIS_PAD_JTAG;CONFIG_SOC_EFUSE_DIS_USB_JTAG;CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT;CONFIG_SOC_EFUSE_SOFT_DIS_JTAG;CONFIG_SOC_EFUSE_DIS_ICACHE;CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK;CONFIG_SOC_SECURE_BOOT_V2_RSA;CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS;CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS;CONFIG_SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY;CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX;CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES;CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128;CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE;CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE;CONFIG_SOC_UART_NUM;CONFIG_SOC_UART_HP_NUM;CONFIG_SOC_UART_FIFO_LEN;CONFIG_SOC_UART_BITRATE_MAX;CONFIG_SOC_UART_SUPPORT_APB_CLK;CONFIG_SOC_UART_SUPPORT_RTC_CLK;CONFIG_SOC_UART_SUPPORT_XTAL_CLK;CONFIG_SOC_UART_SUPPORT_WAKEUP_INT;CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND;CONFIG_SOC_COEX_HW_PTI;CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE;CONFIG_SOC_MAC_BB_PD_MEM_SIZE;CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH;CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP;CONFIG_SOC_PM_SUPPORT_BT_WAKEUP;CONFIG_SOC_PM_SUPPORT_CPU_PD;CONFIG_SOC_PM_SUPPORT_WIFI_PD;CONFIG_SOC_PM_SUPPORT_BT_PD;CONFIG_SOC_PM_SUPPORT_RC_FAST_PD;CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD;CONFIG_SOC_PM_SUPPORT_MAC_BB_PD;CONFIG_SOC_PM_CPU_RETENTION_BY_RTCCNTL;CONFIG_SOC_PM_MODEM_RETENTION_BY_BACKUPDMA;CONFIG_SOC_PM_MODEM_PD_BY_SW;CONFIG_SOC_CLK_RC_FAST_D256_SUPPORTED;CONFIG_SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256;CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION;CONFIG_SOC_CLK_XTAL32K_SUPPORTED;CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC;CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL;CONFIG_SOC_WIFI_HW_TSF;CONFIG_SOC_WIFI_FTM_SUPPORT;CONFIG_SOC_WIFI_GCMP_SUPPORT;CONFIG_SOC_WIFI_WAPI_SUPPORT;CONFIG_SOC_WIFI_CSI_SUPPORT;CONFIG_SOC_WIFI_MESH_SUPPORT;CONFIG_SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW;CONFIG_SOC_WIFI_PHY_NEEDS_USB_WORKAROUND;CONFIG_SOC_BLE_SUPPORTED;CONFIG_SOC_BLE_MESH_SUPPORTED;CONFIG_SOC_BLE_50_SUPPORTED;CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED;CONFIG_SOC_BLUFI_SUPPORTED;CONFIG_SOC_PHY_COMBO_MODULE;CONFIG_IDF_CMAKE;CONFIG_IDF_TOOLCHAIN;CONFIG_IDF_TOOLCHAIN_GCC;CONFIG_IDF_TARGET_ARCH_RISCV;CONFIG_IDF_TARGET_ARCH;CONFIG_IDF_TARGET;CONFIG_IDF_INIT_VERSION;CONFIG_IDF_TARGET_ESP32C3;CONFIG_IDF_FIRMWARE_CHIP_ID;CONFIG_APP_BUILD_TYPE_APP_2NDBOOT;CONFIG_APP_BUILD_TYPE_RAM;CONFIG_APP_BUILD_TYPE_ELF_RAM;CONFIG_APP_BUILD_GENERATE_BINARIES;CONFIG_APP_BUILD_BOOTLOADER;CONFIG_APP_BUILD_USE_FLASH_SECTIONS;CONFIG_APP_REPRODUCIBLE_BUILD;CONFIG_APP_NO_BLOBS;CONFIG_NO_BLOBS;CONFIG_BOOTLOADER_COMPILE_TIME_DATE;CONFIG_BOOTLOADER_PROJECT_VER;CONFIG_BOOTLOADER_OFFSET_IN_FLASH;CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE;CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG;CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF;CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_NONE;CONFIG_BOOTLOADER_LOG_LEVEL_NONE;CONFIG_LOG_BOOTLOADER_LEVEL_NONE;CONFIG_BOOTLOADER_LOG_LEVEL_ERROR;CONFIG_LOG_BOOTLOADER_LEVEL_ERROR;CONFIG_BOOTLOADER_LOG_LEVEL_WARN;CONFIG_LOG_BOOTLOADER_LEVEL_WARN;CONFIG_BOOTLOADER_LOG_LEVEL_INFO;CONFIG_LOG_BOOTLOADER_LEVEL_INFO;CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG;CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG;CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE;CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE;CONFIG_BOOTLOADER_LOG_LEVEL;CONFIG_LOG_BOOTLOADER_LEVEL;CONFIG_BOOTLOADER_LOG_COLORS;CONFIG_BOOTLOADER_LOG_TIMESTAMP_SOURCE_CPU_TICKS;CONFIG_BOOTLOADER_FLASH_DC_AWARE;CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT;CONFIG_BOOTLOADER_FACTORY_RESET;CONFIG_BOOTLOADER_APP_TEST;CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE;CONFIG_BOOTLOADER_WDT_ENABLE;CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE;CONFIG_BOOTLOADER_WDT_TIME_MS;CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE;CONFIG_APP_ROLLBACK_ENABLE;CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP;CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON;CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS;CONFIG_BOOTLOADER_RESERVE_RTC_SIZE;CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC;CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED;CONFIG_SECURE_BOOT_V2_PREFERRED;CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT;CONFIG_SECURE_BOOT;CONFIG_SECURE_FLASH_ENC_ENABLED;CONFIG_FLASH_ENCRYPTION_ENABLED;CONFIG_SECURE_ROM_DL_MODE_ENABLED;CONFIG_APP_COMPILE_TIME_DATE;CONFIG_APP_EXCLUDE_PROJECT_VER_VAR;CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR;CONFIG_APP_PROJECT_VER_FROM_CONFIG;CONFIG_APP_RETRIEVE_LEN_ELF_SHA;CONFIG_ESP_ROM_HAS_CRC_LE;CONFIG_ESP_ROM_HAS_CRC_BE;CONFIG_ESP_ROM_HAS_MZ_CRC32;CONFIG_ESP_ROM_HAS_JPEG_DECODE;CONFIG_ESP_ROM_UART_CLK_IS_XTAL;CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM;CONFIG_ESP_ROM_HAS_RETARGETABLE_LOCKING;CONFIG_ESP_ROM_HAS_ERASE_0_REGION_BUG;CONFIG_ESP_ROM_HAS_ENCRYPTED_WRITES_USING_LEGACY_DRV;CONFIG_ESP_ROM_GET_CLK_FREQ;CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND;CONFIG_ESP_ROM_HAS_LAYOUT_TABLE;CONFIG_ESP_ROM_HAS_SPI_FLASH;CONFIG_ESP_ROM_HAS_ETS_PRINTF_BUG;CONFIG_ESP_ROM_HAS_NEWLIB;CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT;CONFIG_ESP_ROM_HAS_NEWLIB_32BIT_TIME;CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE;CONFIG_ESP_ROM_RAM_APP_NEEDS_MMU_INIT;CONFIG_ESP_ROM_HAS_SW_FLOAT;CONFIG_ESP_ROM_USB_OTG_NUM;CONFIG_ESP_ROM_HAS_VERSION;CONFIG_ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB;CONFIG_BOOT_ROM_LOG_ALWAYS_ON;CONFIG_BOOT_ROM_LOG_ALWAYS_OFF;CONFIG_BOOT_ROM_LOG_ON_GPIO_HIGH;CONFIG_BOOT_ROM_LOG_ON_GPIO_LOW;CONFIG_ESPTOOLPY_NO_STUB;CONFIG_ESPTOOLPY_FLASHMODE_QIO;CONFIG_FLASHMODE_QIO;CONFIG_ESPTOOLPY_FLASHMODE_QOUT;CONFIG_FLASHMODE_QOUT;CONFIG_ESPTOOLPY_FLASHMODE_DIO;CONFIG_FLASHMODE_DIO;CONFIG_ESPTOOLPY_FLASHMODE_DOUT;CONFIG_FLASHMODE_DOUT;CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR;CONFIG_ESPTOOLPY_FLASHMODE;CONFIG_ESPTOOLPY_FLASHFREQ_80M;CONFIG_ESPTOOLPY_FLASHFREQ_40M;CONFIG_ESPTOOLPY_FLASHFREQ_26M;CONFIG_ESPTOOLPY_FLASHFREQ_20M;CONFIG_ESPTOOLPY_FLASHFREQ;CONFIG_ESPTOOLPY_FLASHSIZE_1MB;CONFIG_ESPTOOLPY_FLASHSIZE_2MB;CONFIG_ESPTOOLPY_FLASHSIZE_4MB;CONFIG_ESPTOOLPY_FLASHSIZE_8MB;CONFIG_ESPTOOLPY_FLASHSIZE_16MB;CONFIG_ESPTOOLPY_FLASHSIZE_32MB;CONFIG_ESPTOOLPY_FLASHSIZE_64MB;CONFIG_ESPTOOLPY_FLASHSIZE_128MB;CONFIG_ESPTOOLPY_FLASHSIZE;CONFIG_ESPTOOLPY_HEADER_FLASHSIZE_UPDATE;CONFIG_ESPTOOLPY_BEFORE_RESET;CONFIG_ESPTOOLPY_BEFORE_NORESET;CONFIG_ESPTOOLPY_BEFORE;CONFIG_ESPTOOLPY_AFTER_RESET;CONFIG_ESPTOOLPY_AFTER_NORESET;CONFIG_ESPTOOLPY_AFTER;CONFIG_ESPTOOLPY_MONITOR_BAUD;CONFIG_MONITOR_BAUD;CONFIG_PARTITION_TABLE_SINGLE_APP;CONFIG_PARTITION_TABLE_SINGLE_APP_LARGE;CONFIG_PARTITION_TABLE_TWO_OTA;CONFIG_PARTITION_TABLE_TWO_OTA_LARGE;CONFIG_PARTITION_TABLE_CUSTOM;CONFIG_PARTITION_TABLE_CUSTOM_FILENAME;CONFIG_PARTITION_TABLE_FILENAME;CONFIG_PARTITION_TABLE_OFFSET;CONFIG_PARTITION_TABLE_MD5;CONFIG_COMPILER_OPTIMIZATION_DEBUG;CONFIG_OPTIMIZATION_LEVEL_DEBUG;CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG;CONFIG_COMPILER_OPTIMIZATION_DEFAULT;CONFIG_COMPILER_OPTIMIZATION_SIZE;CONFIG_OPTIMIZATION_LEVEL_RELEASE;CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE;CONFIG_COMPILER_OPTIMIZATION_PERF;CONFIG_COMPILER_OPTIMIZATION_NONE;CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE;CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED;CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT;CONFIG_OPTIMIZATION_ASSERTIONS_SILENT;CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE;CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED;CONFIG_COMPILER_ASSERT_NDEBUG_EVALUATE;CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB;CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL;CONFIG_OPTIMIZATION_ASSERTION_LEVEL;CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT;CONFIG_COMPILER_HIDE_PATHS_MACROS;CONFIG_COMPILER_CXX_EXCEPTIONS;CONFIG_CXX_EXCEPTIONS;CONFIG_COMPILER_CXX_RTTI;CONFIG_COMPILER_STACK_CHECK_MODE_NONE;CONFIG_STACK_CHECK_NONE;CONFIG_COMPILER_STACK_CHECK_MODE_NORM;CONFIG_STACK_CHECK_NORM;CONFIG_COMPILER_STACK_CHECK_MODE_STRONG;CONFIG_STACK_CHECK_STRONG;CONFIG_COMPILER_STACK_CHECK_MODE_ALL;CONFIG_STACK_CHECK_ALL;CONFIG_COMPILER_NO_MERGE_CONSTANTS;CONFIG_COMPILER_WARN_WRITE_STRINGS;CONFIG_WARN_WRITE_STRINGS;CONFIG_COMPILER_SAVE_RESTORE_LIBCALLS;CONFIG_COMPILER_DISABLE_DEFAULT_ERRORS;CONFIG_COMPILER_DISABLE_GCC12_WARNINGS;CONFIG_COMPILER_DISABLE_GCC13_WARNINGS;CONFIG_COMPILER_DISABLE_GCC14_WARNINGS;CONFIG_COMPILER_DUMP_RTL_FILES;CONFIG_COMPILER_RT_LIB_GCCLIB;CONFIG_COMPILER_RT_LIB_NAME;CONFIG_COMPILER_ORPHAN_SECTIONS_WARNING;CONFIG_COMPILER_ORPHAN_SECTIONS_PLACE;CONFIG_COMPILER_STATIC_ANALYZER;CONFIG_EFUSE_CUSTOM_TABLE;CONFIG_EFUSE_VIRTUAL;CONFIG_EFUSE_MAX_BLK_LEN;CONFIG_ESP_ERR_TO_NAME_LOOKUP;CONFIG_ESP32C3_REV_MIN_0;CONFIG_ESP32C3_REV_MIN_1;CONFIG_ESP32C3_REV_MIN_2;CONFIG_ESP32C3_REV_MIN_3;CONFIG_ESP32C3_REV_MIN_4;CONFIG_ESP32C3_REV_MIN_101;CONFIG_ESP32C3_REV_MIN_FULL;CONFIG_ESP_REV_MIN_FULL;CONFIG_ESP32C3_REV_MAX_FULL;CONFIG_ESP_REV_MAX_FULL;CONFIG_ESP_EFUSE_BLOCK_REV_MIN_FULL;CONFIG_ESP_EFUSE_BLOCK_REV_MAX_FULL;CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA;CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP;CONFIG_ESP_MAC_ADDR_UNIVERSE_BT;CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH;CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR;CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES;CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES_TWO;CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR;CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES;CONFIG_ESP_MAC_USE_CUSTOM_MAC_AS_BASE_MAC;CONFIG_ESP_SLEEP_POWER_DOWN_FLASH;CONFIG_ESP_SYSTEM_PD_FLASH;CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND;CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU;CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND;CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND;CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY;CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION;CONFIG_ESP_SLEEP_DEBUG;CONFIG_ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS;CONFIG_RTC_CLK_SRC_INT_RC;CONFIG_ESP32C3_RTC_CLK_SRC_INT_RC;CONFIG_RTC_CLK_SRC_EXT_CRYS;CONFIG_ESP32C3_RTC_CLK_SRC_EXT_CRYS;CONFIG_RTC_CLK_SRC_EXT_OSC;CONFIG_ESP32C3_RTC_CLK_SRC_EXT_OSC;CONFIG_RTC_CLK_SRC_INT_8MD256;CONFIG_ESP32C3_RTC_CLK_SRC_INT_8MD256;CONFIG_RTC_CLK_CAL_CYCLES;CONFIG_ESP32C3_RTC_CLK_CAL_CYCLES;CONFIG_PERIPH_CTRL_FUNC_IN_IRAM;CONFIG_GDMA_CTRL_FUNC_IN_IRAM;CONFIG_GDMA_ISR_IRAM_SAFE;CONFIG_GDMA_ENABLE_DEBUG_LOG;CONFIG_XTAL_FREQ_40;CONFIG_XTAL_FREQ;CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80;CONFIG_ESP32C3_DEFAULT_CPU_FREQ_80;CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160;CONFIG_ESP32C3_DEFAULT_CPU_FREQ_160;CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ;CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ;CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT;CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT;CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT;CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS;CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE;CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK;CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP;CONFIG_ESP_SYSTEM_USE_EH_FRAME;CONFIG_ESP_SYSTEM_MEMPROT_FEATURE;CONFIG_ESP32C3_MEMPROT_FEATURE;CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK;CONFIG_ESP32C3_MEMPROT_FEATURE_LOCK;CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE;CONFIG_SYSTEM_EVENT_QUEUE_SIZE;CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE;CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE;CONFIG_ESP_MAIN_TASK_STACK_SIZE;CONFIG_MAIN_TASK_STACK_SIZE;CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0;CONFIG_ESP_MAIN_TASK_AFFINITY_NO_AFFINITY;CONFIG_ESP_MAIN_TASK_AFFINITY;CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE;CONFIG_ESP_CONSOLE_UART_DEFAULT;CONFIG_CONSOLE_UART_DEFAULT;CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG;CONFIG_ESP_CONSOLE_UART_CUSTOM;CONFIG_CONSOLE_UART_CUSTOM;CONFIG_ESP_CONSOLE_NONE;CONFIG_CONSOLE_UART_NONE;CONFIG_ESP_CONSOLE_UART_NONE;CONFIG_ESP_CONSOLE_SECONDARY_NONE;CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG;CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED;CONFIG_ESP_CONSOLE_UART;CONFIG_CONSOLE_UART;CONFIG_ESP_CONSOLE_UART_NUM;CONFIG_CONSOLE_UART_NUM;CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM;CONFIG_ESP_CONSOLE_UART_BAUDRATE;CONFIG_CONSOLE_UART_BAUDRATE;CONFIG_ESP_INT_WDT;CONFIG_INT_WDT;CONFIG_ESP_INT_WDT_TIMEOUT_MS;CONFIG_INT_WDT_TIMEOUT_MS;CONFIG_ESP_TASK_WDT_EN;CONFIG_ESP_TASK_WDT_INIT;CONFIG_TASK_WDT;CONFIG_ESP_TASK_WDT;CONFIG_ESP_TASK_WDT_PANIC;CONFIG_TASK_WDT_PANIC;CONFIG_ESP_TASK_WDT_TIMEOUT_S;CONFIG_TASK_WDT_TIMEOUT_S;CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0;CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0;CONFIG_ESP_PANIC_HANDLER_IRAM;CONFIG_ESP_DEBUG_STUBS_ENABLE;CONFIG_ESP32_DEBUG_STUBS_ENABLE;CONFIG_ESP_DEBUG_OCDAWARE;CONFIG_ESP32C3_DEBUG_OCDAWARE;CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4;CONFIG_ESP_BROWNOUT_DET;CONFIG_BROWNOUT_DET;CONFIG_ESP32C3_BROWNOUT_DET;CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7;CONFIG_BROWNOUT_DET_LVL_SEL_7;CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_7;CONFIG_ESP_BROWNOUT_DET_LVL_SEL_6;CONFIG_BROWNOUT_DET_LVL_SEL_6;CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_6;CONFIG_ESP_BROWNOUT_DET_LVL_SEL_5;CONFIG_BROWNOUT_DET_LVL_SEL_5;CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_5;CONFIG_ESP_BROWNOUT_DET_LVL_SEL_4;CONFIG_BROWNOUT_DET_LVL_SEL_4;CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_4;CONFIG_ESP_BROWNOUT_DET_LVL_SEL_3;CONFIG_BROWNOUT_DET_LVL_SEL_3;CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_3;CONFIG_ESP_BROWNOUT_DET_LVL_SEL_2;CONFIG_BROWNOUT_DET_LVL_SEL_2;CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_2;CONFIG_ESP_BROWNOUT_DET_LVL;CONFIG_BROWNOUT_DET_LVL;CONFIG_ESP32C3_BROWNOUT_DET_LVL;CONFIG_ESP_SYSTEM_BROWNOUT_INTR;CONFIG_ESP_SYSTEM_HW_STACK_GUARD;CONFIG_ESP_SYSTEM_HW_PC_RECORD;CONFIG_ESP_IPC_TASK_STACK_SIZE;CONFIG_IPC_TASK_STACK_SIZE;CONFIG_FREERTOS_SMP;CONFIG_FREERTOS_UNICORE;CONFIG_FREERTOS_HZ;CONFIG_FREERTOS_OPTIMIZED_SCHEDULER;CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE;CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL;CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY;CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS;CONFIG_FREERTOS_IDLE_TASK_STACKSIZE;CONFIG_FREERTOS_USE_IDLE_HOOK;CONFIG_FREERTOS_USE_TICK_HOOK;CONFIG_FREERTOS_MAX_TASK_NAME_LEN;CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY;CONFIG_FREERTOS_USE_TIMERS;CONFIG_FREERTOS_TIMER_SERVICE_TASK_NAME;CONFIG_FREERTOS_TIMER_TASK_AFFINITY_CPU0;CONFIG_FREERTOS_TIMER_TASK_NO_AFFINITY;CONFIG_FREERTOS_TIMER_SERVICE_TASK_CORE_AFFINITY;CONFIG_FREERTOS_TIMER_TASK_PRIORITY;CONFIG_TIMER_TASK_PRIORITY;CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH;CONFIG_TIMER_TASK_STACK_DEPTH;CONFIG_FREERTOS_TIMER_QUEUE_LENGTH;CONFIG_TIMER_QUEUE_LENGTH;CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE;CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES;CONFIG_FREERTOS_USE_TRACE_FACILITY;CONFIG_FREERTOS_USE_LIST_DATA_INTEGRITY_CHECK_BYTES;CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS;CONFIG_FREERTOS_USE_APPLICATION_TASK_TAG;CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER;CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK;CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS;CONFIG_FREERTOS_TASK_PRE_DELETION_HOOK;CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP;CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK;CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER;CONFIG_FREERTOS_ISR_STACKSIZE;CONFIG_FREERTOS_INTERRUPT_BACKTRACE;CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER;CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1;CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3;CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER;CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH;CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE;CONFIG_FREERTOS_PORT;CONFIG_FREERTOS_NO_AFFINITY;CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION;CONFIG_FREERTOS_DEBUG_OCDAWARE;CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT;CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH;CONFIG_FREERTOS_NUMBER_OF_CORES;CONFIG_HAL_ASSERTION_EQUALS_SYSTEM;CONFIG_HAL_ASSERTION_DISABLE;CONFIG_HAL_ASSERTION_SILENT;CONFIG_HAL_ASSERTION_SILIENT;CONFIG_HAL_ASSERTION_ENABLE;CONFIG_HAL_DEFAULT_ASSERTION_LEVEL;CONFIG_LOG_DEFAULT_LEVEL_NONE;CONFIG_LOG_DEFAULT_LEVEL_ERROR;CONFIG_LOG_DEFAULT_LEVEL_WARN;CONFIG_LOG_DEFAULT_LEVEL_INFO;CONFIG_LOG_DEFAULT_LEVEL_DEBUG;CONFIG_LOG_DEFAULT_LEVEL_VERBOSE;CONFIG_LOG_DEFAULT_LEVEL;CONFIG_LOG_MAXIMUM_EQUALS_DEFAULT;CONFIG_LOG_MAXIMUM_LEVEL_DEBUG;CONFIG_LOG_MAXIMUM_LEVEL_VERBOSE;CONFIG_LOG_MAXIMUM_LEVEL;CONFIG_LOG_MASTER_LEVEL;CONFIG_LOG_DYNAMIC_LEVEL_CONTROL;CONFIG_LOG_TAG_LEVEL_IMPL_NONE;CONFIG_LOG_TAG_LEVEL_IMPL_LINKED_LIST;CONFIG_LOG_TAG_LEVEL_IMPL_CACHE_AND_LINKED_LIST;CONFIG_LOG_TAG_LEVEL_CACHE_ARRAY;CONFIG_LOG_TAG_LEVEL_CACHE_BINARY_MIN_HEAP;CONFIG_LOG_TAG_LEVEL_IMPL_CACHE_SIZE;CONFIG_LOG_COLORS;CONFIG_LOG_TIMESTAMP_SOURCE_RTOS;CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM;CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF;CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF;CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR;CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF;CONFIG_NEWLIB_STDIN_LINE_ENDING_LF;CONFIG_NEWLIB_STDIN_LINE_ENDING_CR;CONFIG_NEWLIB_NANO_FORMAT;CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT;CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC_SYSTIMER;CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC;CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC;CONFIG_NEWLIB_TIME_SYSCALL_USE_HRT;CONFIG_ESP32C3_TIME_SYSCALL_USE_SYSTIMER;CONFIG_NEWLIB_TIME_SYSCALL_USE_NONE;CONFIG_ESP32C3_TIME_SYSCALL_USE_NONE;CONFIG_MMU_PAGE_SIZE_64KB;CONFIG_MMU_PAGE_MODE;CONFIG_MMU_PAGE_SIZE;CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC;CONFIG_SPI_FLASH_BROWNOUT_RESET;CONFIG_SPI_FLASH_AUTO_SUSPEND;CONFIG_SPI_FLASH_SUSPEND_TSUS_VAL_US;CONFIG_SPI_FLASH_FORCE_ENABLE_XMC_C_SUSPEND;CONFIG_SPI_FLASH_VERIFY_WRITE;CONFIG_SPI_FLASH_ENABLE_COUNTERS;CONFIG_SPI_FLASH_ROM_DRIVER_PATCH;CONFIG_SPI_FLASH_ROM_IMPL;CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS;CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS;CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS;CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS;CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED;CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED;CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE;CONFIG_SPI_FLASH_YIELD_DURING_ERASE;CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS;CONFIG_SPI_FLASH_ERASE_YIELD_TICKS;CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE;CONFIG_SPI_FLASH_SIZE_OVERRIDE;CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED;CONFIG_SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST;CONFIG_SPI_FLASH_VENDOR_XMC_SUPPORTED;CONFIG_SPI_FLASH_VENDOR_GD_SUPPORTED;CONFIG_SPI_FLASH_VENDOR_ISSI_SUPPORTED;CONFIG_SPI_FLASH_VENDOR_MXIC_SUPPORTED;CONFIG_SPI_FLASH_VENDOR_WINBOND_SUPPORTED;CONFIG_SPI_FLASH_VENDOR_BOYA_SUPPORTED;CONFIG_SPI_FLASH_VENDOR_TH_SUPPORTED;CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP;CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP;CONFIG_SPI_FLASH_SUPPORT_GD_CHIP;CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP;CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP;CONFIG_SPI_FLASH_SUPPORT_TH_CHIP;CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE;CONFIG_IDF_EXPERIMENTAL_FEATURES)
+# List of deprecated options for backward compatibility
+set(CONFIG_APP_BUILD_TYPE_ELF_RAM "")
+set(CONFIG_NO_BLOBS "")
+set(CONFIG_LOG_BOOTLOADER_LEVEL_NONE "")
+set(CONFIG_LOG_BOOTLOADER_LEVEL_ERROR "")
+set(CONFIG_LOG_BOOTLOADER_LEVEL_WARN "")
+set(CONFIG_LOG_BOOTLOADER_LEVEL_INFO "y")
+set(CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG "")
+set(CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE "")
+set(CONFIG_LOG_BOOTLOADER_LEVEL "3")
+set(CONFIG_APP_ROLLBACK_ENABLE "")
+set(CONFIG_FLASH_ENCRYPTION_ENABLED "")
+set(CONFIG_FLASHMODE_QIO "")
+set(CONFIG_FLASHMODE_QOUT "")
+set(CONFIG_FLASHMODE_DIO "y")
+set(CONFIG_FLASHMODE_DOUT "")
+set(CONFIG_MONITOR_BAUD "115200")
+set(CONFIG_OPTIMIZATION_LEVEL_DEBUG "y")
+set(CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG "y")
+set(CONFIG_COMPILER_OPTIMIZATION_DEFAULT "y")
+set(CONFIG_OPTIMIZATION_LEVEL_RELEASE "")
+set(CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE "")
+set(CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED "y")
+set(CONFIG_OPTIMIZATION_ASSERTIONS_SILENT "")
+set(CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED "")
+set(CONFIG_OPTIMIZATION_ASSERTION_LEVEL "2")
+set(CONFIG_CXX_EXCEPTIONS "")
+set(CONFIG_STACK_CHECK_NONE "y")
+set(CONFIG_STACK_CHECK_NORM "")
+set(CONFIG_STACK_CHECK_STRONG "")
+set(CONFIG_STACK_CHECK_ALL "")
+set(CONFIG_WARN_WRITE_STRINGS "")
+set(CONFIG_ESP_SYSTEM_PD_FLASH "")
+set(CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND "y")
+set(CONFIG_ESP32C3_RTC_CLK_SRC_INT_RC "y")
+set(CONFIG_ESP32C3_RTC_CLK_SRC_EXT_CRYS "")
+set(CONFIG_ESP32C3_RTC_CLK_SRC_EXT_OSC "")
+set(CONFIG_ESP32C3_RTC_CLK_SRC_INT_8MD256 "")
+set(CONFIG_ESP32C3_RTC_CLK_CAL_CYCLES "1024")
+set(CONFIG_ESP32C3_DEFAULT_CPU_FREQ_80 "")
+set(CONFIG_ESP32C3_DEFAULT_CPU_FREQ_160 "y")
+set(CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ "160")
+set(CONFIG_ESP32C3_MEMPROT_FEATURE "y")
+set(CONFIG_ESP32C3_MEMPROT_FEATURE_LOCK "y")
+set(CONFIG_SYSTEM_EVENT_QUEUE_SIZE "32")
+set(CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE "2304")
+set(CONFIG_MAIN_TASK_STACK_SIZE "3584")
+set(CONFIG_CONSOLE_UART_DEFAULT "y")
+set(CONFIG_CONSOLE_UART_CUSTOM "")
+set(CONFIG_CONSOLE_UART_NONE "")
+set(CONFIG_ESP_CONSOLE_UART_NONE "")
+set(CONFIG_CONSOLE_UART "y")
+set(CONFIG_CONSOLE_UART_NUM "0")
+set(CONFIG_CONSOLE_UART_BAUDRATE "115200")
+set(CONFIG_INT_WDT "y")
+set(CONFIG_INT_WDT_TIMEOUT_MS "300")
+set(CONFIG_TASK_WDT "y")
+set(CONFIG_ESP_TASK_WDT "y")
+set(CONFIG_TASK_WDT_PANIC "")
+set(CONFIG_TASK_WDT_TIMEOUT_S "5")
+set(CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0 "y")
+set(CONFIG_ESP32_DEBUG_STUBS_ENABLE "")
+set(CONFIG_ESP32C3_DEBUG_OCDAWARE "y")
+set(CONFIG_BROWNOUT_DET "y")
+set(CONFIG_ESP32C3_BROWNOUT_DET "y")
+set(CONFIG_BROWNOUT_DET_LVL_SEL_7 "y")
+set(CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_7 "y")
+set(CONFIG_BROWNOUT_DET_LVL_SEL_6 "")
+set(CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_6 "")
+set(CONFIG_BROWNOUT_DET_LVL_SEL_5 "")
+set(CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_5 "")
+set(CONFIG_BROWNOUT_DET_LVL_SEL_4 "")
+set(CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_4 "")
+set(CONFIG_BROWNOUT_DET_LVL_SEL_3 "")
+set(CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_3 "")
+set(CONFIG_BROWNOUT_DET_LVL_SEL_2 "")
+set(CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_2 "")
+set(CONFIG_BROWNOUT_DET_LVL "7")
+set(CONFIG_ESP32C3_BROWNOUT_DET_LVL "7")
+set(CONFIG_IPC_TASK_STACK_SIZE "1024")
+set(CONFIG_TIMER_TASK_PRIORITY "1")
+set(CONFIG_TIMER_TASK_STACK_DEPTH "2048")
+set(CONFIG_TIMER_QUEUE_LENGTH "10")
+set(CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK "")
+set(CONFIG_HAL_ASSERTION_SILIENT "")
+set(CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC_SYSTIMER "y")
+set(CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC "")
+set(CONFIG_ESP32C3_TIME_SYSCALL_USE_SYSTIMER "")
+set(CONFIG_ESP32C3_TIME_SYSCALL_USE_NONE "")
+set(CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS "y")
+set(CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS "")
+set(CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED "")
diff --git a/ESP32-IDF_ESPNOW-Receiver/build/bootloader/config/sdkconfig.h b/ESP32-IDF_ESPNOW-Receiver/build/bootloader/config/sdkconfig.h
new file mode 100644
index 000000000..208a84ea4
--- /dev/null
+++ b/ESP32-IDF_ESPNOW-Receiver/build/bootloader/config/sdkconfig.h
@@ -0,0 +1,548 @@
+/*
+ * Automatically generated file. DO NOT EDIT.
+ * Espressif IoT Development Framework (ESP-IDF) 5.4.1 Configuration Header
+ */
+#pragma once
+#define CONFIG_SOC_ADC_SUPPORTED 1
+#define CONFIG_SOC_DEDICATED_GPIO_SUPPORTED 1
+#define CONFIG_SOC_UART_SUPPORTED 1
+#define CONFIG_SOC_GDMA_SUPPORTED 1
+#define CONFIG_SOC_AHB_GDMA_SUPPORTED 1
+#define CONFIG_SOC_GPTIMER_SUPPORTED 1
+#define CONFIG_SOC_TWAI_SUPPORTED 1
+#define CONFIG_SOC_BT_SUPPORTED 1
+#define CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED 1
+#define CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED 1
+#define CONFIG_SOC_TEMP_SENSOR_SUPPORTED 1
+#define CONFIG_SOC_XT_WDT_SUPPORTED 1
+#define CONFIG_SOC_PHY_SUPPORTED 1
+#define CONFIG_SOC_WIFI_SUPPORTED 1
+#define CONFIG_SOC_SUPPORTS_SECURE_DL_MODE 1
+#define CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD 1
+#define CONFIG_SOC_EFUSE_HAS_EFUSE_RST_BUG 1
+#define CONFIG_SOC_EFUSE_SUPPORTED 1
+#define CONFIG_SOC_RTC_FAST_MEM_SUPPORTED 1
+#define CONFIG_SOC_RTC_MEM_SUPPORTED 1
+#define CONFIG_SOC_I2S_SUPPORTED 1
+#define CONFIG_SOC_RMT_SUPPORTED 1
+#define CONFIG_SOC_SDM_SUPPORTED 1
+#define CONFIG_SOC_GPSPI_SUPPORTED 1
+#define CONFIG_SOC_LEDC_SUPPORTED 1
+#define CONFIG_SOC_I2C_SUPPORTED 1
+#define CONFIG_SOC_SYSTIMER_SUPPORTED 1
+#define CONFIG_SOC_SUPPORT_COEXISTENCE 1
+#define CONFIG_SOC_AES_SUPPORTED 1
+#define CONFIG_SOC_MPI_SUPPORTED 1
+#define CONFIG_SOC_SHA_SUPPORTED 1
+#define CONFIG_SOC_HMAC_SUPPORTED 1
+#define CONFIG_SOC_DIG_SIGN_SUPPORTED 1
+#define CONFIG_SOC_FLASH_ENC_SUPPORTED 1
+#define CONFIG_SOC_SECURE_BOOT_SUPPORTED 1
+#define CONFIG_SOC_MEMPROT_SUPPORTED 1
+#define CONFIG_SOC_BOD_SUPPORTED 1
+#define CONFIG_SOC_CLK_TREE_SUPPORTED 1
+#define CONFIG_SOC_ASSIST_DEBUG_SUPPORTED 1
+#define CONFIG_SOC_WDT_SUPPORTED 1
+#define CONFIG_SOC_SPI_FLASH_SUPPORTED 1
+#define CONFIG_SOC_RNG_SUPPORTED 1
+#define CONFIG_SOC_LIGHT_SLEEP_SUPPORTED 1
+#define CONFIG_SOC_DEEP_SLEEP_SUPPORTED 1
+#define CONFIG_SOC_LP_PERIPH_SHARE_INTERRUPT 1
+#define CONFIG_SOC_PM_SUPPORTED 1
+#define CONFIG_SOC_XTAL_SUPPORT_40M 1
+#define CONFIG_SOC_AES_SUPPORT_DMA 1
+#define CONFIG_SOC_AES_GDMA 1
+#define CONFIG_SOC_AES_SUPPORT_AES_128 1
+#define CONFIG_SOC_AES_SUPPORT_AES_256 1
+#define CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED 1
+#define CONFIG_SOC_ADC_ARBITER_SUPPORTED 1
+#define CONFIG_SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
+#define CONFIG_SOC_ADC_MONITOR_SUPPORTED 1
+#define CONFIG_SOC_ADC_DMA_SUPPORTED 1
+#define CONFIG_SOC_ADC_PERIPH_NUM 2
+#define CONFIG_SOC_ADC_MAX_CHANNEL_NUM 5
+#define CONFIG_SOC_ADC_ATTEN_NUM 4
+#define CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM 1
+#define CONFIG_SOC_ADC_PATT_LEN_MAX 8
+#define CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH 12
+#define CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH 12
+#define CONFIG_SOC_ADC_DIGI_RESULT_BYTES 4
+#define CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV 4
+#define CONFIG_SOC_ADC_DIGI_IIR_FILTER_NUM 2
+#define CONFIG_SOC_ADC_DIGI_MONITOR_NUM 2
+#define CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
+#define CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
+#define CONFIG_SOC_ADC_RTC_MIN_BITWIDTH 12
+#define CONFIG_SOC_ADC_RTC_MAX_BITWIDTH 12
+#define CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED 1
+#define CONFIG_SOC_ADC_SELF_HW_CALI_SUPPORTED 1
+#define CONFIG_SOC_ADC_SHARED_POWER 1
+#define CONFIG_SOC_APB_BACKUP_DMA 1
+#define CONFIG_SOC_BROWNOUT_RESET_SUPPORTED 1
+#define CONFIG_SOC_SHARED_IDCACHE_SUPPORTED 1
+#define CONFIG_SOC_CACHE_MEMORY_IBANK_SIZE 0x4000
+#define CONFIG_SOC_CPU_CORES_NUM 1
+#define CONFIG_SOC_CPU_INTR_NUM 32
+#define CONFIG_SOC_CPU_HAS_FLEXIBLE_INTC 1
+#define CONFIG_SOC_CPU_HAS_CSR_PC 1
+#define CONFIG_SOC_CPU_BREAKPOINTS_NUM 8
+#define CONFIG_SOC_CPU_WATCHPOINTS_NUM 8
+#define CONFIG_SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000
+#define CONFIG_SOC_DS_SIGNATURE_MAX_BIT_LEN 3072
+#define CONFIG_SOC_DS_KEY_PARAM_MD_IV_LENGTH 16
+#define CONFIG_SOC_DS_KEY_CHECK_MAX_WAIT_US 1100
+#define CONFIG_SOC_AHB_GDMA_VERSION 1
+#define CONFIG_SOC_GDMA_NUM_GROUPS_MAX 1
+#define CONFIG_SOC_GDMA_PAIRS_PER_GROUP_MAX 3
+#define CONFIG_SOC_GPIO_PORT 1
+#define CONFIG_SOC_GPIO_PIN_COUNT 22
+#define CONFIG_SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
+#define CONFIG_SOC_GPIO_FILTER_CLK_SUPPORT_APB 1
+#define CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD 1
+#define CONFIG_SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP 1
+#define CONFIG_SOC_GPIO_IN_RANGE_MAX 21
+#define CONFIG_SOC_GPIO_OUT_RANGE_MAX 21
+#define CONFIG_SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK 0
+#define CONFIG_SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT 6
+#define CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000003FFFC0
+#define CONFIG_SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX 1
+#define CONFIG_SOC_GPIO_CLOCKOUT_CHANNEL_NUM 3
+#define CONFIG_SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP 1
+#define CONFIG_SOC_DEDIC_GPIO_OUT_CHANNELS_NUM 8
+#define CONFIG_SOC_DEDIC_GPIO_IN_CHANNELS_NUM 8
+#define CONFIG_SOC_DEDIC_PERIPH_ALWAYS_ENABLE 1
+#define CONFIG_SOC_I2C_NUM 1
+#define CONFIG_SOC_HP_I2C_NUM 1
+#define CONFIG_SOC_I2C_FIFO_LEN 32
+#define CONFIG_SOC_I2C_CMD_REG_NUM 8
+#define CONFIG_SOC_I2C_SUPPORT_SLAVE 1
+#define CONFIG_SOC_I2C_SUPPORT_HW_CLR_BUS 1
+#define CONFIG_SOC_I2C_SUPPORT_XTAL 1
+#define CONFIG_SOC_I2C_SUPPORT_RTC 1
+#define CONFIG_SOC_I2C_SUPPORT_10BIT_ADDR 1
+#define CONFIG_SOC_I2C_SLAVE_SUPPORT_BROADCAST 1
+#define CONFIG_SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE 1
+#define CONFIG_SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS 1
+#define CONFIG_SOC_I2S_NUM 1
+#define CONFIG_SOC_I2S_HW_VERSION_2 1
+#define CONFIG_SOC_I2S_SUPPORTS_XTAL 1
+#define CONFIG_SOC_I2S_SUPPORTS_PLL_F160M 1
+#define CONFIG_SOC_I2S_SUPPORTS_PCM 1
+#define CONFIG_SOC_I2S_SUPPORTS_PDM 1
+#define CONFIG_SOC_I2S_SUPPORTS_PDM_TX 1
+#define CONFIG_SOC_I2S_PDM_MAX_TX_LINES 2
+#define CONFIG_SOC_I2S_SUPPORTS_TDM 1
+#define CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK 1
+#define CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK 1
+#define CONFIG_SOC_LEDC_TIMER_NUM 4
+#define CONFIG_SOC_LEDC_CHANNEL_NUM 6
+#define CONFIG_SOC_LEDC_TIMER_BIT_WIDTH 14
+#define CONFIG_SOC_LEDC_SUPPORT_FADE_STOP 1
+#define CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM 1
+#define CONFIG_SOC_MMU_PERIPH_NUM 1
+#define CONFIG_SOC_MPU_MIN_REGION_SIZE 0x20000000
+#define CONFIG_SOC_MPU_REGIONS_MAX_NUM 8
+#define CONFIG_SOC_RMT_GROUPS 1
+#define CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP 2
+#define CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP 2
+#define CONFIG_SOC_RMT_CHANNELS_PER_GROUP 4
+#define CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL 48
+#define CONFIG_SOC_RMT_SUPPORT_RX_PINGPONG 1
+#define CONFIG_SOC_RMT_SUPPORT_RX_DEMODULATION 1
+#define CONFIG_SOC_RMT_SUPPORT_TX_ASYNC_STOP 1
+#define CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT 1
+#define CONFIG_SOC_RMT_SUPPORT_TX_SYNCHRO 1
+#define CONFIG_SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY 1
+#define CONFIG_SOC_RMT_SUPPORT_XTAL 1
+#define CONFIG_SOC_RMT_SUPPORT_APB 1
+#define CONFIG_SOC_RMT_SUPPORT_RC_FAST 1
+#define CONFIG_SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH 128
+#define CONFIG_SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM 108
+#define CONFIG_SOC_SLEEP_SYSTIMER_STALL_WORKAROUND 1
+#define CONFIG_SOC_SLEEP_TGWDT_STOP_WORKAROUND 1
+#define CONFIG_SOC_RTCIO_PIN_COUNT 0
+#define CONFIG_SOC_MPI_MEM_BLOCKS_NUM 4
+#define CONFIG_SOC_MPI_OPERATIONS_NUM 3
+#define CONFIG_SOC_RSA_MAX_BIT_LEN 3072
+#define CONFIG_SOC_SHA_DMA_MAX_BUFFER_SIZE 3968
+#define CONFIG_SOC_SHA_SUPPORT_DMA 1
+#define CONFIG_SOC_SHA_SUPPORT_RESUME 1
+#define CONFIG_SOC_SHA_GDMA 1
+#define CONFIG_SOC_SHA_SUPPORT_SHA1 1
+#define CONFIG_SOC_SHA_SUPPORT_SHA224 1
+#define CONFIG_SOC_SHA_SUPPORT_SHA256 1
+#define CONFIG_SOC_SDM_GROUPS 1
+#define CONFIG_SOC_SDM_CHANNELS_PER_GROUP 4
+#define CONFIG_SOC_SDM_CLK_SUPPORT_APB 1
+#define CONFIG_SOC_SPI_PERIPH_NUM 2
+#define CONFIG_SOC_SPI_MAX_CS_NUM 6
+#define CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE 64
+#define CONFIG_SOC_SPI_SUPPORT_DDRCLK 1
+#define CONFIG_SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
+#define CONFIG_SOC_SPI_SUPPORT_CD_SIG 1
+#define CONFIG_SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
+#define CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
+#define CONFIG_SOC_SPI_SUPPORT_CLK_APB 1
+#define CONFIG_SOC_SPI_SUPPORT_CLK_XTAL 1
+#define CONFIG_SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT 1
+#define CONFIG_SOC_SPI_SCT_SUPPORTED 1
+#define CONFIG_SOC_SPI_SCT_REG_NUM 14
+#define CONFIG_SOC_SPI_SCT_BUFFER_NUM_MAX 1
+#define CONFIG_SOC_SPI_SCT_CONF_BITLEN_MAX 0x3FFFA
+#define CONFIG_SOC_MEMSPI_IS_INDEPENDENT 1
+#define CONFIG_SOC_SPI_MAX_PRE_DIVIDER 16
+#define CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE 1
+#define CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND 1
+#define CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_RESUME 1
+#define CONFIG_SOC_SPI_MEM_SUPPORT_IDLE_INTR 1
+#define CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND 1
+#define CONFIG_SOC_SPI_MEM_SUPPORT_CHECK_SUS 1
+#define CONFIG_SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE 1
+#define CONFIG_SOC_SPI_MEM_SUPPORT_WRAP 1
+#define CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
+#define CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1
+#define CONFIG_SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED 1
+#define CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
+#define CONFIG_SOC_SYSTIMER_COUNTER_NUM 2
+#define CONFIG_SOC_SYSTIMER_ALARM_NUM 3
+#define CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO 32
+#define CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI 20
+#define CONFIG_SOC_SYSTIMER_FIXED_DIVIDER 1
+#define CONFIG_SOC_SYSTIMER_INT_LEVEL 1
+#define CONFIG_SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1
+#define CONFIG_SOC_TIMER_GROUPS 2
+#define CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP 1
+#define CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH 54
+#define CONFIG_SOC_TIMER_GROUP_SUPPORT_XTAL 1
+#define CONFIG_SOC_TIMER_GROUP_SUPPORT_APB 1
+#define CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS 2
+#define CONFIG_SOC_LP_TIMER_BIT_WIDTH_LO 32
+#define CONFIG_SOC_LP_TIMER_BIT_WIDTH_HI 16
+#define CONFIG_SOC_MWDT_SUPPORT_XTAL 1
+#define CONFIG_SOC_TWAI_CONTROLLER_NUM 1
+#define CONFIG_SOC_TWAI_CLK_SUPPORT_APB 1
+#define CONFIG_SOC_TWAI_BRP_MIN 2
+#define CONFIG_SOC_TWAI_BRP_MAX 16384
+#define CONFIG_SOC_TWAI_SUPPORTS_RX_STATUS 1
+#define CONFIG_SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
+#define CONFIG_SOC_EFUSE_DIS_PAD_JTAG 1
+#define CONFIG_SOC_EFUSE_DIS_USB_JTAG 1
+#define CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT 1
+#define CONFIG_SOC_EFUSE_SOFT_DIS_JTAG 1
+#define CONFIG_SOC_EFUSE_DIS_ICACHE 1
+#define CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1
+#define CONFIG_SOC_SECURE_BOOT_V2_RSA 1
+#define CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
+#define CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
+#define CONFIG_SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
+#define CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX 32
+#define CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES 1
+#define CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128 1
+#define CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE 16
+#define CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE 512
+#define CONFIG_SOC_UART_NUM 2
+#define CONFIG_SOC_UART_HP_NUM 2
+#define CONFIG_SOC_UART_FIFO_LEN 128
+#define CONFIG_SOC_UART_BITRATE_MAX 5000000
+#define CONFIG_SOC_UART_SUPPORT_APB_CLK 1
+#define CONFIG_SOC_UART_SUPPORT_RTC_CLK 1
+#define CONFIG_SOC_UART_SUPPORT_XTAL_CLK 1
+#define CONFIG_SOC_UART_SUPPORT_WAKEUP_INT 1
+#define CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND 1
+#define CONFIG_SOC_COEX_HW_PTI 1
+#define CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE 21
+#define CONFIG_SOC_MAC_BB_PD_MEM_SIZE 192
+#define CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH 12
+#define CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP 1
+#define CONFIG_SOC_PM_SUPPORT_BT_WAKEUP 1
+#define CONFIG_SOC_PM_SUPPORT_CPU_PD 1
+#define CONFIG_SOC_PM_SUPPORT_WIFI_PD 1
+#define CONFIG_SOC_PM_SUPPORT_BT_PD 1
+#define CONFIG_SOC_PM_SUPPORT_RC_FAST_PD 1
+#define CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD 1
+#define CONFIG_SOC_PM_SUPPORT_MAC_BB_PD 1
+#define CONFIG_SOC_PM_CPU_RETENTION_BY_RTCCNTL 1
+#define CONFIG_SOC_PM_MODEM_RETENTION_BY_BACKUPDMA 1
+#define CONFIG_SOC_PM_MODEM_PD_BY_SW 1
+#define CONFIG_SOC_CLK_RC_FAST_D256_SUPPORTED 1
+#define CONFIG_SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256 1
+#define CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION 1
+#define CONFIG_SOC_CLK_XTAL32K_SUPPORTED 1
+#define CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC 1
+#define CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL 1
+#define CONFIG_SOC_WIFI_HW_TSF 1
+#define CONFIG_SOC_WIFI_FTM_SUPPORT 1
+#define CONFIG_SOC_WIFI_GCMP_SUPPORT 1
+#define CONFIG_SOC_WIFI_WAPI_SUPPORT 1
+#define CONFIG_SOC_WIFI_CSI_SUPPORT 1
+#define CONFIG_SOC_WIFI_MESH_SUPPORT 1
+#define CONFIG_SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW 1
+#define CONFIG_SOC_WIFI_PHY_NEEDS_USB_WORKAROUND 1
+#define CONFIG_SOC_BLE_SUPPORTED 1
+#define CONFIG_SOC_BLE_MESH_SUPPORTED 1
+#define CONFIG_SOC_BLE_50_SUPPORTED 1
+#define CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED 1
+#define CONFIG_SOC_BLUFI_SUPPORTED 1
+#define CONFIG_SOC_PHY_COMBO_MODULE 1
+#define CONFIG_IDF_CMAKE 1
+#define CONFIG_IDF_TOOLCHAIN "gcc"
+#define CONFIG_IDF_TOOLCHAIN_GCC 1
+#define CONFIG_IDF_TARGET_ARCH_RISCV 1
+#define CONFIG_IDF_TARGET_ARCH "riscv"
+#define CONFIG_IDF_TARGET "esp32c3"
+#define CONFIG_IDF_INIT_VERSION "5.4.1"
+#define CONFIG_IDF_TARGET_ESP32C3 1
+#define CONFIG_IDF_FIRMWARE_CHIP_ID 0x0005
+#define CONFIG_APP_BUILD_TYPE_APP_2NDBOOT 1
+#define CONFIG_APP_BUILD_GENERATE_BINARIES 1
+#define CONFIG_APP_BUILD_BOOTLOADER 1
+#define CONFIG_APP_BUILD_USE_FLASH_SECTIONS 1
+#define CONFIG_BOOTLOADER_COMPILE_TIME_DATE 1
+#define CONFIG_BOOTLOADER_PROJECT_VER 1
+#define CONFIG_BOOTLOADER_OFFSET_IN_FLASH 0x0
+#define CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE 1
+#define CONFIG_BOOTLOADER_LOG_LEVEL_INFO 1
+#define CONFIG_BOOTLOADER_LOG_LEVEL 3
+#define CONFIG_BOOTLOADER_LOG_TIMESTAMP_SOURCE_CPU_TICKS 1
+#define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1
+#define CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE 1
+#define CONFIG_BOOTLOADER_WDT_ENABLE 1
+#define CONFIG_BOOTLOADER_WDT_TIME_MS 9000
+#define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x0
+#define CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED 1
+#define CONFIG_SECURE_BOOT_V2_PREFERRED 1
+#define CONFIG_SECURE_ROM_DL_MODE_ENABLED 1
+#define CONFIG_APP_COMPILE_TIME_DATE 1
+#define CONFIG_APP_RETRIEVE_LEN_ELF_SHA 9
+#define CONFIG_ESP_ROM_HAS_CRC_LE 1
+#define CONFIG_ESP_ROM_HAS_CRC_BE 1
+#define CONFIG_ESP_ROM_HAS_MZ_CRC32 1
+#define CONFIG_ESP_ROM_HAS_JPEG_DECODE 1
+#define CONFIG_ESP_ROM_UART_CLK_IS_XTAL 1
+#define CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM 3
+#define CONFIG_ESP_ROM_HAS_RETARGETABLE_LOCKING 1
+#define CONFIG_ESP_ROM_HAS_ERASE_0_REGION_BUG 1
+#define CONFIG_ESP_ROM_HAS_ENCRYPTED_WRITES_USING_LEGACY_DRV 1
+#define CONFIG_ESP_ROM_GET_CLK_FREQ 1
+#define CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND 1
+#define CONFIG_ESP_ROM_HAS_LAYOUT_TABLE 1
+#define CONFIG_ESP_ROM_HAS_SPI_FLASH 1
+#define CONFIG_ESP_ROM_HAS_ETS_PRINTF_BUG 1
+#define CONFIG_ESP_ROM_HAS_NEWLIB 1
+#define CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT 1
+#define CONFIG_ESP_ROM_HAS_NEWLIB_32BIT_TIME 1
+#define CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE 1
+#define CONFIG_ESP_ROM_RAM_APP_NEEDS_MMU_INIT 1
+#define CONFIG_ESP_ROM_HAS_SW_FLOAT 1
+#define CONFIG_ESP_ROM_USB_OTG_NUM -1
+#define CONFIG_ESP_ROM_HAS_VERSION 1
+#define CONFIG_ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB 1
+#define CONFIG_BOOT_ROM_LOG_ALWAYS_ON 1
+#define CONFIG_ESPTOOLPY_FLASHMODE_DIO 1
+#define CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR 1
+#define CONFIG_ESPTOOLPY_FLASHMODE "dio"
+#define CONFIG_ESPTOOLPY_FLASHFREQ_80M 1
+#define CONFIG_ESPTOOLPY_FLASHFREQ "80m"
+#define CONFIG_ESPTOOLPY_FLASHSIZE_2MB 1
+#define CONFIG_ESPTOOLPY_FLASHSIZE "2MB"
+#define CONFIG_ESPTOOLPY_BEFORE_RESET 1
+#define CONFIG_ESPTOOLPY_BEFORE "default_reset"
+#define CONFIG_ESPTOOLPY_AFTER_RESET 1
+#define CONFIG_ESPTOOLPY_AFTER "hard_reset"
+#define CONFIG_ESPTOOLPY_MONITOR_BAUD 115200
+#define CONFIG_PARTITION_TABLE_SINGLE_APP 1
+#define CONFIG_PARTITION_TABLE_CUSTOM_FILENAME "partitions.csv"
+#define CONFIG_PARTITION_TABLE_FILENAME "partitions_singleapp.csv"
+#define CONFIG_PARTITION_TABLE_OFFSET 0x8000
+#define CONFIG_PARTITION_TABLE_MD5 1
+#define CONFIG_COMPILER_OPTIMIZATION_DEBUG 1
+#define CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE 1
+#define CONFIG_COMPILER_ASSERT_NDEBUG_EVALUATE 1
+#define CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB 1
+#define CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL 2
+#define CONFIG_COMPILER_HIDE_PATHS_MACROS 1
+#define CONFIG_COMPILER_STACK_CHECK_MODE_NONE 1
+#define CONFIG_COMPILER_DISABLE_DEFAULT_ERRORS 1
+#define CONFIG_COMPILER_RT_LIB_GCCLIB 1
+#define CONFIG_COMPILER_RT_LIB_NAME "gcc"
+#define CONFIG_COMPILER_ORPHAN_SECTIONS_WARNING 1
+#define CONFIG_EFUSE_MAX_BLK_LEN 256
+#define CONFIG_ESP_ERR_TO_NAME_LOOKUP 1
+#define CONFIG_ESP32C3_REV_MIN_3 1
+#define CONFIG_ESP32C3_REV_MIN_FULL 3
+#define CONFIG_ESP_REV_MIN_FULL 3
+#define CONFIG_ESP32C3_REV_MAX_FULL 199
+#define CONFIG_ESP_REV_MAX_FULL 199
+#define CONFIG_ESP_EFUSE_BLOCK_REV_MIN_FULL 0
+#define CONFIG_ESP_EFUSE_BLOCK_REV_MAX_FULL 199
+#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA 1
+#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP 1
+#define CONFIG_ESP_MAC_ADDR_UNIVERSE_BT 1
+#define CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH 1
+#define CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR 1
+#define CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES 4
+#define CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR 1
+#define CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES 4
+#define CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND 1
+#define CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND 1
+#define CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY 0
+#define CONFIG_ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS 1
+#define CONFIG_RTC_CLK_SRC_INT_RC 1
+#define CONFIG_RTC_CLK_CAL_CYCLES 1024
+#define CONFIG_PERIPH_CTRL_FUNC_IN_IRAM 1
+#define CONFIG_GDMA_CTRL_FUNC_IN_IRAM 1
+#define CONFIG_XTAL_FREQ_40 1
+#define CONFIG_XTAL_FREQ 40
+#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160 1
+#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 160
+#define CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT 1
+#define CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS 0
+#define CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE 1
+#define CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK 1
+#define CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP 1
+#define CONFIG_ESP_SYSTEM_MEMPROT_FEATURE 1
+#define CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK 1
+#define CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE 32
+#define CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE 2304
+#define CONFIG_ESP_MAIN_TASK_STACK_SIZE 3584
+#define CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0 1
+#define CONFIG_ESP_MAIN_TASK_AFFINITY 0x0
+#define CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE 2048
+#define CONFIG_ESP_CONSOLE_UART_DEFAULT 1
+#define CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG 1
+#define CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED 1
+#define CONFIG_ESP_CONSOLE_UART 1
+#define CONFIG_ESP_CONSOLE_UART_NUM 0
+#define CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM 0
+#define CONFIG_ESP_CONSOLE_UART_BAUDRATE 115200
+#define CONFIG_ESP_INT_WDT 1
+#define CONFIG_ESP_INT_WDT_TIMEOUT_MS 300
+#define CONFIG_ESP_TASK_WDT_EN 1
+#define CONFIG_ESP_TASK_WDT_INIT 1
+#define CONFIG_ESP_TASK_WDT_TIMEOUT_S 5
+#define CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 1
+#define CONFIG_ESP_DEBUG_OCDAWARE 1
+#define CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 1
+#define CONFIG_ESP_BROWNOUT_DET 1
+#define CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7 1
+#define CONFIG_ESP_BROWNOUT_DET_LVL 7
+#define CONFIG_ESP_SYSTEM_BROWNOUT_INTR 1
+#define CONFIG_ESP_SYSTEM_HW_STACK_GUARD 1
+#define CONFIG_ESP_SYSTEM_HW_PC_RECORD 1
+#define CONFIG_ESP_IPC_TASK_STACK_SIZE 1024
+#define CONFIG_FREERTOS_UNICORE 1
+#define CONFIG_FREERTOS_HZ 100
+#define CONFIG_FREERTOS_OPTIMIZED_SCHEDULER 1
+#define CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY 1
+#define CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS 1
+#define CONFIG_FREERTOS_IDLE_TASK_STACKSIZE 1536
+#define CONFIG_FREERTOS_MAX_TASK_NAME_LEN 16
+#define CONFIG_FREERTOS_USE_TIMERS 1
+#define CONFIG_FREERTOS_TIMER_SERVICE_TASK_NAME "Tmr Svc"
+#define CONFIG_FREERTOS_TIMER_TASK_NO_AFFINITY 1
+#define CONFIG_FREERTOS_TIMER_SERVICE_TASK_CORE_AFFINITY 0x7FFFFFFF
+#define CONFIG_FREERTOS_TIMER_TASK_PRIORITY 1
+#define CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH 2048
+#define CONFIG_FREERTOS_TIMER_QUEUE_LENGTH 10
+#define CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE 0
+#define CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES 1
+#define CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER 1
+#define CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS 1
+#define CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER 1
+#define CONFIG_FREERTOS_ISR_STACKSIZE 1536
+#define CONFIG_FREERTOS_INTERRUPT_BACKTRACE 1
+#define CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER 1
+#define CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1 1
+#define CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER 1
+#define CONFIG_FREERTOS_PORT 1
+#define CONFIG_FREERTOS_NO_AFFINITY 0x7FFFFFFF
+#define CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION 1
+#define CONFIG_FREERTOS_DEBUG_OCDAWARE 1
+#define CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT 1
+#define CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH 1
+#define CONFIG_FREERTOS_NUMBER_OF_CORES 1
+#define CONFIG_HAL_ASSERTION_EQUALS_SYSTEM 1
+#define CONFIG_HAL_DEFAULT_ASSERTION_LEVEL 2
+#define CONFIG_LOG_DEFAULT_LEVEL_INFO 1
+#define CONFIG_LOG_DEFAULT_LEVEL 3
+#define CONFIG_LOG_MAXIMUM_EQUALS_DEFAULT 1
+#define CONFIG_LOG_MAXIMUM_LEVEL 3
+#define CONFIG_LOG_DYNAMIC_LEVEL_CONTROL 1
+#define CONFIG_LOG_TAG_LEVEL_IMPL_CACHE_AND_LINKED_LIST 1
+#define CONFIG_LOG_TAG_LEVEL_CACHE_BINARY_MIN_HEAP 1
+#define CONFIG_LOG_TAG_LEVEL_IMPL_CACHE_SIZE 31
+#define CONFIG_LOG_TIMESTAMP_SOURCE_RTOS 1
+#define CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF 1
+#define CONFIG_NEWLIB_STDIN_LINE_ENDING_CR 1
+#define CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT 1
+#define CONFIG_MMU_PAGE_SIZE_64KB 1
+#define CONFIG_MMU_PAGE_MODE "64KB"
+#define CONFIG_MMU_PAGE_SIZE 0x10000
+#define CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC 1
+#define CONFIG_SPI_FLASH_BROWNOUT_RESET 1
+#define CONFIG_SPI_FLASH_SUSPEND_TSUS_VAL_US 50
+#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1
+#define CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS 1
+#define CONFIG_SPI_FLASH_YIELD_DURING_ERASE 1
+#define CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS 20
+#define CONFIG_SPI_FLASH_ERASE_YIELD_TICKS 1
+#define CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE 8192
+#define CONFIG_SPI_FLASH_VENDOR_XMC_SUPPORTED 1
+#define CONFIG_SPI_FLASH_VENDOR_GD_SUPPORTED 1
+#define CONFIG_SPI_FLASH_VENDOR_ISSI_SUPPORTED 1
+#define CONFIG_SPI_FLASH_VENDOR_MXIC_SUPPORTED 1
+#define CONFIG_SPI_FLASH_VENDOR_WINBOND_SUPPORTED 1
+#define CONFIG_SPI_FLASH_VENDOR_BOYA_SUPPORTED 1
+#define CONFIG_SPI_FLASH_VENDOR_TH_SUPPORTED 1
+#define CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP 1
+#define CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP 1
+#define CONFIG_SPI_FLASH_SUPPORT_GD_CHIP 1
+#define CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP 1
+#define CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP 1
+#define CONFIG_SPI_FLASH_SUPPORT_TH_CHIP 1
+#define CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE 1
+
+/* List of deprecated options */
+#define CONFIG_BROWNOUT_DET CONFIG_ESP_BROWNOUT_DET
+#define CONFIG_BROWNOUT_DET_LVL CONFIG_ESP_BROWNOUT_DET_LVL
+#define CONFIG_BROWNOUT_DET_LVL_SEL_7 CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7
+#define CONFIG_COMPILER_OPTIMIZATION_DEFAULT CONFIG_COMPILER_OPTIMIZATION_DEBUG
+#define CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG CONFIG_COMPILER_OPTIMIZATION_DEBUG
+#define CONFIG_CONSOLE_UART CONFIG_ESP_CONSOLE_UART
+#define CONFIG_CONSOLE_UART_BAUDRATE CONFIG_ESP_CONSOLE_UART_BAUDRATE
+#define CONFIG_CONSOLE_UART_DEFAULT CONFIG_ESP_CONSOLE_UART_DEFAULT
+#define CONFIG_CONSOLE_UART_NUM CONFIG_ESP_CONSOLE_UART_NUM
+#define CONFIG_ESP32C3_BROWNOUT_DET CONFIG_ESP_BROWNOUT_DET
+#define CONFIG_ESP32C3_BROWNOUT_DET_LVL CONFIG_ESP_BROWNOUT_DET_LVL
+#define CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_7 CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7
+#define CONFIG_ESP32C3_DEBUG_OCDAWARE CONFIG_ESP_DEBUG_OCDAWARE
+#define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_160 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160
+#define CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
+#define CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND
+#define CONFIG_ESP32C3_MEMPROT_FEATURE CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
+#define CONFIG_ESP32C3_MEMPROT_FEATURE_LOCK CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK
+#define CONFIG_ESP32C3_RTC_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES
+#define CONFIG_ESP32C3_RTC_CLK_SRC_INT_RC CONFIG_RTC_CLK_SRC_INT_RC
+#define CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC_SYSTIMER CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT
+#define CONFIG_ESP_TASK_WDT CONFIG_ESP_TASK_WDT_INIT
+#define CONFIG_FLASHMODE_DIO CONFIG_ESPTOOLPY_FLASHMODE_DIO
+#define CONFIG_INT_WDT CONFIG_ESP_INT_WDT
+#define CONFIG_INT_WDT_TIMEOUT_MS CONFIG_ESP_INT_WDT_TIMEOUT_MS
+#define CONFIG_IPC_TASK_STACK_SIZE CONFIG_ESP_IPC_TASK_STACK_SIZE
+#define CONFIG_LOG_BOOTLOADER_LEVEL CONFIG_BOOTLOADER_LOG_LEVEL
+#define CONFIG_LOG_BOOTLOADER_LEVEL_INFO CONFIG_BOOTLOADER_LOG_LEVEL_INFO
+#define CONFIG_MAIN_TASK_STACK_SIZE CONFIG_ESP_MAIN_TASK_STACK_SIZE
+#define CONFIG_MONITOR_BAUD CONFIG_ESPTOOLPY_MONITOR_BAUD
+#define CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE
+#define CONFIG_OPTIMIZATION_ASSERTION_LEVEL CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL
+#define CONFIG_OPTIMIZATION_LEVEL_DEBUG CONFIG_COMPILER_OPTIMIZATION_DEBUG
+#define CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS
+#define CONFIG_STACK_CHECK_NONE CONFIG_COMPILER_STACK_CHECK_MODE_NONE
+#define CONFIG_SYSTEM_EVENT_QUEUE_SIZE CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE
+#define CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE
+#define CONFIG_TASK_WDT CONFIG_ESP_TASK_WDT_INIT
+#define CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
+#define CONFIG_TASK_WDT_TIMEOUT_S CONFIG_ESP_TASK_WDT_TIMEOUT_S
+#define CONFIG_TIMER_QUEUE_LENGTH CONFIG_FREERTOS_TIMER_QUEUE_LENGTH
+#define CONFIG_TIMER_TASK_PRIORITY CONFIG_FREERTOS_TIMER_TASK_PRIORITY
+#define CONFIG_TIMER_TASK_STACK_DEPTH CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH
diff --git a/ESP32-IDF_ESPNOW-Receiver/build/bootloader/config/sdkconfig.json b/ESP32-IDF_ESPNOW-Receiver/build/bootloader/config/sdkconfig.json
new file mode 100644
index 000000000..9ff6ea23c
--- /dev/null
+++ b/ESP32-IDF_ESPNOW-Receiver/build/bootloader/config/sdkconfig.json
@@ -0,0 +1,659 @@
+{
+    "APP_BUILD_BOOTLOADER": true,
+    "APP_BUILD_GENERATE_BINARIES": true,
+    "APP_BUILD_TYPE_APP_2NDBOOT": true,
+    "APP_BUILD_TYPE_RAM": false,
+    "APP_BUILD_USE_FLASH_SECTIONS": true,
+    "APP_COMPILE_TIME_DATE": true,
+    "APP_EXCLUDE_PROJECT_NAME_VAR": false,
+    "APP_EXCLUDE_PROJECT_VER_VAR": false,
+    "APP_NO_BLOBS": false,
+    "APP_PROJECT_VER_FROM_CONFIG": false,
+    "APP_REPRODUCIBLE_BUILD": false,
+    "APP_RETRIEVE_LEN_ELF_SHA": 9,
+    "BOOTLOADER_APP_ROLLBACK_ENABLE": false,
+    "BOOTLOADER_APP_TEST": false,
+    "BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG": false,
+    "BOOTLOADER_COMPILER_OPTIMIZATION_NONE": false,
+    "BOOTLOADER_COMPILER_OPTIMIZATION_PERF": false,
+    "BOOTLOADER_COMPILER_OPTIMIZATION_SIZE": true,
+    "BOOTLOADER_COMPILE_TIME_DATE": true,
+    "BOOTLOADER_CUSTOM_RESERVE_RTC": false,
+    "BOOTLOADER_FACTORY_RESET": false,
+    "BOOTLOADER_FLASH_DC_AWARE": false,
+    "BOOTLOADER_FLASH_XMC_SUPPORT": true,
+    "BOOTLOADER_LOG_COLORS": false,
+    "BOOTLOADER_LOG_LEVEL": 3,
+    "BOOTLOADER_LOG_LEVEL_DEBUG": false,
+    "BOOTLOADER_LOG_LEVEL_ERROR": false,
+    "BOOTLOADER_LOG_LEVEL_INFO": true,
+    "BOOTLOADER_LOG_LEVEL_NONE": false,
+    "BOOTLOADER_LOG_LEVEL_VERBOSE": false,
+    "BOOTLOADER_LOG_LEVEL_WARN": false,
+    "BOOTLOADER_LOG_TIMESTAMP_SOURCE_CPU_TICKS": true,
+    "BOOTLOADER_OFFSET_IN_FLASH": 0,
+    "BOOTLOADER_PROJECT_VER": 1,
+    "BOOTLOADER_REGION_PROTECTION_ENABLE": true,
+    "BOOTLOADER_RESERVE_RTC_SIZE": 0,
+    "BOOTLOADER_SKIP_VALIDATE_ALWAYS": false,
+    "BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP": false,
+    "BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON": false,
+    "BOOTLOADER_WDT_DISABLE_IN_USER_CODE": false,
+    "BOOTLOADER_WDT_ENABLE": true,
+    "BOOTLOADER_WDT_TIME_MS": 9000,
+    "BOOT_ROM_LOG_ALWAYS_OFF": false,
+    "BOOT_ROM_LOG_ALWAYS_ON": true,
+    "BOOT_ROM_LOG_ON_GPIO_HIGH": false,
+    "BOOT_ROM_LOG_ON_GPIO_LOW": false,
+    "COMPILER_ASSERT_NDEBUG_EVALUATE": true,
+    "COMPILER_CXX_EXCEPTIONS": false,
+    "COMPILER_CXX_RTTI": false,
+    "COMPILER_DISABLE_DEFAULT_ERRORS": true,
+    "COMPILER_DISABLE_GCC12_WARNINGS": false,
+    "COMPILER_DISABLE_GCC13_WARNINGS": false,
+    "COMPILER_DISABLE_GCC14_WARNINGS": false,
+    "COMPILER_DUMP_RTL_FILES": false,
+    "COMPILER_FLOAT_LIB_FROM_GCCLIB": true,
+    "COMPILER_HIDE_PATHS_MACROS": true,
+    "COMPILER_NO_MERGE_CONSTANTS": false,
+    "COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE": false,
+    "COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE": true,
+    "COMPILER_OPTIMIZATION_ASSERTIONS_SILENT": false,
+    "COMPILER_OPTIMIZATION_ASSERTION_LEVEL": 2,
+    "COMPILER_OPTIMIZATION_CHECKS_SILENT": false,
+    "COMPILER_OPTIMIZATION_DEBUG": true,
+    "COMPILER_OPTIMIZATION_NONE": false,
+    "COMPILER_OPTIMIZATION_PERF": false,
+    "COMPILER_OPTIMIZATION_SIZE": false,
+    "COMPILER_ORPHAN_SECTIONS_PLACE": false,
+    "COMPILER_ORPHAN_SECTIONS_WARNING": true,
+    "COMPILER_RT_LIB_GCCLIB": true,
+    "COMPILER_RT_LIB_NAME": "gcc",
+    "COMPILER_SAVE_RESTORE_LIBCALLS": false,
+    "COMPILER_STACK_CHECK_MODE_ALL": false,
+    "COMPILER_STACK_CHECK_MODE_NONE": true,
+    "COMPILER_STACK_CHECK_MODE_NORM": false,
+    "COMPILER_STACK_CHECK_MODE_STRONG": false,
+    "COMPILER_STATIC_ANALYZER": false,
+    "COMPILER_WARN_WRITE_STRINGS": false,
+    "EFUSE_CUSTOM_TABLE": false,
+    "EFUSE_MAX_BLK_LEN": 256,
+    "EFUSE_VIRTUAL": false,
+    "ESP32C3_REV_MAX_FULL": 199,
+    "ESP32C3_REV_MIN_0": false,
+    "ESP32C3_REV_MIN_1": false,
+    "ESP32C3_REV_MIN_101": false,
+    "ESP32C3_REV_MIN_2": false,
+    "ESP32C3_REV_MIN_3": true,
+    "ESP32C3_REV_MIN_4": false,
+    "ESP32C3_REV_MIN_FULL": 3,
+    "ESP32C3_UNIVERSAL_MAC_ADDRESSES": 4,
+    "ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR": true,
+    "ESP32C3_UNIVERSAL_MAC_ADDRESSES_TWO": false,
+    "ESPTOOLPY_AFTER": "hard_reset",
+    "ESPTOOLPY_AFTER_NORESET": false,
+    "ESPTOOLPY_AFTER_RESET": true,
+    "ESPTOOLPY_BEFORE": "default_reset",
+    "ESPTOOLPY_BEFORE_NORESET": false,
+    "ESPTOOLPY_BEFORE_RESET": true,
+    "ESPTOOLPY_FLASHFREQ": "80m",
+    "ESPTOOLPY_FLASHFREQ_20M": false,
+    "ESPTOOLPY_FLASHFREQ_26M": false,
+    "ESPTOOLPY_FLASHFREQ_40M": false,
+    "ESPTOOLPY_FLASHFREQ_80M": true,
+    "ESPTOOLPY_FLASHMODE": "dio",
+    "ESPTOOLPY_FLASHMODE_DIO": true,
+    "ESPTOOLPY_FLASHMODE_DOUT": false,
+    "ESPTOOLPY_FLASHMODE_QIO": false,
+    "ESPTOOLPY_FLASHMODE_QOUT": false,
+    "ESPTOOLPY_FLASHSIZE": "2MB",
+    "ESPTOOLPY_FLASHSIZE_128MB": false,
+    "ESPTOOLPY_FLASHSIZE_16MB": false,
+    "ESPTOOLPY_FLASHSIZE_1MB": false,
+    "ESPTOOLPY_FLASHSIZE_2MB": true,
+    "ESPTOOLPY_FLASHSIZE_32MB": false,
+    "ESPTOOLPY_FLASHSIZE_4MB": false,
+    "ESPTOOLPY_FLASHSIZE_64MB": false,
+    "ESPTOOLPY_FLASHSIZE_8MB": false,
+    "ESPTOOLPY_FLASH_SAMPLE_MODE_STR": true,
+    "ESPTOOLPY_HEADER_FLASHSIZE_UPDATE": false,
+    "ESPTOOLPY_MONITOR_BAUD": 115200,
+    "ESPTOOLPY_NO_STUB": false,
+    "ESP_BROWNOUT_DET": true,
+    "ESP_BROWNOUT_DET_LVL": 7,
+    "ESP_BROWNOUT_DET_LVL_SEL_2": false,
+    "ESP_BROWNOUT_DET_LVL_SEL_3": false,
+    "ESP_BROWNOUT_DET_LVL_SEL_4": false,
+    "ESP_BROWNOUT_DET_LVL_SEL_5": false,
+    "ESP_BROWNOUT_DET_LVL_SEL_6": false,
+    "ESP_BROWNOUT_DET_LVL_SEL_7": true,
+    "ESP_CONSOLE_NONE": false,
+    "ESP_CONSOLE_ROM_SERIAL_PORT_NUM": 0,
+    "ESP_CONSOLE_SECONDARY_NONE": false,
+    "ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG": true,
+    "ESP_CONSOLE_UART": true,
+    "ESP_CONSOLE_UART_BAUDRATE": 115200,
+    "ESP_CONSOLE_UART_CUSTOM": false,
+    "ESP_CONSOLE_UART_DEFAULT": true,
+    "ESP_CONSOLE_UART_NUM": 0,
+    "ESP_CONSOLE_USB_SERIAL_JTAG": false,
+    "ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED": true,
+    "ESP_DEBUG_OCDAWARE": true,
+    "ESP_DEBUG_STUBS_ENABLE": false,
+    "ESP_DEFAULT_CPU_FREQ_MHZ": 160,
+    "ESP_DEFAULT_CPU_FREQ_MHZ_160": true,
+    "ESP_DEFAULT_CPU_FREQ_MHZ_80": false,
+    "ESP_EFUSE_BLOCK_REV_MAX_FULL": 199,
+    "ESP_EFUSE_BLOCK_REV_MIN_FULL": 0,
+    "ESP_ERR_TO_NAME_LOOKUP": true,
+    "ESP_INT_WDT": true,
+    "ESP_INT_WDT_TIMEOUT_MS": 300,
+    "ESP_IPC_TASK_STACK_SIZE": 1024,
+    "ESP_MAC_ADDR_UNIVERSE_BT": true,
+    "ESP_MAC_ADDR_UNIVERSE_ETH": true,
+    "ESP_MAC_ADDR_UNIVERSE_WIFI_AP": true,
+    "ESP_MAC_ADDR_UNIVERSE_WIFI_STA": true,
+    "ESP_MAC_UNIVERSAL_MAC_ADDRESSES": 4,
+    "ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR": true,
+    "ESP_MAC_USE_CUSTOM_MAC_AS_BASE_MAC": false,
+    "ESP_MAIN_TASK_AFFINITY": 0,
+    "ESP_MAIN_TASK_AFFINITY_CPU0": true,
+    "ESP_MAIN_TASK_AFFINITY_NO_AFFINITY": false,
+    "ESP_MAIN_TASK_STACK_SIZE": 3584,
+    "ESP_MINIMAL_SHARED_STACK_SIZE": 2048,
+    "ESP_PANIC_HANDLER_IRAM": false,
+    "ESP_REV_MAX_FULL": 199,
+    "ESP_REV_MIN_FULL": 3,
+    "ESP_ROM_GET_CLK_FREQ": true,
+    "ESP_ROM_HAS_CRC_BE": true,
+    "ESP_ROM_HAS_CRC_LE": true,
+    "ESP_ROM_HAS_ENCRYPTED_WRITES_USING_LEGACY_DRV": true,
+    "ESP_ROM_HAS_ERASE_0_REGION_BUG": true,
+    "ESP_ROM_HAS_ETS_PRINTF_BUG": true,
+    "ESP_ROM_HAS_JPEG_DECODE": true,
+    "ESP_ROM_HAS_LAYOUT_TABLE": true,
+    "ESP_ROM_HAS_MZ_CRC32": true,
+    "ESP_ROM_HAS_NEWLIB": true,
+    "ESP_ROM_HAS_NEWLIB_32BIT_TIME": true,
+    "ESP_ROM_HAS_NEWLIB_NANO_FORMAT": true,
+    "ESP_ROM_HAS_RETARGETABLE_LOCKING": true,
+    "ESP_ROM_HAS_SPI_FLASH": true,
+    "ESP_ROM_HAS_SW_FLOAT": true,
+    "ESP_ROM_HAS_VERSION": true,
+    "ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE": true,
+    "ESP_ROM_NEEDS_SWSETUP_WORKAROUND": true,
+    "ESP_ROM_RAM_APP_NEEDS_MMU_INIT": true,
+    "ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB": true,
+    "ESP_ROM_UART_CLK_IS_XTAL": true,
+    "ESP_ROM_USB_OTG_NUM": -1,
+    "ESP_ROM_USB_SERIAL_DEVICE_NUM": 3,
+    "ESP_SLEEP_CACHE_SAFE_ASSERTION": false,
+    "ESP_SLEEP_DEBUG": false,
+    "ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND": true,
+    "ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS": true,
+    "ESP_SLEEP_GPIO_RESET_WORKAROUND": true,
+    "ESP_SLEEP_MSPI_NEED_ALL_IO_PU": false,
+    "ESP_SLEEP_POWER_DOWN_FLASH": false,
+    "ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY": 0,
+    "ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP": true,
+    "ESP_SYSTEM_BROWNOUT_INTR": true,
+    "ESP_SYSTEM_CHECK_INT_LEVEL_4": true,
+    "ESP_SYSTEM_EVENT_QUEUE_SIZE": 32,
+    "ESP_SYSTEM_EVENT_TASK_STACK_SIZE": 2304,
+    "ESP_SYSTEM_HW_PC_RECORD": true,
+    "ESP_SYSTEM_HW_STACK_GUARD": true,
+    "ESP_SYSTEM_MEMPROT_FEATURE": true,
+    "ESP_SYSTEM_MEMPROT_FEATURE_LOCK": true,
+    "ESP_SYSTEM_PANIC_PRINT_HALT": false,
+    "ESP_SYSTEM_PANIC_PRINT_REBOOT": true,
+    "ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS": 0,
+    "ESP_SYSTEM_PANIC_SILENT_REBOOT": false,
+    "ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK": true,
+    "ESP_SYSTEM_SINGLE_CORE_MODE": true,
+    "ESP_SYSTEM_USE_EH_FRAME": false,
+    "ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0": true,
+    "ESP_TASK_WDT_EN": true,
+    "ESP_TASK_WDT_INIT": true,
+    "ESP_TASK_WDT_PANIC": false,
+    "ESP_TASK_WDT_TIMEOUT_S": 5,
+    "FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER": true,
+    "FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE": false,
+    "FREERTOS_CHECK_STACKOVERFLOW_CANARY": true,
+    "FREERTOS_CHECK_STACKOVERFLOW_NONE": false,
+    "FREERTOS_CHECK_STACKOVERFLOW_PTRVAL": false,
+    "FREERTOS_CORETIMER_SYSTIMER_LVL1": true,
+    "FREERTOS_CORETIMER_SYSTIMER_LVL3": false,
+    "FREERTOS_DEBUG_OCDAWARE": true,
+    "FREERTOS_ENABLE_BACKWARD_COMPATIBILITY": false,
+    "FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP": false,
+    "FREERTOS_ENABLE_TASK_SNAPSHOT": true,
+    "FREERTOS_GENERATE_RUN_TIME_STATS": false,
+    "FREERTOS_HZ": 100,
+    "FREERTOS_IDLE_TASK_STACKSIZE": 1536,
+    "FREERTOS_INTERRUPT_BACKTRACE": true,
+    "FREERTOS_ISR_STACKSIZE": 1536,
+    "FREERTOS_MAX_TASK_NAME_LEN": 16,
+    "FREERTOS_NO_AFFINITY": 2147483647,
+    "FREERTOS_NUMBER_OF_CORES": 1,
+    "FREERTOS_OPTIMIZED_SCHEDULER": true,
+    "FREERTOS_PLACE_FUNCTIONS_INTO_FLASH": false,
+    "FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH": true,
+    "FREERTOS_PORT": true,
+    "FREERTOS_QUEUE_REGISTRY_SIZE": 0,
+    "FREERTOS_SMP": false,
+    "FREERTOS_SUPPORT_STATIC_ALLOCATION": true,
+    "FREERTOS_SYSTICK_USES_SYSTIMER": true,
+    "FREERTOS_TASK_FUNCTION_WRAPPER": true,
+    "FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES": 1,
+    "FREERTOS_TASK_PRE_DELETION_HOOK": false,
+    "FREERTOS_THREAD_LOCAL_STORAGE_POINTERS": 1,
+    "FREERTOS_TICK_SUPPORT_SYSTIMER": true,
+    "FREERTOS_TIMER_QUEUE_LENGTH": 10,
+    "FREERTOS_TIMER_SERVICE_TASK_CORE_AFFINITY": 2147483647,
+    "FREERTOS_TIMER_SERVICE_TASK_NAME": "Tmr Svc",
+    "FREERTOS_TIMER_TASK_AFFINITY_CPU0": false,
+    "FREERTOS_TIMER_TASK_NO_AFFINITY": true,
+    "FREERTOS_TIMER_TASK_PRIORITY": 1,
+    "FREERTOS_TIMER_TASK_STACK_DEPTH": 2048,
+    "FREERTOS_TLSP_DELETION_CALLBACKS": true,
+    "FREERTOS_UNICORE": true,
+    "FREERTOS_USE_APPLICATION_TASK_TAG": false,
+    "FREERTOS_USE_IDLE_HOOK": false,
+    "FREERTOS_USE_LIST_DATA_INTEGRITY_CHECK_BYTES": false,
+    "FREERTOS_USE_TICK_HOOK": false,
+    "FREERTOS_USE_TIMERS": true,
+    "FREERTOS_USE_TRACE_FACILITY": false,
+    "FREERTOS_WATCHPOINT_END_OF_STACK": false,
+    "GDMA_CTRL_FUNC_IN_IRAM": true,
+    "GDMA_ENABLE_DEBUG_LOG": false,
+    "GDMA_ISR_IRAM_SAFE": false,
+    "HAL_ASSERTION_DISABLE": false,
+    "HAL_ASSERTION_ENABLE": false,
+    "HAL_ASSERTION_EQUALS_SYSTEM": true,
+    "HAL_ASSERTION_SILENT": false,
+    "HAL_DEFAULT_ASSERTION_LEVEL": 2,
+    "IDF_CMAKE": true,
+    "IDF_EXPERIMENTAL_FEATURES": false,
+    "IDF_FIRMWARE_CHIP_ID": 5,
+    "IDF_INIT_VERSION": "5.4.1",
+    "IDF_TARGET": "esp32c3",
+    "IDF_TARGET_ARCH": "riscv",
+    "IDF_TARGET_ARCH_RISCV": true,
+    "IDF_TARGET_ESP32C3": true,
+    "IDF_TOOLCHAIN": "gcc",
+    "IDF_TOOLCHAIN_GCC": true,
+    "LOG_COLORS": false,
+    "LOG_DEFAULT_LEVEL": 3,
+    "LOG_DEFAULT_LEVEL_DEBUG": false,
+    "LOG_DEFAULT_LEVEL_ERROR": false,
+    "LOG_DEFAULT_LEVEL_INFO": true,
+    "LOG_DEFAULT_LEVEL_NONE": false,
+    "LOG_DEFAULT_LEVEL_VERBOSE": false,
+    "LOG_DEFAULT_LEVEL_WARN": false,
+    "LOG_DYNAMIC_LEVEL_CONTROL": true,
+    "LOG_MASTER_LEVEL": false,
+    "LOG_MAXIMUM_EQUALS_DEFAULT": true,
+    "LOG_MAXIMUM_LEVEL": 3,
+    "LOG_MAXIMUM_LEVEL_DEBUG": false,
+    "LOG_MAXIMUM_LEVEL_VERBOSE": false,
+    "LOG_TAG_LEVEL_CACHE_ARRAY": false,
+    "LOG_TAG_LEVEL_CACHE_BINARY_MIN_HEAP": true,
+    "LOG_TAG_LEVEL_IMPL_CACHE_AND_LINKED_LIST": true,
+    "LOG_TAG_LEVEL_IMPL_CACHE_SIZE": 31,
+    "LOG_TAG_LEVEL_IMPL_LINKED_LIST": false,
+    "LOG_TAG_LEVEL_IMPL_NONE": false,
+    "LOG_TIMESTAMP_SOURCE_RTOS": true,
+    "LOG_TIMESTAMP_SOURCE_SYSTEM": false,
+    "MMU_PAGE_MODE": "64KB",
+    "MMU_PAGE_SIZE": 65536,
+    "MMU_PAGE_SIZE_64KB": true,
+    "NEWLIB_NANO_FORMAT": false,
+    "NEWLIB_STDIN_LINE_ENDING_CR": true,
+    "NEWLIB_STDIN_LINE_ENDING_CRLF": false,
+    "NEWLIB_STDIN_LINE_ENDING_LF": false,
+    "NEWLIB_STDOUT_LINE_ENDING_CR": false,
+    "NEWLIB_STDOUT_LINE_ENDING_CRLF": true,
+    "NEWLIB_STDOUT_LINE_ENDING_LF": false,
+    "NEWLIB_TIME_SYSCALL_USE_HRT": false,
+    "NEWLIB_TIME_SYSCALL_USE_NONE": false,
+    "NEWLIB_TIME_SYSCALL_USE_RTC": false,
+    "NEWLIB_TIME_SYSCALL_USE_RTC_HRT": true,
+    "PARTITION_TABLE_CUSTOM": false,
+    "PARTITION_TABLE_CUSTOM_FILENAME": "partitions.csv",
+    "PARTITION_TABLE_FILENAME": "partitions_singleapp.csv",
+    "PARTITION_TABLE_MD5": true,
+    "PARTITION_TABLE_OFFSET": 32768,
+    "PARTITION_TABLE_SINGLE_APP": true,
+    "PARTITION_TABLE_SINGLE_APP_LARGE": false,
+    "PARTITION_TABLE_TWO_OTA": false,
+    "PARTITION_TABLE_TWO_OTA_LARGE": false,
+    "PERIPH_CTRL_FUNC_IN_IRAM": true,
+    "RTC_CLK_CAL_CYCLES": 1024,
+    "RTC_CLK_SRC_EXT_CRYS": false,
+    "RTC_CLK_SRC_EXT_OSC": false,
+    "RTC_CLK_SRC_INT_8MD256": false,
+    "RTC_CLK_SRC_INT_RC": true,
+    "SECURE_BOOT": false,
+    "SECURE_BOOT_V2_PREFERRED": true,
+    "SECURE_BOOT_V2_RSA_SUPPORTED": true,
+    "SECURE_FLASH_ENC_ENABLED": false,
+    "SECURE_ROM_DL_MODE_ENABLED": true,
+    "SECURE_SIGNED_APPS_NO_SECURE_BOOT": false,
+    "SOC_ADC_ARBITER_SUPPORTED": true,
+    "SOC_ADC_ATTEN_NUM": 4,
+    "SOC_ADC_CALIBRATION_V1_SUPPORTED": true,
+    "SOC_ADC_DIGI_CONTROLLER_NUM": 1,
+    "SOC_ADC_DIGI_DATA_BYTES_PER_CONV": 4,
+    "SOC_ADC_DIGI_IIR_FILTER_NUM": 2,
+    "SOC_ADC_DIGI_MAX_BITWIDTH": 12,
+    "SOC_ADC_DIGI_MIN_BITWIDTH": 12,
+    "SOC_ADC_DIGI_MONITOR_NUM": 2,
+    "SOC_ADC_DIGI_RESULT_BYTES": 4,
+    "SOC_ADC_DIG_CTRL_SUPPORTED": true,
+    "SOC_ADC_DIG_IIR_FILTER_SUPPORTED": true,
+    "SOC_ADC_DMA_SUPPORTED": true,
+    "SOC_ADC_MAX_CHANNEL_NUM": 5,
+    "SOC_ADC_MONITOR_SUPPORTED": true,
+    "SOC_ADC_PATT_LEN_MAX": 8,
+    "SOC_ADC_PERIPH_NUM": 2,
+    "SOC_ADC_RTC_MAX_BITWIDTH": 12,
+    "SOC_ADC_RTC_MIN_BITWIDTH": 12,
+    "SOC_ADC_SAMPLE_FREQ_THRES_HIGH": 83333,
+    "SOC_ADC_SAMPLE_FREQ_THRES_LOW": 611,
+    "SOC_ADC_SELF_HW_CALI_SUPPORTED": true,
+    "SOC_ADC_SHARED_POWER": true,
+    "SOC_ADC_SUPPORTED": true,
+    "SOC_AES_GDMA": true,
+    "SOC_AES_SUPPORTED": true,
+    "SOC_AES_SUPPORT_AES_128": true,
+    "SOC_AES_SUPPORT_AES_256": true,
+    "SOC_AES_SUPPORT_DMA": true,
+    "SOC_AHB_GDMA_SUPPORTED": true,
+    "SOC_AHB_GDMA_VERSION": 1,
+    "SOC_APB_BACKUP_DMA": true,
+    "SOC_ASSIST_DEBUG_SUPPORTED": true,
+    "SOC_ASYNC_MEMCPY_SUPPORTED": true,
+    "SOC_BLE_50_SUPPORTED": true,
+    "SOC_BLE_DEVICE_PRIVACY_SUPPORTED": true,
+    "SOC_BLE_MESH_SUPPORTED": true,
+    "SOC_BLE_SUPPORTED": true,
+    "SOC_BLUFI_SUPPORTED": true,
+    "SOC_BOD_SUPPORTED": true,
+    "SOC_BROWNOUT_RESET_SUPPORTED": true,
+    "SOC_BT_SUPPORTED": true,
+    "SOC_CACHE_MEMORY_IBANK_SIZE": 16384,
+    "SOC_CLK_RC_FAST_D256_SUPPORTED": true,
+    "SOC_CLK_RC_FAST_SUPPORT_CALIBRATION": true,
+    "SOC_CLK_TREE_SUPPORTED": true,
+    "SOC_CLK_XTAL32K_SUPPORTED": true,
+    "SOC_COEX_HW_PTI": true,
+    "SOC_CPU_BREAKPOINTS_NUM": 8,
+    "SOC_CPU_CORES_NUM": 1,
+    "SOC_CPU_HAS_CSR_PC": true,
+    "SOC_CPU_HAS_FLEXIBLE_INTC": true,
+    "SOC_CPU_INTR_NUM": 32,
+    "SOC_CPU_WATCHPOINTS_NUM": 8,
+    "SOC_CPU_WATCHPOINT_MAX_REGION_SIZE": 2147483648,
+    "SOC_DEDICATED_GPIO_SUPPORTED": true,
+    "SOC_DEDIC_GPIO_IN_CHANNELS_NUM": 8,
+    "SOC_DEDIC_GPIO_OUT_CHANNELS_NUM": 8,
+    "SOC_DEDIC_PERIPH_ALWAYS_ENABLE": true,
+    "SOC_DEEP_SLEEP_SUPPORTED": true,
+    "SOC_DIG_SIGN_SUPPORTED": true,
+    "SOC_DS_KEY_CHECK_MAX_WAIT_US": 1100,
+    "SOC_DS_KEY_PARAM_MD_IV_LENGTH": 16,
+    "SOC_DS_SIGNATURE_MAX_BIT_LEN": 3072,
+    "SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK": true,
+    "SOC_EFUSE_DIS_DIRECT_BOOT": true,
+    "SOC_EFUSE_DIS_DOWNLOAD_ICACHE": true,
+    "SOC_EFUSE_DIS_ICACHE": true,
+    "SOC_EFUSE_DIS_PAD_JTAG": true,
+    "SOC_EFUSE_DIS_USB_JTAG": true,
+    "SOC_EFUSE_HAS_EFUSE_RST_BUG": true,
+    "SOC_EFUSE_KEY_PURPOSE_FIELD": true,
+    "SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS": true,
+    "SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS": 3,
+    "SOC_EFUSE_SOFT_DIS_JTAG": true,
+    "SOC_EFUSE_SUPPORTED": true,
+    "SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX": 32,
+    "SOC_FLASH_ENCRYPTION_XTS_AES": true,
+    "SOC_FLASH_ENCRYPTION_XTS_AES_128": true,
+    "SOC_FLASH_ENC_SUPPORTED": true,
+    "SOC_GDMA_NUM_GROUPS_MAX": 1,
+    "SOC_GDMA_PAIRS_PER_GROUP_MAX": 3,
+    "SOC_GDMA_SUPPORTED": true,
+    "SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX": true,
+    "SOC_GPIO_CLOCKOUT_CHANNEL_NUM": 3,
+    "SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT": 6,
+    "SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK": 0,
+    "SOC_GPIO_FILTER_CLK_SUPPORT_APB": true,
+    "SOC_GPIO_IN_RANGE_MAX": 21,
+    "SOC_GPIO_OUT_RANGE_MAX": 21,
+    "SOC_GPIO_PIN_COUNT": 22,
+    "SOC_GPIO_PORT": 1,
+    "SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP": true,
+    "SOC_GPIO_SUPPORT_FORCE_HOLD": true,
+    "SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP": true,
+    "SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER": true,
+    "SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK": 4194240,
+    "SOC_GPSPI_SUPPORTED": true,
+    "SOC_GPTIMER_SUPPORTED": true,
+    "SOC_HMAC_SUPPORTED": true,
+    "SOC_HP_I2C_NUM": 1,
+    "SOC_I2C_CMD_REG_NUM": 8,
+    "SOC_I2C_FIFO_LEN": 32,
+    "SOC_I2C_NUM": 1,
+    "SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE": true,
+    "SOC_I2C_SLAVE_SUPPORT_BROADCAST": true,
+    "SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS": true,
+    "SOC_I2C_SUPPORTED": true,
+    "SOC_I2C_SUPPORT_10BIT_ADDR": true,
+    "SOC_I2C_SUPPORT_HW_CLR_BUS": true,
+    "SOC_I2C_SUPPORT_RTC": true,
+    "SOC_I2C_SUPPORT_SLAVE": true,
+    "SOC_I2C_SUPPORT_XTAL": true,
+    "SOC_I2S_HW_VERSION_2": true,
+    "SOC_I2S_NUM": 1,
+    "SOC_I2S_PDM_MAX_TX_LINES": 2,
+    "SOC_I2S_SUPPORTED": true,
+    "SOC_I2S_SUPPORTS_PCM": true,
+    "SOC_I2S_SUPPORTS_PDM": true,
+    "SOC_I2S_SUPPORTS_PDM_TX": true,
+    "SOC_I2S_SUPPORTS_PLL_F160M": true,
+    "SOC_I2S_SUPPORTS_TDM": true,
+    "SOC_I2S_SUPPORTS_XTAL": true,
+    "SOC_LEDC_CHANNEL_NUM": 6,
+    "SOC_LEDC_SUPPORTED": true,
+    "SOC_LEDC_SUPPORT_APB_CLOCK": true,
+    "SOC_LEDC_SUPPORT_FADE_STOP": true,
+    "SOC_LEDC_SUPPORT_XTAL_CLOCK": true,
+    "SOC_LEDC_TIMER_BIT_WIDTH": 14,
+    "SOC_LEDC_TIMER_NUM": 4,
+    "SOC_LIGHT_SLEEP_SUPPORTED": true,
+    "SOC_LP_PERIPH_SHARE_INTERRUPT": true,
+    "SOC_LP_TIMER_BIT_WIDTH_HI": 16,
+    "SOC_LP_TIMER_BIT_WIDTH_LO": 32,
+    "SOC_MAC_BB_PD_MEM_SIZE": 192,
+    "SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE": 16,
+    "SOC_MEMPROT_MEM_ALIGN_SIZE": 512,
+    "SOC_MEMPROT_SUPPORTED": true,
+    "SOC_MEMSPI_IS_INDEPENDENT": true,
+    "SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED": true,
+    "SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED": true,
+    "SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED": true,
+    "SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED": true,
+    "SOC_MMU_LINEAR_ADDRESS_REGION_NUM": 1,
+    "SOC_MMU_PERIPH_NUM": 1,
+    "SOC_MPI_MEM_BLOCKS_NUM": 4,
+    "SOC_MPI_OPERATIONS_NUM": 3,
+    "SOC_MPI_SUPPORTED": true,
+    "SOC_MPU_MIN_REGION_SIZE": 536870912,
+    "SOC_MPU_REGIONS_MAX_NUM": 8,
+    "SOC_MWDT_SUPPORT_XTAL": true,
+    "SOC_PHY_COMBO_MODULE": true,
+    "SOC_PHY_DIG_REGS_MEM_SIZE": 21,
+    "SOC_PHY_SUPPORTED": true,
+    "SOC_PM_CPU_RETENTION_BY_RTCCNTL": true,
+    "SOC_PM_MODEM_PD_BY_SW": true,
+    "SOC_PM_MODEM_RETENTION_BY_BACKUPDMA": true,
+    "SOC_PM_SUPPORTED": true,
+    "SOC_PM_SUPPORT_BT_PD": true,
+    "SOC_PM_SUPPORT_BT_WAKEUP": true,
+    "SOC_PM_SUPPORT_CPU_PD": true,
+    "SOC_PM_SUPPORT_MAC_BB_PD": true,
+    "SOC_PM_SUPPORT_RC_FAST_PD": true,
+    "SOC_PM_SUPPORT_VDDSDIO_PD": true,
+    "SOC_PM_SUPPORT_WIFI_PD": true,
+    "SOC_PM_SUPPORT_WIFI_WAKEUP": true,
+    "SOC_RMT_CHANNELS_PER_GROUP": 4,
+    "SOC_RMT_GROUPS": 1,
+    "SOC_RMT_MEM_WORDS_PER_CHANNEL": 48,
+    "SOC_RMT_RX_CANDIDATES_PER_GROUP": 2,
+    "SOC_RMT_SUPPORTED": true,
+    "SOC_RMT_SUPPORT_APB": true,
+    "SOC_RMT_SUPPORT_RC_FAST": true,
+    "SOC_RMT_SUPPORT_RX_DEMODULATION": true,
+    "SOC_RMT_SUPPORT_RX_PINGPONG": true,
+    "SOC_RMT_SUPPORT_TX_ASYNC_STOP": true,
+    "SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY": true,
+    "SOC_RMT_SUPPORT_TX_LOOP_COUNT": true,
+    "SOC_RMT_SUPPORT_TX_SYNCHRO": true,
+    "SOC_RMT_SUPPORT_XTAL": true,
+    "SOC_RMT_TX_CANDIDATES_PER_GROUP": 2,
+    "SOC_RNG_SUPPORTED": true,
+    "SOC_RSA_MAX_BIT_LEN": 3072,
+    "SOC_RTCIO_PIN_COUNT": 0,
+    "SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH": 128,
+    "SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM": 108,
+    "SOC_RTC_FAST_MEM_SUPPORTED": true,
+    "SOC_RTC_MEM_SUPPORTED": true,
+    "SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256": true,
+    "SOC_SDM_CHANNELS_PER_GROUP": 4,
+    "SOC_SDM_CLK_SUPPORT_APB": true,
+    "SOC_SDM_GROUPS": 1,
+    "SOC_SDM_SUPPORTED": true,
+    "SOC_SECURE_BOOT_SUPPORTED": true,
+    "SOC_SECURE_BOOT_V2_RSA": true,
+    "SOC_SHARED_IDCACHE_SUPPORTED": true,
+    "SOC_SHA_DMA_MAX_BUFFER_SIZE": 3968,
+    "SOC_SHA_GDMA": true,
+    "SOC_SHA_SUPPORTED": true,
+    "SOC_SHA_SUPPORT_DMA": true,
+    "SOC_SHA_SUPPORT_RESUME": true,
+    "SOC_SHA_SUPPORT_SHA1": true,
+    "SOC_SHA_SUPPORT_SHA224": true,
+    "SOC_SHA_SUPPORT_SHA256": true,
+    "SOC_SLEEP_SYSTIMER_STALL_WORKAROUND": true,
+    "SOC_SLEEP_TGWDT_STOP_WORKAROUND": true,
+    "SOC_SPI_FLASH_SUPPORTED": true,
+    "SOC_SPI_MAXIMUM_BUFFER_SIZE": 64,
+    "SOC_SPI_MAX_CS_NUM": 6,
+    "SOC_SPI_MAX_PRE_DIVIDER": 16,
+    "SOC_SPI_MEM_SUPPORT_AUTO_RESUME": true,
+    "SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND": true,
+    "SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE": true,
+    "SOC_SPI_MEM_SUPPORT_CHECK_SUS": true,
+    "SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE": true,
+    "SOC_SPI_MEM_SUPPORT_IDLE_INTR": true,
+    "SOC_SPI_MEM_SUPPORT_SW_SUSPEND": true,
+    "SOC_SPI_MEM_SUPPORT_WRAP": true,
+    "SOC_SPI_PERIPH_NUM": 2,
+    "SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT": true,
+    "SOC_SPI_SCT_BUFFER_NUM_MAX": true,
+    "SOC_SPI_SCT_CONF_BITLEN_MAX": 262138,
+    "SOC_SPI_SCT_REG_NUM": 14,
+    "SOC_SPI_SCT_SUPPORTED": true,
+    "SOC_SPI_SLAVE_SUPPORT_SEG_TRANS": true,
+    "SOC_SPI_SUPPORT_CD_SIG": true,
+    "SOC_SPI_SUPPORT_CLK_APB": true,
+    "SOC_SPI_SUPPORT_CLK_XTAL": true,
+    "SOC_SPI_SUPPORT_CONTINUOUS_TRANS": true,
+    "SOC_SPI_SUPPORT_DDRCLK": true,
+    "SOC_SPI_SUPPORT_SLAVE_HD_VER2": true,
+    "SOC_SUPPORTS_SECURE_DL_MODE": true,
+    "SOC_SUPPORT_COEXISTENCE": true,
+    "SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY": true,
+    "SOC_SYSTIMER_ALARM_MISS_COMPENSATE": true,
+    "SOC_SYSTIMER_ALARM_NUM": 3,
+    "SOC_SYSTIMER_BIT_WIDTH_HI": 20,
+    "SOC_SYSTIMER_BIT_WIDTH_LO": 32,
+    "SOC_SYSTIMER_COUNTER_NUM": 2,
+    "SOC_SYSTIMER_FIXED_DIVIDER": true,
+    "SOC_SYSTIMER_INT_LEVEL": true,
+    "SOC_SYSTIMER_SUPPORTED": true,
+    "SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC": true,
+    "SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL": true,
+    "SOC_TEMP_SENSOR_SUPPORTED": true,
+    "SOC_TIMER_GROUPS": 2,
+    "SOC_TIMER_GROUP_COUNTER_BIT_WIDTH": 54,
+    "SOC_TIMER_GROUP_SUPPORT_APB": true,
+    "SOC_TIMER_GROUP_SUPPORT_XTAL": true,
+    "SOC_TIMER_GROUP_TIMERS_PER_GROUP": 1,
+    "SOC_TIMER_GROUP_TOTAL_TIMERS": 2,
+    "SOC_TWAI_BRP_MAX": 16384,
+    "SOC_TWAI_BRP_MIN": 2,
+    "SOC_TWAI_CLK_SUPPORT_APB": true,
+    "SOC_TWAI_CONTROLLER_NUM": 1,
+    "SOC_TWAI_SUPPORTED": true,
+    "SOC_TWAI_SUPPORTS_RX_STATUS": true,
+    "SOC_UART_BITRATE_MAX": 5000000,
+    "SOC_UART_FIFO_LEN": 128,
+    "SOC_UART_HP_NUM": 2,
+    "SOC_UART_NUM": 2,
+    "SOC_UART_SUPPORTED": true,
+    "SOC_UART_SUPPORT_APB_CLK": true,
+    "SOC_UART_SUPPORT_FSM_TX_WAIT_SEND": true,
+    "SOC_UART_SUPPORT_RTC_CLK": true,
+    "SOC_UART_SUPPORT_WAKEUP_INT": true,
+    "SOC_UART_SUPPORT_XTAL_CLK": true,
+    "SOC_USB_SERIAL_JTAG_SUPPORTED": true,
+    "SOC_WDT_SUPPORTED": true,
+    "SOC_WIFI_CSI_SUPPORT": true,
+    "SOC_WIFI_FTM_SUPPORT": true,
+    "SOC_WIFI_GCMP_SUPPORT": true,
+    "SOC_WIFI_HW_TSF": true,
+    "SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH": 12,
+    "SOC_WIFI_MESH_SUPPORT": true,
+    "SOC_WIFI_PHY_NEEDS_USB_WORKAROUND": true,
+    "SOC_WIFI_SUPPORTED": true,
+    "SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW": true,
+    "SOC_WIFI_WAPI_SUPPORT": true,
+    "SOC_XTAL_SUPPORT_40M": true,
+    "SOC_XT_WDT_SUPPORTED": true,
+    "SPI_FLASH_AUTO_SUSPEND": false,
+    "SPI_FLASH_BROWNOUT_RESET": true,
+    "SPI_FLASH_BROWNOUT_RESET_XMC": true,
+    "SPI_FLASH_BYPASS_BLOCK_ERASE": false,
+    "SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED": false,
+    "SPI_FLASH_DANGEROUS_WRITE_ABORTS": true,
+    "SPI_FLASH_DANGEROUS_WRITE_ALLOWED": false,
+    "SPI_FLASH_DANGEROUS_WRITE_FAILS": false,
+    "SPI_FLASH_ENABLE_COUNTERS": false,
+    "SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE": true,
+    "SPI_FLASH_ERASE_YIELD_DURATION_MS": 20,
+    "SPI_FLASH_ERASE_YIELD_TICKS": 1,
+    "SPI_FLASH_FORCE_ENABLE_XMC_C_SUSPEND": false,
+    "SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST": false,
+    "SPI_FLASH_ROM_DRIVER_PATCH": true,
+    "SPI_FLASH_ROM_IMPL": false,
+    "SPI_FLASH_SIZE_OVERRIDE": false,
+    "SPI_FLASH_SUPPORT_BOYA_CHIP": true,
+    "SPI_FLASH_SUPPORT_GD_CHIP": true,
+    "SPI_FLASH_SUPPORT_ISSI_CHIP": true,
+    "SPI_FLASH_SUPPORT_MXIC_CHIP": true,
+    "SPI_FLASH_SUPPORT_TH_CHIP": true,
+    "SPI_FLASH_SUPPORT_WINBOND_CHIP": true,
+    "SPI_FLASH_SUSPEND_TSUS_VAL_US": 50,
+    "SPI_FLASH_VENDOR_BOYA_SUPPORTED": true,
+    "SPI_FLASH_VENDOR_GD_SUPPORTED": true,
+    "SPI_FLASH_VENDOR_ISSI_SUPPORTED": true,
+    "SPI_FLASH_VENDOR_MXIC_SUPPORTED": true,
+    "SPI_FLASH_VENDOR_TH_SUPPORTED": true,
+    "SPI_FLASH_VENDOR_WINBOND_SUPPORTED": true,
+    "SPI_FLASH_VENDOR_XMC_SUPPORTED": true,
+    "SPI_FLASH_VERIFY_WRITE": false,
+    "SPI_FLASH_WRITE_CHUNK_SIZE": 8192,
+    "SPI_FLASH_YIELD_DURING_ERASE": true,
+    "XTAL_FREQ": 40,
+    "XTAL_FREQ_40": true
+}
\ No newline at end of file
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new file mode 100644
index 000000000..64cdd2799
--- /dev/null
+++ b/ESP32-IDF_ESPNOW-Receiver/build/bootloader/kconfigs.in
@@ -0,0 +1,11 @@
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+source "/home/abobkov/esp/v5.4.1/esp-idf/components/esp_common/Kconfig"
+source "/home/abobkov/esp/v5.4.1/esp-idf/components/esp_hw_support/Kconfig"
+source "/home/abobkov/esp/v5.4.1/esp-idf/components/esp_security/Kconfig"
+source "/home/abobkov/esp/v5.4.1/esp-idf/components/esp_system/Kconfig"
+source "/home/abobkov/esp/v5.4.1/esp-idf/components/freertos/Kconfig"
+source "/home/abobkov/esp/v5.4.1/esp-idf/components/hal/Kconfig"
+source "/home/abobkov/esp/v5.4.1/esp-idf/components/log/Kconfig"
+source "/home/abobkov/esp/v5.4.1/esp-idf/components/newlib/Kconfig"
+source "/home/abobkov/esp/v5.4.1/esp-idf/components/soc/Kconfig"
+source "/home/abobkov/esp/v5.4.1/esp-idf/components/spi_flash/Kconfig"
\ No newline at end of file
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new file mode 100644
index 000000000..1fc5efd99
--- /dev/null
+++ b/ESP32-IDF_ESPNOW-Receiver/build/bootloader/kconfigs_projbuild.in
@@ -0,0 +1,5 @@
+source "/home/abobkov/esp/v5.4.1/esp-idf/components/bootloader/Kconfig.projbuild"
+source "/home/abobkov/esp/v5.4.1/esp-idf/components/esp_app_format/Kconfig.projbuild"
+source "/home/abobkov/esp/v5.4.1/esp-idf/components/esp_rom/Kconfig.projbuild"
+source "/home/abobkov/esp/v5.4.1/esp-idf/components/esptool_py/Kconfig.projbuild"
+source "/home/abobkov/esp/v5.4.1/esp-idf/components/partition_table/Kconfig.projbuild"
\ No newline at end of file
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+.byte 0x75, 0x1f, 0x3b, 0xff, 0x6c, 0xa8, 0xc5, 0xc6, 0x56, 0xf8, 0xb4, 0xed, 0x8a, 0x44, 0xa3, 0xab
+.byte 0x6c, 0x4c, 0xfc, 0x1d, 0xd0, 0xdc, 0xef, 0x68, 0xbd, 0xcf, 0xe4, 0xaa, 0xce, 0xf0, 0x55, 0xf7
+.byte 0xa2, 0x34, 0xd4, 0x83, 0x6b, 0x37, 0x7c, 0x1c, 0xc2, 0xfe, 0xb5, 0x03, 0xec, 0x57, 0xce, 0xbc
+.byte 0xb4, 0xb5, 0xc5, 0xed, 0x00, 0x0f, 0x53, 0x37, 0x2a, 0x4d, 0xf4, 0x4f, 0x0c, 0x83, 0xfb, 0x86
+.byte 0xcf, 0xcb, 0xfe, 0x8c, 0x4e, 0xbd, 0x87, 0xf9, 0xa7, 0x8b, 0x21, 0x57, 0x9c, 0x7a, 0xdf, 0x03
+.byte 0x67, 0x89, 0x2c, 0x9d, 0x97, 0x61, 0xa7, 0x10, 0xb8, 0x55, 0x90, 0x7f, 0x0e, 0x2d, 0x27, 0x38
+.byte 0x74, 0xdf, 0xe7, 0xfd, 0xda, 0x4e, 0x12, 0xe3, 0x4d, 0x15, 0x22, 0x02, 0xc8, 0xe0, 0xe0, 0xfc
+.byte 0x0f, 0xad, 0x8a, 0xd7, 0xc9, 0x54, 0x50, 0xcc, 0x3b, 0x0f, 0xca, 0x16, 0x80, 0x84, 0xd0, 0x51
+.byte 0x56, 0xc3, 0x8e, 0x56, 0x7f, 0x89, 0x22, 0x33, 0x2f, 0xe6, 0x85, 0x0a, 0xbd, 0xa5, 0xa8, 0x1b
+.byte 0x36, 0xde, 0xd3, 0xdc, 0x2c, 0x6d, 0x3b, 0xc7, 0x13, 0xbd, 0x59, 0x23, 0x2c, 0xe6, 0xe5, 0xa4
+.byte 0xf7, 0xd8, 0x0b, 0xed, 0xea, 0x90, 0x40, 0x44, 0xa8, 0x95, 0xbb, 0x93, 0xd5, 0xd0, 0x80, 0x34
+.byte 0xb6, 0x46, 0x78, 0x0e, 0x1f, 0x00, 0x93, 0x46, 0xe1, 0xee, 0xe9, 0xf9, 0xec, 0x4f, 0x17, 0x02
+.byte 0x03, 0x01, 0x00, 0x01
+
+.global _binary_x509_crt_bundle_end
+_binary_x509_crt_bundle_end: /* for objcopy compatibility */
+
+
+.global x509_crt_bundle_length
+x509_crt_bundle_length:
+.long 69876