mirror of
https://github.com/espressif/esp-idf.git
synced 2025-08-11 13:00:19 +00:00
Merge branch 'feat/adding_esp32c61_gdma' into 'master'
feat: c61 add gdma support Closes IDF-9310, IDF-9311, and IDF-9315 See merge request espressif/esp-idf!32145
This commit is contained in:
morris
@@ -11,6 +11,14 @@ config SOC_UART_SUPPORTED
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bool
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default y
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config SOC_GDMA_SUPPORTED
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bool
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default y
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config SOC_AHB_GDMA_SUPPORTED
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bool
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default y
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config SOC_GPTIMER_SUPPORTED
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bool
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default y
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@@ -19,6 +27,10 @@ config SOC_USB_SERIAL_JTAG_SUPPORTED
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bool
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default y
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config SOC_ASYNC_MEMCPY_SUPPORTED
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bool
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default y
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config SOC_SUPPORTS_SECURE_DL_MODE
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bool
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default y
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@@ -167,6 +179,22 @@ config SOC_CPU_PMP_REGION_GRANULARITY
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int
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default 128
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config SOC_DMA_CAN_ACCESS_FLASH
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bool
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default y
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config SOC_AHB_GDMA_VERSION
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int
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default 2
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config SOC_GDMA_NUM_GROUPS_MAX
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int
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default 1
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config SOC_GDMA_PAIRS_PER_GROUP_MAX
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int
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default 2
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config SOC_ETM_GROUPS
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int
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default 1
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2371
components/soc/esp32c61/include/soc/ahb_dma_reg.h
Normal file
2371
components/soc/esp32c61/include/soc/ahb_dma_reg.h
Normal file
File diff suppressed because it is too large
Load Diff
@@ -47,7 +47,7 @@ typedef union {
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} gdma_in_int_raw_chn_reg_t;
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} ahb_dma_in_int_raw_chn_reg_t;
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/** Type of in_int_st_chn register
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* Masked interrupt status of RX channel 0
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@@ -85,7 +85,7 @@ typedef union {
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} gdma_in_int_st_chn_reg_t;
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} ahb_dma_in_int_st_chn_reg_t;
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/** Type of in_int_ena_chn register
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* Interrupt enable bits of RX channel 0
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@@ -123,7 +123,7 @@ typedef union {
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} gdma_in_int_ena_chn_reg_t;
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} ahb_dma_in_int_ena_chn_reg_t;
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/** Type of in_int_clr_chn register
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* Interrupt clear bits of RX channel 0
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@@ -161,7 +161,7 @@ typedef union {
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} gdma_in_int_clr_chn_reg_t;
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} ahb_dma_in_int_clr_chn_reg_t;
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/** Type of out_int_raw_chn register
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* Raw interrupt status of TX channel 0
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@@ -195,7 +195,7 @@ typedef union {
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uint32_t reserved_6:26;
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};
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uint32_t val;
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} gdma_out_int_raw_chn_reg_t;
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} ahb_dma_out_int_raw_chn_reg_t;
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/** Type of out_int_st_chn register
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* Masked interrupt status of TX channel 0
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@@ -229,7 +229,7 @@ typedef union {
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uint32_t reserved_6:26;
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};
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uint32_t val;
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} gdma_out_int_st_chn_reg_t;
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} ahb_dma_out_int_st_chn_reg_t;
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/** Type of out_int_ena_chn register
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* Interrupt enable bits of TX channel 0
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@@ -263,7 +263,7 @@ typedef union {
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uint32_t reserved_6:26;
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};
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uint32_t val;
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} gdma_out_int_ena_chn_reg_t;
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} ahb_dma_out_int_ena_chn_reg_t;
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/** Type of out_int_clr_chn register
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* Interrupt clear bits of TX channel 0
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@@ -297,7 +297,7 @@ typedef union {
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uint32_t reserved_6:26;
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};
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uint32_t val;
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} gdma_out_int_clr_chn_reg_t;
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} ahb_dma_out_int_clr_chn_reg_t;
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/** Group: Debug Registers */
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@@ -318,7 +318,7 @@ typedef union {
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uint32_t reserved_6:26;
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};
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uint32_t val;
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} gdma_ahb_test_reg_t;
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} ahb_dma_ahb_test_reg_t;
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/** Group: Configuration Registers */
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@@ -345,7 +345,7 @@ typedef union {
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uint32_t reserved_4:28;
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};
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uint32_t val;
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} gdma_misc_conf_reg_t;
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} ahb_dma_misc_conf_reg_t;
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/** Type of in_conf0_chn register
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* Configuration register 0 of RX channel 0
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@@ -384,7 +384,7 @@ typedef union {
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uint32_t reserved_8:24;
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};
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uint32_t val;
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} gdma_in_conf0_chn_reg_t;
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} ahb_dma_in_conf0_chn_reg_t;
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/** Type of in_conf1_chn register
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* Configuration register 1 of RX channel 0
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@@ -400,7 +400,7 @@ typedef union {
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uint32_t reserved_13:19;
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};
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uint32_t val;
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} gdma_in_conf1_chn_reg_t;
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} ahb_dma_in_conf1_chn_reg_t;
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/** Type of in_pop_chn register
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* Pop control register of RX channel 0
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@@ -419,7 +419,7 @@ typedef union {
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uint32_t reserved_13:19;
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};
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uint32_t val;
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} gdma_in_pop_chn_reg_t;
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} ahb_dma_in_pop_chn_reg_t;
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/** Type of in_link_chn register
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* Linked list descriptor configuration and control register of RX channel 0
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@@ -453,7 +453,7 @@ typedef union {
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uint32_t reserved_5:27;
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};
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uint32_t val;
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} gdma_in_link_chn_reg_t;
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} ahb_dma_in_link_chn_reg_t;
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/** Type of out_conf0_ch0 register
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* Configuration register 0 of TX channel 0
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@@ -501,7 +501,7 @@ typedef union {
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uint32_t reserved_10:22;
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};
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uint32_t val;
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} gdma_out_conf0_ch0_reg_t;
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} ahb_dma_out_conf0_ch0_reg_t;
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/** Type of out_conf1_chn register
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* Configuration register 1 of TX channel 0
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@@ -517,7 +517,7 @@ typedef union {
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uint32_t reserved_13:19;
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};
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uint32_t val;
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} gdma_out_conf1_chn_reg_t;
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} ahb_dma_out_conf1_chn_reg_t;
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/** Type of out_push_chn register
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* Push control register of TX channel 0
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@@ -536,7 +536,7 @@ typedef union {
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uint32_t reserved_10:22;
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};
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uint32_t val;
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} gdma_out_push_chn_reg_t;
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} ahb_dma_out_push_chn_reg_t;
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/** Type of out_link_chn register
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* Linked list descriptor configuration and control register of TX channel 0
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@@ -565,7 +565,7 @@ typedef union {
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uint32_t reserved_4:28;
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};
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uint32_t val;
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} gdma_out_link_chn_reg_t;
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} ahb_dma_out_link_chn_reg_t;
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/** Type of out_conf0_chn register
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* Configuration register 0 of TX channel 1
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@@ -613,7 +613,7 @@ typedef union {
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uint32_t reserved_10:22;
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};
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uint32_t val;
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} gdma_out_conf0_chn_reg_t;
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} ahb_dma_out_conf0_chn_reg_t;
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/** Type of tx_ch_arb_weigh_chn register
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* TX channel 0 arbitration weight configuration register
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@@ -627,7 +627,7 @@ typedef union {
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uint32_t reserved_4:28;
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};
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uint32_t val;
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} gdma_tx_ch_arb_weigh_chn_reg_t;
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} ahb_dma_tx_ch_arb_weigh_chn_reg_t;
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/** Type of tx_arb_weigh_opt_dir_chn register
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* TX channel 0 weight arbitration optimization enable register
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@@ -641,7 +641,7 @@ typedef union {
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} gdma_tx_arb_weigh_opt_dir_chn_reg_t;
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} ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t;
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/** Type of rx_ch_arb_weigh_chn register
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* RX channel 0 arbitration weight configuration register
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@@ -655,7 +655,7 @@ typedef union {
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uint32_t reserved_4:28;
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};
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uint32_t val;
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} gdma_rx_ch_arb_weigh_chn_reg_t;
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} ahb_dma_rx_ch_arb_weigh_chn_reg_t;
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/** Type of rx_arb_weigh_opt_dir_chn register
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* RX channel 0 weight arbitration optimization enable register
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@@ -669,7 +669,7 @@ typedef union {
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} gdma_rx_arb_weigh_opt_dir_chn_reg_t;
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} ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t;
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/** Type of in_link_addr_chn register
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* Link list descriptor address configuration of RX channel 0
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@@ -682,7 +682,7 @@ typedef union {
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uint32_t inlink_addr_chn:32;
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};
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uint32_t val;
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} gdma_in_link_addr_chn_reg_t;
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} ahb_dma_in_link_addr_chn_reg_t;
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/** Type of out_link_addr_chn register
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* Link list descriptor address configuration of TX channel 0
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@@ -695,7 +695,7 @@ typedef union {
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uint32_t outlink_addr_chn:32;
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};
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uint32_t val;
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} gdma_out_link_addr_chn_reg_t;
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} ahb_dma_out_link_addr_chn_reg_t;
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/** Type of intr_mem_start_addr register
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* Accessible address space start address configuration register
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@@ -708,7 +708,7 @@ typedef union {
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uint32_t access_intr_mem_start_addr:32;
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};
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uint32_t val;
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} gdma_intr_mem_start_addr_reg_t;
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} ahb_dma_intr_mem_start_addr_reg_t;
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/** Type of intr_mem_end_addr register
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* Accessible address space end address configuration register
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@@ -721,7 +721,7 @@ typedef union {
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uint32_t access_intr_mem_end_addr:32;
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};
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uint32_t val;
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} gdma_intr_mem_end_addr_reg_t;
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} ahb_dma_intr_mem_end_addr_reg_t;
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/** Type of arb_timeout_tx register
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* TX arbitration timeout configuration register
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@@ -735,7 +735,7 @@ typedef union {
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uint32_t reserved_16:16;
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};
|
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uint32_t val;
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} gdma_arb_timeout_tx_reg_t;
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} ahb_dma_arb_timeout_tx_reg_t;
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|
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/** Type of arb_timeout_rx register
|
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* RX arbitration timeout configuration register
|
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@@ -749,7 +749,7 @@ typedef union {
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uint32_t reserved_16:16;
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};
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uint32_t val;
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} gdma_arb_timeout_rx_reg_t;
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} ahb_dma_arb_timeout_rx_reg_t;
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|
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/** Type of weight_en_tx register
|
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* TX weight arbitration enable register
|
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@@ -763,7 +763,7 @@ typedef union {
|
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uint32_t reserved_1:31;
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};
|
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uint32_t val;
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} gdma_weight_en_tx_reg_t;
|
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} ahb_dma_weight_en_tx_reg_t;
|
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|
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/** Type of weight_en_rx register
|
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* RX weight arbitration enable register
|
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@@ -777,7 +777,7 @@ typedef union {
|
||||
uint32_t reserved_1:31;
|
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};
|
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uint32_t val;
|
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} gdma_weight_en_rx_reg_t;
|
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} ahb_dma_weight_en_rx_reg_t;
|
||||
|
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|
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/** Group: Version Registers */
|
||||
@@ -792,7 +792,7 @@ typedef union {
|
||||
uint32_t date:32;
|
||||
};
|
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uint32_t val;
|
||||
} gdma_date_reg_t;
|
||||
} ahb_dma_date_reg_t;
|
||||
|
||||
|
||||
/** Group: Status Registers */
|
||||
@@ -838,7 +838,7 @@ typedef union {
|
||||
uint32_t reserved_28:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} gdma_infifo_status_chn_reg_t;
|
||||
} ahb_dma_infifo_status_chn_reg_t;
|
||||
|
||||
/** Type of in_state_chn register
|
||||
* Receive status of RX channel 0
|
||||
@@ -861,7 +861,7 @@ typedef union {
|
||||
uint32_t reserved_23:9;
|
||||
};
|
||||
uint32_t val;
|
||||
} gdma_in_state_chn_reg_t;
|
||||
} ahb_dma_in_state_chn_reg_t;
|
||||
|
||||
/** Type of in_suc_eof_des_addr_chn register
|
||||
* Receive descriptor address when EOF occurs on RX channel 0
|
||||
@@ -875,7 +875,7 @@ typedef union {
|
||||
uint32_t in_suc_eof_des_addr_chn:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} gdma_in_suc_eof_des_addr_chn_reg_t;
|
||||
} ahb_dma_in_suc_eof_des_addr_chn_reg_t;
|
||||
|
||||
/** Type of in_err_eof_des_addr_chn register
|
||||
* Receive descriptor address when errors occur of RX channel 0
|
||||
@@ -889,7 +889,7 @@ typedef union {
|
||||
uint32_t in_err_eof_des_addr_chn:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} gdma_in_err_eof_des_addr_chn_reg_t;
|
||||
} ahb_dma_in_err_eof_des_addr_chn_reg_t;
|
||||
|
||||
/** Type of in_dscr_chn register
|
||||
* Current receive descriptor address of RX channel 0
|
||||
@@ -903,7 +903,7 @@ typedef union {
|
||||
uint32_t inlink_dscr_chn:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} gdma_in_dscr_chn_reg_t;
|
||||
} ahb_dma_in_dscr_chn_reg_t;
|
||||
|
||||
/** Type of in_dscr_bf0_chn register
|
||||
* The last receive descriptor address of RX channel 0
|
||||
@@ -917,7 +917,7 @@ typedef union {
|
||||
uint32_t inlink_dscr_bf0_chn:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} gdma_in_dscr_bf0_chn_reg_t;
|
||||
} ahb_dma_in_dscr_bf0_chn_reg_t;
|
||||
|
||||
/** Type of in_dscr_bf1_chn register
|
||||
* The second-to-last receive descriptor address of RX channel 0
|
||||
@@ -931,7 +931,7 @@ typedef union {
|
||||
uint32_t inlink_dscr_bf1_chn:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} gdma_in_dscr_bf1_chn_reg_t;
|
||||
} ahb_dma_in_dscr_bf1_chn_reg_t;
|
||||
|
||||
/** Type of in_done_des_addr_chn register
|
||||
* RX_done Inlink descriptor address of RX channel 0
|
||||
@@ -944,7 +944,7 @@ typedef union {
|
||||
uint32_t in_done_des_addr_chn:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} gdma_in_done_des_addr_chn_reg_t;
|
||||
} ahb_dma_in_done_des_addr_chn_reg_t;
|
||||
|
||||
/** Type of outfifo_status_chn register
|
||||
* Transmit FIFO status of TX channel 0
|
||||
@@ -984,7 +984,7 @@ typedef union {
|
||||
uint32_t reserved_27:5;
|
||||
};
|
||||
uint32_t val;
|
||||
} gdma_outfifo_status_chn_reg_t;
|
||||
} ahb_dma_outfifo_status_chn_reg_t;
|
||||
|
||||
/** Type of out_state_chn register
|
||||
* Transmit status of TX channel 0
|
||||
@@ -1007,7 +1007,7 @@ typedef union {
|
||||
uint32_t reserved_23:9;
|
||||
};
|
||||
uint32_t val;
|
||||
} gdma_out_state_chn_reg_t;
|
||||
} ahb_dma_out_state_chn_reg_t;
|
||||
|
||||
/** Type of out_eof_des_addr_chn register
|
||||
* Transmit descriptor address when EOF occurs on TX channel 0
|
||||
@@ -1021,7 +1021,7 @@ typedef union {
|
||||
uint32_t out_eof_des_addr_chn:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} gdma_out_eof_des_addr_chn_reg_t;
|
||||
} ahb_dma_out_eof_des_addr_chn_reg_t;
|
||||
|
||||
/** Type of out_eof_bfr_des_addr_chn register
|
||||
* The last transmit descriptor address when EOF occurs on TX channel 0
|
||||
@@ -1035,7 +1035,7 @@ typedef union {
|
||||
uint32_t out_eof_bfr_des_addr_chn:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} gdma_out_eof_bfr_des_addr_chn_reg_t;
|
||||
} ahb_dma_out_eof_bfr_des_addr_chn_reg_t;
|
||||
|
||||
/** Type of out_dscr_chn register
|
||||
* Current transmit descriptor address of TX channel 0
|
||||
@@ -1049,7 +1049,7 @@ typedef union {
|
||||
uint32_t outlink_dscr_chn:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} gdma_out_dscr_chn_reg_t;
|
||||
} ahb_dma_out_dscr_chn_reg_t;
|
||||
|
||||
/** Type of out_dscr_bf0_chn register
|
||||
* The last transmit descriptor address of TX channel 0
|
||||
@@ -1063,7 +1063,7 @@ typedef union {
|
||||
uint32_t outlink_dscr_bf0_chn:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} gdma_out_dscr_bf0_chn_reg_t;
|
||||
} ahb_dma_out_dscr_bf0_chn_reg_t;
|
||||
|
||||
/** Type of out_dscr_bf1_chn register
|
||||
* The second-to-last transmit descriptor address of TX channel 0
|
||||
@@ -1077,7 +1077,7 @@ typedef union {
|
||||
uint32_t outlink_dscr_bf1_chn:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} gdma_out_dscr_bf1_chn_reg_t;
|
||||
} ahb_dma_out_dscr_bf1_chn_reg_t;
|
||||
|
||||
/** Type of out_done_des_addr_chn register
|
||||
* TX done outlink descriptor address of TX channel 0
|
||||
@@ -1090,7 +1090,7 @@ typedef union {
|
||||
uint32_t out_done_des_addr_chn:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} gdma_out_done_des_addr_chn_reg_t;
|
||||
} ahb_dma_out_done_des_addr_chn_reg_t;
|
||||
|
||||
|
||||
/** Group: Priority Registers */
|
||||
@@ -1107,7 +1107,7 @@ typedef union {
|
||||
uint32_t reserved_4:28;
|
||||
};
|
||||
uint32_t val;
|
||||
} gdma_in_pri_chn_reg_t;
|
||||
} ahb_dma_in_pri_chn_reg_t;
|
||||
|
||||
/** Type of out_pri_chn register
|
||||
* Priority register of TX channel 0
|
||||
@@ -1122,7 +1122,7 @@ typedef union {
|
||||
uint32_t reserved_4:28;
|
||||
};
|
||||
uint32_t val;
|
||||
} gdma_out_pri_chn_reg_t;
|
||||
} ahb_dma_out_pri_chn_reg_t;
|
||||
|
||||
|
||||
/** Group: Peripheral Select Registers */
|
||||
@@ -1140,7 +1140,7 @@ typedef union {
|
||||
uint32_t reserved_6:26;
|
||||
};
|
||||
uint32_t val;
|
||||
} gdma_in_peri_sel_chn_reg_t;
|
||||
} ahb_dma_in_peri_sel_chn_reg_t;
|
||||
|
||||
/** Type of out_peri_sel_chn register
|
||||
* Peripheral selection register of TX channel 0
|
||||
@@ -1156,124 +1156,109 @@ typedef union {
|
||||
uint32_t reserved_6:26;
|
||||
};
|
||||
uint32_t val;
|
||||
} gdma_out_peri_sel_chn_reg_t;
|
||||
} ahb_dma_out_peri_sel_chn_reg_t;
|
||||
|
||||
typedef struct {
|
||||
volatile ahb_dma_in_int_raw_chn_reg_t raw;
|
||||
volatile ahb_dma_in_int_st_chn_reg_t st;
|
||||
volatile ahb_dma_in_int_ena_chn_reg_t ena;
|
||||
volatile ahb_dma_in_int_clr_chn_reg_t clr;
|
||||
} ahb_dma_in_int_chn_reg_t;
|
||||
|
||||
typedef struct {
|
||||
volatile ahb_dma_out_int_raw_chn_reg_t raw;
|
||||
volatile ahb_dma_out_int_st_chn_reg_t st;
|
||||
volatile ahb_dma_out_int_ena_chn_reg_t ena;
|
||||
volatile ahb_dma_out_int_clr_chn_reg_t clr;
|
||||
} ahb_dma_out_int_chn_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch0;
|
||||
volatile gdma_in_int_st_chn_reg_t in_int_st_ch0;
|
||||
volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch0;
|
||||
volatile gdma_in_int_clr_chn_reg_t in_int_clr_ch0;
|
||||
volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch1;
|
||||
volatile gdma_in_int_st_chn_reg_t in_int_st_ch1;
|
||||
volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch1;
|
||||
volatile gdma_in_int_clr_chn_reg_t in_int_clr_ch1;
|
||||
uint32_t reserved_020[4];
|
||||
volatile gdma_out_int_raw_chn_reg_t out_int_raw_ch0;
|
||||
volatile gdma_out_int_st_chn_reg_t out_int_st_ch0;
|
||||
volatile gdma_out_int_ena_chn_reg_t out_int_ena_ch0;
|
||||
volatile gdma_out_int_clr_chn_reg_t out_int_clr_ch0;
|
||||
volatile gdma_out_int_raw_chn_reg_t out_int_raw_ch1;
|
||||
volatile gdma_out_int_st_chn_reg_t out_int_st_ch1;
|
||||
volatile gdma_out_int_ena_chn_reg_t out_int_ena_ch1;
|
||||
volatile gdma_out_int_clr_chn_reg_t out_int_clr_ch1;
|
||||
uint32_t reserved_050[4];
|
||||
volatile gdma_ahb_test_reg_t ahb_test;
|
||||
volatile gdma_misc_conf_reg_t misc_conf;
|
||||
volatile gdma_date_reg_t date;
|
||||
uint32_t reserved_06c;
|
||||
volatile gdma_in_conf0_chn_reg_t in_conf0_ch0;
|
||||
volatile gdma_in_conf1_chn_reg_t in_conf1_ch0;
|
||||
volatile gdma_infifo_status_chn_reg_t infifo_status_ch0;
|
||||
volatile gdma_in_pop_chn_reg_t in_pop_ch0;
|
||||
volatile gdma_in_link_chn_reg_t in_link_ch0;
|
||||
volatile gdma_in_state_chn_reg_t in_state_ch0;
|
||||
volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch0;
|
||||
volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch0;
|
||||
volatile gdma_in_dscr_chn_reg_t in_dscr_ch0;
|
||||
volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch0;
|
||||
volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch0;
|
||||
volatile gdma_in_pri_chn_reg_t in_pri_ch0;
|
||||
volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch0;
|
||||
uint32_t reserved_0a4[3];
|
||||
volatile gdma_in_done_des_addr_chn_reg_t in_done_des_addr_ch0;
|
||||
uint32_t reserved_0b4[7];
|
||||
volatile gdma_out_conf0_ch0_reg_t out_conf0_ch0;
|
||||
volatile gdma_out_conf1_chn_reg_t out_conf1_ch0;
|
||||
volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch0;
|
||||
volatile gdma_out_push_chn_reg_t out_push_ch0;
|
||||
volatile gdma_out_link_chn_reg_t out_link_ch0;
|
||||
volatile gdma_out_state_chn_reg_t out_state_ch0;
|
||||
volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch0;
|
||||
volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch0;
|
||||
volatile gdma_out_dscr_chn_reg_t out_dscr_ch0;
|
||||
volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch0;
|
||||
volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch0;
|
||||
volatile gdma_out_pri_chn_reg_t out_pri_ch0;
|
||||
volatile gdma_out_peri_sel_chn_reg_t out_peri_sel_ch0;
|
||||
uint32_t reserved_104[3];
|
||||
volatile gdma_out_done_des_addr_chn_reg_t out_done_des_addr_ch0;
|
||||
uint32_t reserved_114[7];
|
||||
volatile gdma_in_conf0_chn_reg_t in_conf0_ch1;
|
||||
volatile gdma_in_conf1_chn_reg_t in_conf1_ch1;
|
||||
volatile gdma_infifo_status_chn_reg_t infifo_status_ch1;
|
||||
volatile gdma_in_pop_chn_reg_t in_pop_ch1;
|
||||
volatile gdma_in_link_chn_reg_t in_link_ch1;
|
||||
volatile gdma_in_state_chn_reg_t in_state_ch1;
|
||||
volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch1;
|
||||
volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch1;
|
||||
volatile gdma_in_dscr_chn_reg_t in_dscr_ch1;
|
||||
volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch1;
|
||||
volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch1;
|
||||
volatile gdma_in_pri_chn_reg_t in_pri_ch1;
|
||||
volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch1;
|
||||
uint32_t reserved_164[3];
|
||||
volatile gdma_in_done_des_addr_chn_reg_t in_done_des_addr_ch1;
|
||||
uint32_t reserved_174[7];
|
||||
volatile gdma_out_conf0_chn_reg_t out_conf0_ch1;
|
||||
volatile gdma_out_conf1_chn_reg_t out_conf1_ch1;
|
||||
volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch1;
|
||||
volatile gdma_out_push_chn_reg_t out_push_ch1;
|
||||
volatile gdma_out_link_chn_reg_t out_link_ch1;
|
||||
volatile gdma_out_state_chn_reg_t out_state_ch1;
|
||||
volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch1;
|
||||
volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch1;
|
||||
volatile gdma_out_dscr_chn_reg_t out_dscr_ch1;
|
||||
volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch1;
|
||||
volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch1;
|
||||
volatile gdma_out_pri_chn_reg_t out_pri_ch1;
|
||||
volatile gdma_out_peri_sel_chn_reg_t out_peri_sel_ch1;
|
||||
uint32_t reserved_1c4[3];
|
||||
volatile gdma_out_done_des_addr_chn_reg_t out_done_des_addr_ch1;
|
||||
uint32_t reserved_1d4[66];
|
||||
volatile gdma_tx_ch_arb_weigh_chn_reg_t tx_ch_arb_weigh_ch0;
|
||||
volatile gdma_tx_arb_weigh_opt_dir_chn_reg_t tx_arb_weigh_opt_dir_ch0;
|
||||
uint32_t reserved_2e4[8];
|
||||
volatile gdma_tx_ch_arb_weigh_chn_reg_t tx_ch_arb_weigh_ch1;
|
||||
volatile gdma_tx_arb_weigh_opt_dir_chn_reg_t tx_arb_weigh_opt_dir_ch1;
|
||||
uint32_t reserved_30c[18];
|
||||
volatile gdma_rx_ch_arb_weigh_chn_reg_t rx_ch_arb_weigh_ch0;
|
||||
volatile gdma_rx_arb_weigh_opt_dir_chn_reg_t rx_arb_weigh_opt_dir_ch0;
|
||||
uint32_t reserved_35c[8];
|
||||
volatile gdma_rx_ch_arb_weigh_chn_reg_t rx_ch_arb_weigh_ch1;
|
||||
volatile gdma_rx_arb_weigh_opt_dir_chn_reg_t rx_arb_weigh_opt_dir_ch1;
|
||||
uint32_t reserved_384[10];
|
||||
volatile gdma_in_link_addr_chn_reg_t in_link_addr_chn[2];
|
||||
uint32_t reserved_3b4;
|
||||
volatile gdma_out_link_addr_chn_reg_t out_link_addr_chn[2];
|
||||
uint32_t reserved_3c0;
|
||||
volatile gdma_intr_mem_start_addr_reg_t intr_mem_start_addr;
|
||||
volatile gdma_intr_mem_end_addr_reg_t intr_mem_end_addr;
|
||||
volatile gdma_arb_timeout_tx_reg_t arb_timeout_tx;
|
||||
volatile gdma_arb_timeout_rx_reg_t arb_timeout_rx;
|
||||
volatile gdma_weight_en_tx_reg_t weight_en_tx;
|
||||
volatile gdma_weight_en_rx_reg_t weight_en_rx;
|
||||
} gdma_dev_t;
|
||||
volatile ahb_dma_in_conf0_chn_reg_t in_conf0;
|
||||
volatile ahb_dma_in_conf1_chn_reg_t in_conf1;
|
||||
volatile ahb_dma_infifo_status_chn_reg_t infifo_status;
|
||||
volatile ahb_dma_in_pop_chn_reg_t in_pop;
|
||||
volatile ahb_dma_in_link_chn_reg_t in_link;
|
||||
volatile ahb_dma_in_state_chn_reg_t in_state;
|
||||
volatile ahb_dma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr;
|
||||
volatile ahb_dma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr;
|
||||
volatile ahb_dma_in_dscr_chn_reg_t in_dscr;
|
||||
volatile ahb_dma_in_dscr_bf0_chn_reg_t in_dscr_bf0;
|
||||
volatile ahb_dma_in_dscr_bf1_chn_reg_t in_dscr_bf1;
|
||||
volatile ahb_dma_in_pri_chn_reg_t in_pri;
|
||||
volatile ahb_dma_in_peri_sel_chn_reg_t in_peri_sel;
|
||||
} ahb_dma_in_chn_reg_t;
|
||||
|
||||
extern gdma_dev_t GDMA;
|
||||
typedef struct {
|
||||
volatile ahb_dma_out_conf0_chn_reg_t out_conf0;
|
||||
volatile ahb_dma_out_conf1_chn_reg_t out_conf1;
|
||||
volatile ahb_dma_outfifo_status_chn_reg_t outfifo_status;
|
||||
volatile ahb_dma_out_push_chn_reg_t out_push;
|
||||
volatile ahb_dma_out_link_chn_reg_t out_link;
|
||||
volatile ahb_dma_out_state_chn_reg_t out_state;
|
||||
volatile ahb_dma_out_eof_des_addr_chn_reg_t out_eof_des_addr;
|
||||
volatile ahb_dma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr;
|
||||
volatile ahb_dma_out_dscr_chn_reg_t out_dscr;
|
||||
volatile ahb_dma_out_dscr_bf0_chn_reg_t out_dscr_bf0;
|
||||
volatile ahb_dma_out_dscr_bf1_chn_reg_t out_dscr_bf1;
|
||||
volatile ahb_dma_out_pri_chn_reg_t out_pri;
|
||||
volatile ahb_dma_out_peri_sel_chn_reg_t out_peri_sel;
|
||||
} ahb_dma_out_chn_reg_t;
|
||||
|
||||
typedef struct {
|
||||
volatile ahb_dma_in_chn_reg_t in;
|
||||
uint32_t reserved_0a4[3];
|
||||
volatile ahb_dma_in_done_des_addr_chn_reg_t in_done_des_addr_ch0;
|
||||
uint32_t reserved_0b4[7];
|
||||
volatile ahb_dma_out_chn_reg_t out;
|
||||
uint32_t reserved_104[3];
|
||||
volatile ahb_dma_out_done_des_addr_chn_reg_t out_done_des_addr_ch0;
|
||||
uint32_t reserved_114[7];
|
||||
} ahb_dma_chn_reg_t;
|
||||
|
||||
typedef struct {
|
||||
uint32_t reserved[8];
|
||||
ahb_dma_tx_ch_arb_weigh_chn_reg_t ch_arb_weigh;
|
||||
ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t arb_weigh_opt;
|
||||
} ahb_dma_out_crc_arb_chn_reg_t;
|
||||
|
||||
typedef struct {
|
||||
uint32_t reserved[8];
|
||||
ahb_dma_rx_ch_arb_weigh_chn_reg_t ch_arb_weigh;
|
||||
ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t arb_weigh_opt;
|
||||
} ahb_dma_in_crc_arb_chn_reg_t;
|
||||
|
||||
typedef struct {
|
||||
volatile ahb_dma_in_int_chn_reg_t in_intr[2];
|
||||
uint32_t reserved_020[4];
|
||||
volatile ahb_dma_out_int_chn_reg_t out_intr[2];
|
||||
uint32_t reserved_050[4];
|
||||
volatile ahb_dma_ahb_test_reg_t ahb_test;
|
||||
volatile ahb_dma_misc_conf_reg_t misc_conf;
|
||||
volatile ahb_dma_date_reg_t date;
|
||||
uint32_t reserved_06c;
|
||||
volatile ahb_dma_chn_reg_t channel[2];
|
||||
uint32_t reserved_1d4[51];
|
||||
volatile ahb_dma_out_crc_arb_chn_reg_t out_crc_arb[2];
|
||||
uint32_t reserved_30c[10];
|
||||
volatile ahb_dma_in_crc_arb_chn_reg_t in_crc_arb[2];
|
||||
uint32_t reserved_384[10];
|
||||
volatile ahb_dma_in_link_addr_chn_reg_t in_link_addr[2];
|
||||
uint32_t reserved_3b4;
|
||||
volatile ahb_dma_out_link_addr_chn_reg_t out_link_addr[2];
|
||||
uint32_t reserved_3c0;
|
||||
volatile ahb_dma_intr_mem_start_addr_reg_t intr_mem_start_addr;
|
||||
volatile ahb_dma_intr_mem_end_addr_reg_t intr_mem_end_addr;
|
||||
volatile ahb_dma_arb_timeout_tx_reg_t arb_timeout_tx;
|
||||
volatile ahb_dma_arb_timeout_rx_reg_t arb_timeout_rx;
|
||||
volatile ahb_dma_weight_en_tx_reg_t weight_en_tx;
|
||||
volatile ahb_dma_weight_en_rx_reg_t weight_en_rx;
|
||||
} ahb_dma_dev_t;
|
||||
|
||||
extern ahb_dma_dev_t AHB_DMA;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(gdma_dev_t) == 0x3dc, "Invalid size of gdma_dev_t structure");
|
||||
_Static_assert(sizeof(ahb_dma_dev_t) == 0x3dc, "Invalid size of ahb_dma_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
@@ -5,3 +5,22 @@
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
|
||||
#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1)
|
||||
#define SOC_GDMA_TRIG_PERIPH_SPI2 (0)
|
||||
#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2)
|
||||
#define SOC_GDMA_TRIG_PERIPH_I2S0 (3)
|
||||
#define SOC_GDMA_TRIG_PERIPH_SHA0 (7)
|
||||
#define SOC_GDMA_TRIG_PERIPH_ADC0 (8)
|
||||
|
||||
// On which system bus is the DMA instance of the peripheral connection mounted
|
||||
#define SOC_GDMA_BUS_ANY (-1)
|
||||
#define SOC_GDMA_BUS_AHB (0)
|
||||
|
||||
#define SOC_GDMA_TRIG_PERIPH_M2M0_BUS SOC_GDMA_BUS_ANY
|
||||
#define SOC_GDMA_TRIG_PERIPH_SPI2_BUS SOC_GDMA_BUS_AHB
|
||||
#define SOC_GDMA_TRIG_PERIPH_UHCI0_BUS SOC_GDMA_BUS_AHB
|
||||
#define SOC_GDMA_TRIG_PERIPH_I2S0_BUS SOC_GDMA_BUS_AHB
|
||||
#define SOC_GDMA_TRIG_PERIPH_SHA0_BUS SOC_GDMA_BUS_AHB
|
||||
#define SOC_GDMA_TRIG_PERIPH_ADC0_BUS SOC_GDMA_BUS_AHB
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -36,7 +36,7 @@
|
||||
#define DR_REG_HP_SYSTEM_BASE 0x60095000
|
||||
#define DR_REG_PCR_BASE 0x60096000
|
||||
#define DR_REG_TEE_REG_BASE 0x60098000
|
||||
#define DR_REG_HP_APM_REG_BASE 0x60099000
|
||||
#define DR_REG_HP_APM_BASE 0x60099000
|
||||
#define DR_REG_MISC_BASE 0x6009F000
|
||||
#define DR_REG_MODEM0_BASE 0x600A0000
|
||||
#define DR_REG_MODEM1_BASE 0x600AC000
|
||||
|
||||
@@ -20,13 +20,13 @@
|
||||
// \#define SOC_ADC_SUPPORTED 1 //TODO: [ESP32C61] IDF-9302, IDF-9303, IDF-9304
|
||||
#define SOC_DEDICATED_GPIO_SUPPORTED 1
|
||||
#define SOC_UART_SUPPORTED 1
|
||||
// \#define SOC_GDMA_SUPPORTED 1 //TODO: [ESP32C61] IDF-9310, IDF-9311
|
||||
// \#define SOC_AHB_GDMA_SUPPORTED 1 //TODO: [ESP32C61] IDF-9310, IDF-9311
|
||||
#define SOC_GDMA_SUPPORTED 1
|
||||
#define SOC_AHB_GDMA_SUPPORTED 1
|
||||
#define SOC_GPTIMER_SUPPORTED 1
|
||||
// \#define SOC_BT_SUPPORTED 1
|
||||
// \#define SOC_IEEE802154_SUPPORTED 1
|
||||
// \#define SOC_ASYNC_MEMCPY_SUPPORTED 1 //TODO: [ESP32C61] IDF-9315
|
||||
#define SOC_USB_SERIAL_JTAG_SUPPORTED 1
|
||||
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
|
||||
// \#define SOC_TEMP_SENSOR_SUPPORTED 1 //TODO: [ESP32C61] IDF-9322
|
||||
// \#define SOC_WIFI_SUPPORTED 1
|
||||
#define SOC_SUPPORTS_SECURE_DL_MODE 1
|
||||
@@ -143,13 +143,15 @@
|
||||
#define SOC_CPU_IDRAM_SPLIT_USING_PMP 1
|
||||
#define SOC_CPU_PMP_REGION_GRANULARITY 128 // TODO IDF-9580 check when doing PMP bringup
|
||||
|
||||
/*-------------------------- DMA Common CAPS ----------------------------------------*/
|
||||
#define SOC_DMA_CAN_ACCESS_FLASH 1 /*!< DMA can access Flash memory */
|
||||
|
||||
//TODO: [ESP32C61] IDF-9310
|
||||
/*-------------------------- GDMA CAPS -------------------------------------*/
|
||||
// \#define SOC_AHB_GDMA_VERSION 1U
|
||||
// \#define SOC_GDMA_NUM_GROUPS_MAX 1U
|
||||
// \#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3
|
||||
// \#define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule
|
||||
#define SOC_AHB_GDMA_VERSION 2U
|
||||
#define SOC_GDMA_NUM_GROUPS_MAX 1U
|
||||
#define SOC_GDMA_PAIRS_PER_GROUP_MAX 2
|
||||
// \#define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule TODO: IDF-9964
|
||||
// \#define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 // TODO: IDF-10380
|
||||
|
||||
/*-------------------------- ETM CAPS --------------------------------------*/
|
||||
#define SOC_ETM_GROUPS 1U // Number of ETM groups
|
||||
|
||||
@@ -92,33 +92,24 @@
|
||||
#define RTC_EVT_TICK 84
|
||||
#define RTC_EVT_OVF 85
|
||||
#define RTC_EVT_CMP 86
|
||||
#define GDMA_AHB_EVT_IN_DONE_CH0 87
|
||||
#define GDMA_AHB_EVT_IN_DONE_CH1 88
|
||||
#define GDMA_AHB_EVT_IN_DONE_CH2 89
|
||||
#define GDMA_AHB_EVT_IN_SUC_EOF_CH0 90
|
||||
#define GDMA_AHB_EVT_IN_SUC_EOF_CH1 91
|
||||
#define GDMA_AHB_EVT_IN_SUC_EOF_CH2 92
|
||||
#define GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0 93
|
||||
#define GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1 94
|
||||
#define GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2 95
|
||||
#define GDMA_AHB_EVT_IN_FIFO_FULL_CH0 96
|
||||
#define GDMA_AHB_EVT_IN_FIFO_FULL_CH1 97
|
||||
#define GDMA_AHB_EVT_IN_FIFO_FULL_CH2 98
|
||||
#define GDMA_AHB_EVT_OUT_DONE_CH0 99
|
||||
#define GDMA_AHB_EVT_OUT_DONE_CH1 100
|
||||
#define GDMA_AHB_EVT_OUT_DONE_CH2 101
|
||||
#define GDMA_AHB_EVT_OUT_EOF_CH0 102
|
||||
#define GDMA_AHB_EVT_OUT_EOF_CH1 103
|
||||
#define GDMA_AHB_EVT_OUT_EOF_CH2 104
|
||||
#define GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0 105
|
||||
#define GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1 106
|
||||
#define GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2 107
|
||||
#define GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0 108
|
||||
#define GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1 109
|
||||
#define GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2 110
|
||||
#define GDMA_AHB_EVT_OUT_FIFO_FULL_CH0 111
|
||||
#define GDMA_AHB_EVT_OUT_FIFO_FULL_CH1 112
|
||||
#define GDMA_AHB_EVT_OUT_FIFO_FULL_CH2 113
|
||||
#define GDMA_EVT_IN_DONE_CH0 87
|
||||
#define GDMA_EVT_IN_DONE_CH1 88
|
||||
#define GDMA_EVT_IN_SUC_EOF_CH0 90
|
||||
#define GDMA_EVT_IN_SUC_EOF_CH1 91
|
||||
#define GDMA_EVT_IN_FIFO_EMPTY_CH0 93
|
||||
#define GDMA_EVT_IN_FIFO_EMPTY_CH1 94
|
||||
#define GDMA_EVT_IN_FIFO_FULL_CH0 96
|
||||
#define GDMA_EVT_IN_FIFO_FULL_CH1 97
|
||||
#define GDMA_EVT_OUT_DONE_CH0 99
|
||||
#define GDMA_EVT_OUT_DONE_CH1 100
|
||||
#define GDMA_EVT_OUT_EOF_CH0 102
|
||||
#define GDMA_EVT_OUT_EOF_CH1 103
|
||||
#define GDMA_EVT_OUT_TOTAL_EOF_CH0 105
|
||||
#define GDMA_EVT_OUT_TOTAL_EOF_CH1 106
|
||||
#define GDMA_EVT_OUT_FIFO_EMPTY_CH0 108
|
||||
#define GDMA_EVT_OUT_FIFO_EMPTY_CH1 109
|
||||
#define GDMA_EVT_OUT_FIFO_FULL_CH0 111
|
||||
#define GDMA_EVT_OUT_FIFO_FULL_CH1 112
|
||||
#define PMU_EVT_SLEEP_WEEKUP 114
|
||||
#define GPIO_TASK_CH0_SET 1
|
||||
#define GPIO_TASK_CH1_SET 2
|
||||
@@ -244,10 +235,8 @@
|
||||
#define RTC_TASK_STOP 122
|
||||
#define RTC_TASK_CLR 123
|
||||
#define RTC_TASK_TRIGGERFLW 124
|
||||
#define GDMA_AHB_TASK_IN_START_CH0 125
|
||||
#define GDMA_AHB_TASK_IN_START_CH1 126
|
||||
#define GDMA_AHB_TASK_IN_START_CH2 127
|
||||
#define GDMA_AHB_TASK_OUT_START_CH0 128
|
||||
#define GDMA_AHB_TASK_OUT_START_CH1 129
|
||||
#define GDMA_AHB_TASK_OUT_START_CH2 130
|
||||
#define GDMA_TASK_IN_START_CH0 125
|
||||
#define GDMA_TASK_IN_START_CH1 126
|
||||
#define GDMA_TASK_OUT_START_CH0 128
|
||||
#define GDMA_TASK_OUT_START_CH1 129
|
||||
#define PMU_TASK_SLEEP_REQ 131
|
||||
|
||||
Reference in New Issue
Block a user