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adc: refactor adc single read api on esp32c3

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This commit is contained in:
Armando
2021-02-23 21:40:15 +08:00
parent 69a0f8b9bb
commit 00a3f48bd8
7 changed files with 232 additions and 451 deletions
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1
components/hal/esp32c3/adc_hal.c
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@@ -72,7 +72,6 @@ void adc_hal_digi_controller_config(const adc_digi_config_t *cfg)
}
}
adc_ll_set_controller(pattern_both, ADC_CTRL_DIG);
if (cfg->conv_limit_en) {
adc_ll_digi_set_convert_limit_num(cfg->conv_limit_num);
adc_ll_digi_convert_limit_enable();

164
components/hal/esp32c3/include/hal/adc_ll.h
View File

@@ -54,8 +54,12 @@ typedef enum {
} adc_ll_rtc_raw_data_t;
typedef enum {
ADC_LL_INTR_ADC2_DONE = BIT(30),
ADC_LL_INTR_ADC1_DONE = BIT(31),
ADC_LL_INTR_THRES1_LOW = BIT(26),
ADC_LL_INTR_THRES0_LOW = BIT(27),
ADC_LL_INTR_THRES1_HIGH = BIT(28),
ADC_LL_INTR_THRES0_HIGH = BIT(29),
ADC_LL_INTR_ADC2_DONE = BIT(30),
ADC_LL_INTR_ADC1_DONE = BIT(31),
} adc_ll_intr_t;
FLAG_ATTR(adc_ll_intr_t)
@@ -391,136 +395,6 @@ static inline void adc_ll_digi_monitor_disable(adc_digi_monitor_idx_t idx)
}
}
/**
* Enable interrupt of adc digital controller by bitmask.
*
* @param adc_n ADC unit.
* @param intr Interrupt bitmask.
*/
static inline void adc_ll_digi_intr_enable(adc_ll_num_t adc_n, adc_digi_intr_t intr)
{
if (adc_n == ADC_NUM_1) {
if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) {
APB_SARADC.int_ena.adc1_done = 1;
}
} else { // adc_n == ADC_NUM_2
if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) {
APB_SARADC.int_ena.adc2_done = 1;
}
}
if (intr & ADC_DIGI_INTR_MASK_MONITOR0_HIGH) {
APB_SARADC.int_ena.thres0_high = 1;
}
if (intr & ADC_DIGI_INTR_MASK_MONITOR0_LOW) {
APB_SARADC.int_ena.thres0_low = 1;
}
if (intr & ADC_DIGI_INTR_MASK_MONITOR1_HIGH) {
APB_SARADC.int_ena.thres1_high = 1;
}
if (intr & ADC_DIGI_INTR_MASK_MONITOR1_LOW) {
APB_SARADC.int_ena.thres1_low = 1;
}
}
/**
* Disable interrupt of adc digital controller by bitmask.
*
* @param adc_n ADC unit.
* @param intr Interrupt bitmask.
*/
static inline void adc_ll_digi_intr_disable(adc_ll_num_t adc_n, adc_digi_intr_t intr)
{
if (adc_n == ADC_NUM_1) {
if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) {
APB_SARADC.int_ena.adc1_done = 0;
}
} else { // adc_n == ADC_NUM_2
if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) {
APB_SARADC.int_ena.adc2_done = 0;
}
}
if (intr & ADC_DIGI_INTR_MASK_MONITOR0_HIGH) {
APB_SARADC.int_ena.thres0_high = 0;
}
if (intr & ADC_DIGI_INTR_MASK_MONITOR0_LOW) {
APB_SARADC.int_ena.thres0_low = 0;
}
if (intr & ADC_DIGI_INTR_MASK_MONITOR1_HIGH) {
APB_SARADC.int_ena.thres1_high = 0;
}
if (intr & ADC_DIGI_INTR_MASK_MONITOR1_LOW) {
APB_SARADC.int_ena.thres1_low = 0;
}
}
/**
* Clear interrupt of adc digital controller by bitmask.
*
* @param adc_n ADC unit.
* @param intr Interrupt bitmask.
*/
static inline void adc_ll_digi_intr_clear(adc_ll_num_t adc_n, adc_digi_intr_t intr)
{
if (adc_n == ADC_NUM_1) {
if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) {
APB_SARADC.int_clr.adc1_done = 1;
}
} else { // adc_n == ADC_NUM_2
if (intr & ADC_DIGI_INTR_MASK_MEAS_DONE) {
APB_SARADC.int_clr.adc2_done = 1;
}
}
if (intr & ADC_DIGI_INTR_MASK_MONITOR0_HIGH) {
APB_SARADC.int_clr.thres0_high = 1;
}
if (intr & ADC_DIGI_INTR_MASK_MONITOR0_LOW) {
APB_SARADC.int_clr.thres0_low = 1;
}
if (intr & ADC_DIGI_INTR_MASK_MONITOR1_HIGH) {
APB_SARADC.int_clr.thres1_high = 1;
}
if (intr & ADC_DIGI_INTR_MASK_MONITOR1_LOW) {
APB_SARADC.int_clr.thres1_low = 1;
}
}
/**
* Get interrupt status mask of adc digital controller.
*
* @param adc_n ADC unit.
* @return
* - intr Interrupt bitmask.
*/
static inline uint32_t adc_ll_digi_get_intr_status(adc_ll_num_t adc_n)
{
uint32_t int_st = APB_SARADC.int_st.val;
uint32_t ret_msk = 0;
if (adc_n == ADC_NUM_1) {
if (int_st & APB_SARADC_ADC1_DONE_INT_ST_M) {
ret_msk |= ADC_DIGI_INTR_MASK_MEAS_DONE;
}
} else { // adc_n == ADC_NUM_2
if (int_st & APB_SARADC_ADC2_DONE_INT_ST_M) {
ret_msk |= ADC_DIGI_INTR_MASK_MEAS_DONE;
}
}
if (int_st & APB_SARADC_THRES0_HIGH_INT_ST) {
ret_msk |= ADC_DIGI_INTR_MASK_MONITOR0_HIGH;
}
if (int_st & APB_SARADC_THRES0_LOW_INT_ST_M) {
ret_msk |= ADC_DIGI_INTR_MASK_MONITOR0_LOW;
}
if (int_st & APB_SARADC_THRES1_HIGH_INT_ST_M) {
ret_msk |= ADC_DIGI_INTR_MASK_MONITOR1_HIGH;
}
if (int_st & APB_SARADC_THRES1_LOW_INT_ST_M) {
ret_msk |= ADC_DIGI_INTR_MASK_MONITOR1_LOW;
}
return ret_msk;
}
/**
* Set DMA eof num of adc digital controller.
* If the number of measurements reaches `dma_eof_num`, then `dma_in_suc_eof` signal is generated.
@@ -653,17 +527,6 @@ static inline adc_ll_power_t adc_ll_get_power_manage(void)
return manage;
}
/**
* Set ADC module controller.
* @param adc_n ADC unit.
* @param ctrl ADC controller.
*/
static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_ll_controller_t ctrl)
{
//This is for chip version compability. On esp32c3, the ADC1 is only controlled by digital controller, whereas ADC2 controller is
//auto-selected by arbiter according to the priority.
}
/**
* Set ADC2 module arbiter work mode.
* The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority,
@@ -911,10 +774,13 @@ static inline bool adc_ll_intr_get_status(adc_ll_intr_t mask)
return (APB_SARADC.int_st.val & mask);
}
//--------------------------------adc1------------------------------//
static inline void adc_ll_adc1_onetime_sample_enable(bool enable)
static inline void adc_ll_onetime_sample_enable(adc_ll_num_t adc_n, bool enable)
{
APB_SARADC.onetime_sample.adc1_onetime_sample = enable;
if (adc_n == ADC_NUM_1) {
APB_SARADC.onetime_sample.adc1_onetime_sample = enable;
} else {
APB_SARADC.onetime_sample.adc2_onetime_sample = enable;
}
}
static inline uint32_t adc_ll_adc1_read(void)
@@ -923,12 +789,6 @@ static inline uint32_t adc_ll_adc1_read(void)
return (APB_SARADC.apb_saradc1_data_status.adc1_data & 0xfff);
}
//--------------------------------adc2------------------------------//
static inline void adc_ll_adc2_onetime_sample_enable(bool enable)
{
APB_SARADC.onetime_sample.adc2_onetime_sample = enable;
}
static inline uint32_t adc_ll_adc2_read(void)
{
//On ESP32C3, valid data width is 12-bit