alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-15 06:26:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

feat(spi_master): p4 add master driver supported

Browse Source
This commit is contained in:
wanlei
2023-08-31 19:17:40 +08:00
parent 5306b3308f
commit 00fcdce725
29 changed files with 1728 additions and 540 deletions
Download Patch File Download Diff File Expand all files Collapse all files

26
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
View File

@@ -71,6 +71,10 @@ config SOC_I2S_SUPPORTED
bool
default y
config SOC_GPSPI_SUPPORTED
bool
default y
config SOC_I2C_SUPPORTED
bool
default y
@@ -801,25 +805,21 @@ config SOC_SDM_CLK_SUPPORT_XTAL
config SOC_SPI_PERIPH_NUM
int
default 2
default 3
config SOC_SPI_MAX_CS_NUM
int
default 6
config SOC_MEMSPI_IS_INDEPENDENT
bool
default y
config SOC_SPI_MAXIMUM_BUFFER_SIZE
int
default 64
config SOC_SPI_SUPPORT_DDRCLK
config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
bool
default y
config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
config SOC_SPI_SUPPORT_DDRCLK
bool
default y
@@ -827,23 +827,15 @@ config SOC_SPI_SUPPORT_CD_SIG
bool
default y
config SOC_SPI_SUPPORT_CONTINUOUS_TRANS
config SOC_SPI_SUPPORT_OCT
bool
default y
config SOC_SPI_SUPPORT_SLAVE_HD_VER2
bool
default n
config SOC_SPI_SUPPORT_CLK_XTAL
bool
default y
config SOC_SPI_SUPPORT_CLK_PLL_F80M
bool
default y
config SOC_SPI_SUPPORT_CLK_RC_FAST
config SOC_MEMSPI_IS_INDEPENDENT
bool
default y

12
components/soc/esp32p4/include/soc/clk_tree_defs.h
View File

@@ -370,16 +370,20 @@ typedef enum {
/**
* @brief Array initializer for all supported clock sources of SPI
*/
#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
#define SOC_SPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_SPLL}
/**
* @brief Type of SPI clock source.
*/
typedef enum {
SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */
SPI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */
SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */
SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock */
#if SOC_CLK_TREE_SUPPORTED
SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,
SPI_CLK_SRC_SPLL_480 = SOC_MOD_CLK_SPLL,
SPI_CLK_SRC_DEFAULT = SPI_CLK_SRC_SPLL_480, /*!< Select SPLL_480M as SPI source clock */
#else
SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */
#endif
} soc_periph_spi_clk_src_t;
/////////////////////////////////////////////////PSRAM////////////////////////////////////////////////////////////////////

1
components/soc/esp32p4/include/soc/ext_mem_defs.h
View File

@@ -57,6 +57,7 @@ extern "C" {
#define SOC_MMU_FLASH_SENSITIVE BIT(13)
#define SOC_MMU_PSRAM_SENSITIVE BIT(12)
#define SOC_NON_CACHEABLE_OFFSET 0x40000000
/**
* MMU entry valid bit mask for mapping value.

26
components/soc/esp32p4/include/soc/soc_caps.h
View File

@@ -52,7 +52,7 @@
#define SOC_I2S_SUPPORTED 1
// #define SOC_RMT_SUPPORTED 1 //TODO: IDF-7476
// #define SOC_SDM_SUPPORTED 1 //TODO: IDF-7551
// #define SOC_GPSPI_SUPPORTED 1 //TODO: IDF-7502, TODO: IDF-7503
#define SOC_GPSPI_SUPPORTED 1
// #define SOC_LEDC_SUPPORTED 1 //TODO: IDF-6510
#define SOC_I2C_SUPPORTED 1 //TODO: IDF-6507, TODO: IDF-7491
#define SOC_SYSTIMER_SUPPORTED 1
@@ -377,29 +377,29 @@
#define SOC_SDM_CLK_SUPPORT_PLL_F80M 1
#define SOC_SDM_CLK_SUPPORT_XTAL 1
// TODO: IDF-5334 (Copy from esp32c3, need check)
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 2
#define SOC_SPI_PERIPH_CS_NUM(i) 6
#define SOC_SPI_MAX_CS_NUM 6
#define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_SPI_PERIPH_NUM 3
#define SOC_SPI_PERIPH_CS_NUM(i) (((i)==0)? 2: (((i)==1)? 6: 3))
#define SOC_SPI_MAX_CS_NUM 6
#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
#define SOC_SPI_SUPPORT_DDRCLK 1
// #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 //TODO: IDF-7505
#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
#define SOC_SPI_SUPPORT_DDRCLK 1
#define SOC_SPI_SUPPORT_CD_SIG 1
#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 0
#define SOC_SPI_SUPPORT_OCT 1
#define SOC_SPI_SUPPORT_CLK_XTAL 1
#define SOC_SPI_SUPPORT_CLK_PLL_F80M 1
#define SOC_SPI_SUPPORT_CLK_RC_FAST 1
// #define SOC_SPI_SUPPORT_CLK_RC_FAST 1 //bellow clks are waiting for clock tree
// #define SOC_SPI_SUPPORT_CLK_SPLL_F480M 1 //super pll
// #define SOC_SPI_SUPPORT_CLK_SDIO 1 //sdio pll
// #define SOC_SPI_SUPPORT_CLK_APLL 1 //audio pll
// Peripheral supports DIO, DOUT, QIO, or QOUT
// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;})
#define SOC_SPI_MAX_PRE_DIVIDER 16
#define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_SPI_MAX_PRE_DIVIDER 16
/*-------------------------- SPI MEM CAPS ---------------------------------------*/
#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)

24
components/soc/esp32p4/include/soc/spi_pins.h
View File

@@ -5,3 +5,27 @@
*/
#pragma once
// Normal IOMUX pins
#define SPI2_FUNC_NUM 3
#define SPI2_IOMUX_PIN_NUM_HD 6
#define SPI2_IOMUX_PIN_NUM_CS 7
#define SPI2_IOMUX_PIN_NUM_MOSI 8
#define SPI2_IOMUX_PIN_NUM_CLK 9
#define SPI2_IOMUX_PIN_NUM_MISO 10
#define SPI2_IOMUX_PIN_NUM_WP 11
// When using Octal SPI, we make use of SPI2_FUNC_NUM_OCT to route them as follows.
#define SPI2_FUNC_NUM_OCT 2
#define SPI2_IOMUX_PIN_NUM_HD_OCT 32
#define SPI2_IOMUX_PIN_NUM_CS_OCT 28
#define SPI2_IOMUX_PIN_NUM_MOSI_OCT 29
#define SPI2_IOMUX_PIN_NUM_CLK_OCT 30
#define SPI2_IOMUX_PIN_NUM_MISO_OCT 31
#define SPI2_IOMUX_PIN_NUM_WP_OCT 33
#define SPI2_IOMUX_PIN_NUM_IO4_OCT 34
#define SPI2_IOMUX_PIN_NUM_IO5_OCT 35
#define SPI2_IOMUX_PIN_NUM_IO6_OCT 36
#define SPI2_IOMUX_PIN_NUM_IO7_OCT 37
//SPI3 have no iomux pins

437
components/soc/esp32p4/include/soc/spi_struct.h
View File

@@ -839,198 +839,8 @@ typedef union {
uint32_t val;
} spi_dout_mode_reg_t;
/** Group: Interrupt registers */
/** Type of dma_int_ena register
* SPI interrupt enable register
*/
typedef union {
struct {
/** dma_infifo_full_err_int_ena : R/W; bitpos: [0]; default: 0;
* The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
*/
uint32_t dma_infifo_full_err_int_ena:1;
/** dma_outfifo_empty_err_int_ena : R/W; bitpos: [1]; default: 0;
* The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
*/
uint32_t dma_outfifo_empty_err_int_ena:1;
/** slv_ex_qpi_int_ena : R/W; bitpos: [2]; default: 0;
* The enable bit for SPI slave Ex_QPI interrupt.
*/
uint32_t slv_ex_qpi_int_ena:1;
/** slv_en_qpi_int_ena : R/W; bitpos: [3]; default: 0;
* The enable bit for SPI slave En_QPI interrupt.
*/
uint32_t slv_en_qpi_int_ena:1;
/** slv_cmd7_int_ena : R/W; bitpos: [4]; default: 0;
* The enable bit for SPI slave CMD7 interrupt.
*/
uint32_t slv_cmd7_int_ena:1;
/** slv_cmd8_int_ena : R/W; bitpos: [5]; default: 0;
* The enable bit for SPI slave CMD8 interrupt.
*/
uint32_t slv_cmd8_int_ena:1;
/** slv_cmd9_int_ena : R/W; bitpos: [6]; default: 0;
* The enable bit for SPI slave CMD9 interrupt.
*/
uint32_t slv_cmd9_int_ena:1;
/** slv_cmda_int_ena : R/W; bitpos: [7]; default: 0;
* The enable bit for SPI slave CMDA interrupt.
*/
uint32_t slv_cmda_int_ena:1;
/** slv_rd_dma_done_int_ena : R/W; bitpos: [8]; default: 0;
* The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
*/
uint32_t slv_rd_dma_done_int_ena:1;
/** slv_wr_dma_done_int_ena : R/W; bitpos: [9]; default: 0;
* The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
*/
uint32_t slv_wr_dma_done_int_ena:1;
/** slv_rd_buf_done_int_ena : R/W; bitpos: [10]; default: 0;
* The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
*/
uint32_t slv_rd_buf_done_int_ena:1;
/** slv_wr_buf_done_int_ena : R/W; bitpos: [11]; default: 0;
* The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
*/
uint32_t slv_wr_buf_done_int_ena:1;
/** trans_done_int_ena : R/W; bitpos: [12]; default: 0;
* The enable bit for SPI_TRANS_DONE_INT interrupt.
*/
uint32_t trans_done_int_ena:1;
/** dma_seg_trans_done_int_ena : R/W; bitpos: [13]; default: 0;
* The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
*/
uint32_t dma_seg_trans_done_int_ena:1;
/** seg_magic_err_int_ena : R/W; bitpos: [14]; default: 0;
* The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
*/
uint32_t seg_magic_err_int_ena:1; //this field is only for GPSPI2
/** slv_buf_addr_err_int_ena : R/W; bitpos: [15]; default: 0;
* The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
*/
uint32_t slv_buf_addr_err_int_ena:1;
/** slv_cmd_err_int_ena : R/W; bitpos: [16]; default: 0;
* The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
*/
uint32_t slv_cmd_err_int_ena:1;
/** mst_rx_afifo_wfull_err_int_ena : R/W; bitpos: [17]; default: 0;
* The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
*/
uint32_t mst_rx_afifo_wfull_err_int_ena:1;
/** mst_tx_afifo_rempty_err_int_ena : R/W; bitpos: [18]; default: 0;
* The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
*/
uint32_t mst_tx_afifo_rempty_err_int_ena:1;
/** app2_int_ena : R/W; bitpos: [19]; default: 0;
* The enable bit for SPI_APP2_INT interrupt.
*/
uint32_t app2_int_ena:1;
/** app1_int_ena : R/W; bitpos: [20]; default: 0;
* The enable bit for SPI_APP1_INT interrupt.
*/
uint32_t app1_int_ena:1;
uint32_t reserved_21:11;
};
uint32_t val;
} spi_dma_int_ena_reg_t;
/** Type of dma_int_clr register
* SPI interrupt clear register
*/
typedef union {
struct {
/** dma_infifo_full_err_int_clr : WT; bitpos: [0]; default: 0;
* The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
*/
uint32_t dma_infifo_full_err_int_clr:1;
/** dma_outfifo_empty_err_int_clr : WT; bitpos: [1]; default: 0;
* The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
*/
uint32_t dma_outfifo_empty_err_int_clr:1;
/** slv_ex_qpi_int_clr : WT; bitpos: [2]; default: 0;
* The clear bit for SPI slave Ex_QPI interrupt.
*/
uint32_t slv_ex_qpi_int_clr:1;
/** slv_en_qpi_int_clr : WT; bitpos: [3]; default: 0;
* The clear bit for SPI slave En_QPI interrupt.
*/
uint32_t slv_en_qpi_int_clr:1;
/** slv_cmd7_int_clr : WT; bitpos: [4]; default: 0;
* The clear bit for SPI slave CMD7 interrupt.
*/
uint32_t slv_cmd7_int_clr:1;
/** slv_cmd8_int_clr : WT; bitpos: [5]; default: 0;
* The clear bit for SPI slave CMD8 interrupt.
*/
uint32_t slv_cmd8_int_clr:1;
/** slv_cmd9_int_clr : WT; bitpos: [6]; default: 0;
* The clear bit for SPI slave CMD9 interrupt.
*/
uint32_t slv_cmd9_int_clr:1;
/** slv_cmda_int_clr : WT; bitpos: [7]; default: 0;
* The clear bit for SPI slave CMDA interrupt.
*/
uint32_t slv_cmda_int_clr:1;
/** slv_rd_dma_done_int_clr : WT; bitpos: [8]; default: 0;
* The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
*/
uint32_t slv_rd_dma_done_int_clr:1;
/** slv_wr_dma_done_int_clr : WT; bitpos: [9]; default: 0;
* The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
*/
uint32_t slv_wr_dma_done_int_clr:1;
/** slv_rd_buf_done_int_clr : WT; bitpos: [10]; default: 0;
* The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
*/
uint32_t slv_rd_buf_done_int_clr:1;
/** slv_wr_buf_done_int_clr : WT; bitpos: [11]; default: 0;
* The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
*/
uint32_t slv_wr_buf_done_int_clr:1;
/** trans_done_int_clr : WT; bitpos: [12]; default: 0;
* The clear bit for SPI_TRANS_DONE_INT interrupt.
*/
uint32_t trans_done_int_clr:1;
/** dma_seg_trans_done_int_clr : WT; bitpos: [13]; default: 0;
* The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
*/
uint32_t dma_seg_trans_done_int_clr:1;
/** seg_magic_err_int_clr : WT; bitpos: [14]; default: 0;
* The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
*/
uint32_t seg_magic_err_int_clr:1; //this field is only for GPSPI2
/** slv_buf_addr_err_int_clr : WT; bitpos: [15]; default: 0;
* The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
*/
uint32_t slv_buf_addr_err_int_clr:1;
/** slv_cmd_err_int_clr : WT; bitpos: [16]; default: 0;
* The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
*/
uint32_t slv_cmd_err_int_clr:1;
/** mst_rx_afifo_wfull_err_int_clr : WT; bitpos: [17]; default: 0;
* The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
*/
uint32_t mst_rx_afifo_wfull_err_int_clr:1;
/** mst_tx_afifo_rempty_err_int_clr : WT; bitpos: [18]; default: 0;
* The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
*/
uint32_t mst_tx_afifo_rempty_err_int_clr:1;
/** app2_int_clr : WT; bitpos: [19]; default: 0;
* The clear bit for SPI_APP2_INT interrupt.
*/
uint32_t app2_int_clr:1;
/** app1_int_clr : WT; bitpos: [20]; default: 0;
* The clear bit for SPI_APP1_INT interrupt.
*/
uint32_t app1_int_clr:1;
uint32_t reserved_21:11;
};
uint32_t val;
} spi_dma_int_clr_reg_t;
/** Type of dma_int_raw register
* SPI interrupt raw register
/** Type of dma_int register
* SPI interrupt raw/ena/clr/sta/set register
*/
typedef union {
struct {
@@ -1038,301 +848,112 @@ typedef union {
* 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the
* receive data. 0: Others.
*/
uint32_t dma_infifo_full_err_int_raw:1;
uint32_t dma_infifo_full_err_int:1;
/** dma_outfifo_empty_err_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
* master mode and send out all 0 in slave mode. 0: Others.
*/
uint32_t dma_outfifo_empty_err_int_raw:1;
uint32_t dma_outfifo_empty_err_int:1;
/** slv_ex_qpi_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission
* is ended. 0: Others.
*/
uint32_t slv_ex_qpi_int_raw:1;
uint32_t slv_ex_qpi_int:1;
/** slv_en_qpi_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
* The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission
* is ended. 0: Others.
*/
uint32_t slv_en_qpi_int_raw:1;
uint32_t slv_en_qpi_int:1;
/** slv_cmd7_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
* The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
* ended. 0: Others.
*/
uint32_t slv_cmd7_int_raw:1;
uint32_t slv_cmd7_int:1;
/** slv_cmd8_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
* The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
* ended. 0: Others.
*/
uint32_t slv_cmd8_int_raw:1;
uint32_t slv_cmd8_int:1;
/** slv_cmd9_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
* The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
* ended. 0: Others.
*/
uint32_t slv_cmd9_int_raw:1;
uint32_t slv_cmd9_int:1;
/** slv_cmda_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
* The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
* ended. 0: Others.
*/
uint32_t slv_cmda_int_raw:1;
uint32_t slv_cmda_int:1;
/** slv_rd_dma_done_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
* The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA
* transmission is ended. 0: Others.
*/
uint32_t slv_rd_dma_done_int_raw:1;
uint32_t slv_rd_dma_done_int:1;
/** slv_wr_dma_done_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
* The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA
* transmission is ended. 0: Others.
*/
uint32_t slv_wr_dma_done_int_raw:1;
uint32_t slv_wr_dma_done_int:1;
/** slv_rd_buf_done_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
* The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF
* transmission is ended. 0: Others.
*/
uint32_t slv_rd_buf_done_int_raw:1;
uint32_t slv_rd_buf_done_int:1;
/** slv_wr_buf_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
* The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF
* transmission is ended. 0: Others.
*/
uint32_t slv_wr_buf_done_int_raw:1;
uint32_t slv_wr_buf_done_int:1;
/** trans_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
* The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
* ended. 0: others.
*/
uint32_t trans_done_int_raw:1;
uint32_t trans_done_int:1;
/** dma_seg_trans_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
* The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA
* full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends.
* And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans
* is not ended or not occurred.
*/
uint32_t dma_seg_trans_done_int_raw:1;
uint32_t dma_seg_trans_done_int:1;
/** seg_magic_err_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
* The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer
* is error in the DMA seg-conf-trans. 0: others.
*/
uint32_t seg_magic_err_int_raw:1; //this field is only for GPSPI2
uint32_t seg_magic_err_int_raw:1; //this field is only forPI2
/** slv_buf_addr_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
* The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
* of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is
* bigger than 63. 0: Others.
*/
uint32_t slv_buf_addr_err_int_raw:1;
uint32_t slv_buf_addr_err_int:1;
/** slv_cmd_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
* The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
* current SPI slave HD mode transmission is not supported. 0: Others.
*/
uint32_t slv_cmd_err_int_raw:1;
uint32_t slv_cmd_err_int:1;
/** mst_rx_afifo_wfull_err_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
* The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
* write-full error when SPI inputs data in master mode. 0: Others.
*/
uint32_t mst_rx_afifo_wfull_err_int_raw:1;
uint32_t mst_rx_afifo_wfull_err_int:1;
/** mst_tx_afifo_rempty_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
* The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
* AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
*/
uint32_t mst_tx_afifo_rempty_err_int_raw:1;
uint32_t mst_tx_afifo_rempty_err_int:1;
/** app2_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
* The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.
*/
uint32_t app2_int_raw:1;
uint32_t app2_int:1;
/** app1_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
* The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.
*/
uint32_t app1_int_raw:1;
uint32_t app1_int:1;
uint32_t reserved_21:11;
};
uint32_t val;
} spi_dma_int_raw_reg_t;
/** Type of dma_int_st register
* SPI interrupt status register
*/
typedef union {
struct {
/** dma_infifo_full_err_int_st : RO; bitpos: [0]; default: 0;
* The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
*/
uint32_t dma_infifo_full_err_int_st:1;
/** dma_outfifo_empty_err_int_st : RO; bitpos: [1]; default: 0;
* The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
*/
uint32_t dma_outfifo_empty_err_int_st:1;
/** slv_ex_qpi_int_st : RO; bitpos: [2]; default: 0;
* The status bit for SPI slave Ex_QPI interrupt.
*/
uint32_t slv_ex_qpi_int_st:1;
/** slv_en_qpi_int_st : RO; bitpos: [3]; default: 0;
* The status bit for SPI slave En_QPI interrupt.
*/
uint32_t slv_en_qpi_int_st:1;
/** slv_cmd7_int_st : RO; bitpos: [4]; default: 0;
* The status bit for SPI slave CMD7 interrupt.
*/
uint32_t slv_cmd7_int_st:1;
/** slv_cmd8_int_st : RO; bitpos: [5]; default: 0;
* The status bit for SPI slave CMD8 interrupt.
*/
uint32_t slv_cmd8_int_st:1;
/** slv_cmd9_int_st : RO; bitpos: [6]; default: 0;
* The status bit for SPI slave CMD9 interrupt.
*/
uint32_t slv_cmd9_int_st:1;
/** slv_cmda_int_st : RO; bitpos: [7]; default: 0;
* The status bit for SPI slave CMDA interrupt.
*/
uint32_t slv_cmda_int_st:1;
/** slv_rd_dma_done_int_st : RO; bitpos: [8]; default: 0;
* The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
*/
uint32_t slv_rd_dma_done_int_st:1;
/** slv_wr_dma_done_int_st : RO; bitpos: [9]; default: 0;
* The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
*/
uint32_t slv_wr_dma_done_int_st:1;
/** slv_rd_buf_done_int_st : RO; bitpos: [10]; default: 0;
* The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
*/
uint32_t slv_rd_buf_done_int_st:1;
/** slv_wr_buf_done_int_st : RO; bitpos: [11]; default: 0;
* The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
*/
uint32_t slv_wr_buf_done_int_st:1;
/** trans_done_int_st : RO; bitpos: [12]; default: 0;
* The status bit for SPI_TRANS_DONE_INT interrupt.
*/
uint32_t trans_done_int_st:1;
/** dma_seg_trans_done_int_st : RO; bitpos: [13]; default: 0;
* The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
*/
uint32_t dma_seg_trans_done_int_st:1;
/** seg_magic_err_int_st : RO; bitpos: [14]; default: 0;
* The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
*/
uint32_t seg_magic_err_int_st:1; //this field is only for GPSPI2
/** slv_buf_addr_err_int_st : RO; bitpos: [15]; default: 0;
* The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
*/
uint32_t slv_buf_addr_err_int_st:1;
/** slv_cmd_err_int_st : RO; bitpos: [16]; default: 0;
* The status bit for SPI_SLV_CMD_ERR_INT interrupt.
*/
uint32_t slv_cmd_err_int_st:1;
/** mst_rx_afifo_wfull_err_int_st : RO; bitpos: [17]; default: 0;
* The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
*/
uint32_t mst_rx_afifo_wfull_err_int_st:1;
/** mst_tx_afifo_rempty_err_int_st : RO; bitpos: [18]; default: 0;
* The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
*/
uint32_t mst_tx_afifo_rempty_err_int_st:1;
/** app2_int_st : RO; bitpos: [19]; default: 0;
* The status bit for SPI_APP2_INT interrupt.
*/
uint32_t app2_int_st:1;
/** app1_int_st : RO; bitpos: [20]; default: 0;
* The status bit for SPI_APP1_INT interrupt.
*/
uint32_t app1_int_st:1;
uint32_t reserved_21:11;
};
uint32_t val;
} spi_dma_int_st_reg_t;
/** Type of dma_int_set register
* SPI interrupt software set register
*/
typedef union {
struct {
/** dma_infifo_full_err_int_set : WT; bitpos: [0]; default: 0;
* The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
*/
uint32_t dma_infifo_full_err_int_set:1;
/** dma_outfifo_empty_err_int_set : WT; bitpos: [1]; default: 0;
* The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
*/
uint32_t dma_outfifo_empty_err_int_set:1;
/** slv_ex_qpi_int_set : WT; bitpos: [2]; default: 0;
* The software set bit for SPI slave Ex_QPI interrupt.
*/
uint32_t slv_ex_qpi_int_set:1;
/** slv_en_qpi_int_set : WT; bitpos: [3]; default: 0;
* The software set bit for SPI slave En_QPI interrupt.
*/
uint32_t slv_en_qpi_int_set:1;
/** slv_cmd7_int_set : WT; bitpos: [4]; default: 0;
* The software set bit for SPI slave CMD7 interrupt.
*/
uint32_t slv_cmd7_int_set:1;
/** slv_cmd8_int_set : WT; bitpos: [5]; default: 0;
* The software set bit for SPI slave CMD8 interrupt.
*/
uint32_t slv_cmd8_int_set:1;
/** slv_cmd9_int_set : WT; bitpos: [6]; default: 0;
* The software set bit for SPI slave CMD9 interrupt.
*/
uint32_t slv_cmd9_int_set:1;
/** slv_cmda_int_set : WT; bitpos: [7]; default: 0;
* The software set bit for SPI slave CMDA interrupt.
*/
uint32_t slv_cmda_int_set:1;
/** slv_rd_dma_done_int_set : WT; bitpos: [8]; default: 0;
* The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
*/
uint32_t slv_rd_dma_done_int_set:1;
/** slv_wr_dma_done_int_set : WT; bitpos: [9]; default: 0;
* The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
*/
uint32_t slv_wr_dma_done_int_set:1;
/** slv_rd_buf_done_int_set : WT; bitpos: [10]; default: 0;
* The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
*/
uint32_t slv_rd_buf_done_int_set:1;
/** slv_wr_buf_done_int_set : WT; bitpos: [11]; default: 0;
* The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
*/
uint32_t slv_wr_buf_done_int_set:1;
/** trans_done_int_set : WT; bitpos: [12]; default: 0;
* The software set bit for SPI_TRANS_DONE_INT interrupt.
*/
uint32_t trans_done_int_set:1;
/** dma_seg_trans_done_int_set : WT; bitpos: [13]; default: 0;
* The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
*/
uint32_t dma_seg_trans_done_int_set:1;
/** seg_magic_err_int_set : WT; bitpos: [14]; default: 0;
* The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.
*/
uint32_t seg_magic_err_int_set:1; //this field is only for GPSPI2
/** slv_buf_addr_err_int_set : WT; bitpos: [15]; default: 0;
* The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
*/
uint32_t slv_buf_addr_err_int_set:1;
/** slv_cmd_err_int_set : WT; bitpos: [16]; default: 0;
* The software set bit for SPI_SLV_CMD_ERR_INT interrupt.
*/
uint32_t slv_cmd_err_int_set:1;
/** mst_rx_afifo_wfull_err_int_set : WT; bitpos: [17]; default: 0;
* The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
*/
uint32_t mst_rx_afifo_wfull_err_int_set:1;
/** mst_tx_afifo_rempty_err_int_set : WT; bitpos: [18]; default: 0;
* The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
*/
uint32_t mst_tx_afifo_rempty_err_int_set:1;
/** app2_int_set : WT; bitpos: [19]; default: 0;
* The software set bit for SPI_APP2_INT interrupt.
*/
uint32_t app2_int_set:1;
/** app1_int_set : WT; bitpos: [20]; default: 0;
* The software set bit for SPI_APP1_INT interrupt.
*/
uint32_t app1_int_set:1;
uint32_t reserved_21:11;
};
uint32_t val;
} spi_dma_int_set_reg_t;
} spi_dma_int_reg_t;
/** Type of wn register
* SPI CPU-controlled buffer
@@ -1378,11 +999,11 @@ typedef struct {
volatile spi_din_num_reg_t din_num;
volatile spi_dout_mode_reg_t dout_mode;
volatile spi_dma_conf_reg_t dma_conf;
volatile spi_dma_int_ena_reg_t dma_int_ena;
volatile spi_dma_int_clr_reg_t dma_int_clr;
volatile spi_dma_int_raw_reg_t dma_int_raw;
volatile spi_dma_int_st_reg_t dma_int_st;
volatile spi_dma_int_set_reg_t dma_int_set;
volatile spi_dma_int_reg_t dma_int_ena;
volatile spi_dma_int_reg_t dma_int_clr;
volatile spi_dma_int_reg_t dma_int_raw;
volatile spi_dma_int_reg_t dma_int_sta;
volatile spi_dma_int_reg_t dma_int_set;
uint32_t reserved_048[20];
volatile spi_wn_reg_t data_buf[16];
uint32_t reserved_0d8[2];