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gptimer: unify clock setting with clk_tree API

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This commit is contained in:
morris
2022-12-30 15:56:08 +08:00
parent 080fd7e14f
commit 044a114e66
12 changed files with 113 additions and 140 deletions
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110
components/driver/gptimer/gptimer.c
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -27,6 +27,7 @@
#include "esp_private/periph_ctrl.h"
#include "esp_private/esp_clk.h"
#include "clk_ctrl_os.h"
#include "clk_tree.h"
#include "gptimer_priv.h"
static const char *TAG = "gptimer";
@@ -402,67 +403,58 @@ static void gptimer_release_group_handle(gptimer_group_t *group)
static esp_err_t gptimer_select_periph_clock(gptimer_t *timer, gptimer_clock_source_t src_clk, uint32_t resolution_hz)
{
unsigned int counter_src_hz = 0;
esp_err_t ret = ESP_OK;
uint32_t counter_src_hz = 0;
int timer_id = timer->timer_id;
// [clk_tree] TODO: replace the following switch table by clk_tree API
switch (src_clk) {
#if SOC_TIMER_GROUP_SUPPORT_APB
case GPTIMER_CLK_SRC_APB:
counter_src_hz = esp_clk_apb_freq();
#if CONFIG_PM_ENABLE
sprintf(timer->pm_lock_name, "gptimer_%d_%d", timer->group->group_id, timer_id); // e.g. gptimer_0_0
ret = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, timer->pm_lock_name, &timer->pm_lock);
ESP_RETURN_ON_ERROR(ret, TAG, "create APB_FREQ_MAX lock failed");
ESP_LOGD(TAG, "install APB_FREQ_MAX lock for timer (%d,%d)", timer->group->group_id, timer_id);
#endif
break;
#endif // SOC_TIMER_GROUP_SUPPORT_APB
#if SOC_TIMER_GROUP_SUPPORT_PLL_F40M
case GPTIMER_CLK_SRC_PLL_F40M:
counter_src_hz = 40 * 1000 * 1000;
#if CONFIG_PM_ENABLE
sprintf(timer->pm_lock_name, "gptimer_%d_%d", timer->group->group_id, timer_id); // e.g. gptimer_0_0
// on ESP32C2, PLL_F40M is unavailable when CPU clock source switches from PLL to XTAL, so we're acquiring a "APB" lock here to prevent the clock switch
ret = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, timer->pm_lock_name, &timer->pm_lock);
ESP_RETURN_ON_ERROR(ret, TAG, "create APB_FREQ_MAX lock failed");
ESP_LOGD(TAG, "install APB_FREQ_MAX lock for timer (%d,%d)", timer->group->group_id, timer_id);
#endif
break;
#endif // SOC_TIMER_GROUP_SUPPORT_PLL_F40M
#if SOC_TIMER_GROUP_SUPPORT_PLL_F80M
case GPTIMER_CLK_SRC_PLL_F80M:
counter_src_hz = 80 * 1000 * 1000;
#if CONFIG_PM_ENABLE
sprintf(timer->pm_lock_name, "gptimer_%d_%d", timer->group->group_id, timer_id); // e.g. gptimer_0_0
// ESP32C6 PLL_F80M is available when SOC_ROOT_CLK switches to XTAL
ret = esp_pm_lock_create(ESP_PM_NO_LIGHT_SLEEP, 0, timer->pm_lock_name, &timer->pm_lock);
ESP_RETURN_ON_ERROR(ret, TAG, "create NO_LIGHT_SLEEP lock failed");
ESP_LOGD(TAG, "install NO_LIGHT_SLEEP lock for timer (%d,%d)", timer->group->group_id, timer_id);
#endif
break;
#endif // SOC_TIMER_GROUP_SUPPORT_PLL_F80M
#if SOC_TIMER_GROUP_SUPPORT_AHB
case GPTIMER_CLK_SRC_AHB:
// TODO: decide which kind of PM lock we should use for such clock
counter_src_hz = 48 * 1000 * 1000;
break;
#endif // SOC_TIMER_GROUP_SUPPORT_AHB
#if SOC_TIMER_GROUP_SUPPORT_XTAL
case GPTIMER_CLK_SRC_XTAL:
counter_src_hz = esp_clk_xtal_freq();
break;
#endif // SOC_TIMER_GROUP_SUPPORT_XTAL
// TODO: [clk_tree] to use a generic clock enable/disable or acquire/release function for all clock source
#if SOC_TIMER_GROUP_SUPPORT_RC_FAST
case GPTIMER_CLK_SRC_RC_FAST:
if (src_clk == GPTIMER_CLK_SRC_RC_FAST) {
// RC_FAST clock is not enabled automatically on start up, we enable it here manually.
// Note there's a ref count in the enable/disable function, we must call them in pair in the driver.
periph_rtc_dig_clk8m_enable();
counter_src_hz = periph_rtc_dig_clk8m_get_freq();
break;
#endif // SOC_TIMER_GROUP_SUPPORT_RC_FAST
default:
ESP_RETURN_ON_FALSE(false, ESP_ERR_NOT_SUPPORTED, TAG, "clock source %d is not support", src_clk);
break;
}
#endif // SOC_TIMER_GROUP_SUPPORT_RC_FAST
// get clock source frequency
ESP_RETURN_ON_ERROR(clk_tree_src_get_freq_hz((soc_module_clk_t)src_clk, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &counter_src_hz),
TAG, "get clock source frequency failed");
#if CONFIG_PM_ENABLE
bool need_pm_lock = true;
// to make the gptimer work reliable, the source clock must stay alive and unchanged
// driver will create different pm lock for that purpose, according to different clock source
esp_pm_lock_type_t pm_lock_type = ESP_PM_NO_LIGHT_SLEEP;
#if SOC_TIMER_GROUP_SUPPORT_RC_FAST
if (src_clk == GPTIMER_CLK_SRC_RC_FAST) {
// RC_FAST won't be turn off in sleep and won't change its frequency during DFS
need_pm_lock = false;
}
#endif // SOC_TIMER_GROUP_SUPPORT_RC_FAST
#if SOC_TIMER_GROUP_SUPPORT_APB
if (src_clk == GPTIMER_CLK_SRC_APB) {
// APB clock frequency can be changed during DFS
pm_lock_type = ESP_PM_APB_FREQ_MAX;
}
#endif // SOC_TIMER_GROUP_SUPPORT_APB
#if CONFIG_IDF_TARGET_ESP32C2
if (src_clk == GPTIMER_CLK_SRC_PLL_F40M) {
// although PLL_F40M clock is a fixed PLL clock, which is unchangeable
// on ESP32C2, PLL_F40M can be turned off even during DFS (unlike other PLL clocks)
// so we're acquiring a fake "APB" lock here to prevent the system from doing DFS
pm_lock_type = ESP_PM_APB_FREQ_MAX;
}
#endif // CONFIG_IDF_TARGET_ESP32C2
if (need_pm_lock) {
sprintf(timer->pm_lock_name, "gptimer_%d_%d", timer->group->group_id, timer_id); // e.g. gptimer_0_0
ESP_RETURN_ON_ERROR(esp_pm_lock_create(pm_lock_type, 0, timer->pm_lock_name, &timer->pm_lock),
TAG, "create pm lock failed");
}
#endif // CONFIG_PM_ENABLE
timer_ll_set_clock_source(timer->hal.dev, timer_id, src_clk);
timer->clk_src = src_clk;
unsigned int prescale = counter_src_hz / resolution_hz; // potential resolution loss here
@@ -471,7 +463,7 @@ static esp_err_t gptimer_select_periph_clock(gptimer_t *timer, gptimer_clock_sou
if (timer->resolution_hz != resolution_hz) {
ESP_LOGW(TAG, "resolution lost, expect %"PRIu32", real %"PRIu32, resolution_hz, timer->resolution_hz);
}
return ret;
return ESP_OK;
}
// Put the default ISR handler in the IRAM for better performance