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Merge branch 'master' into feature/esp32s2beta_update

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This commit is contained in:
Angus Gratton
2019-08-08 14:00:45 +10:00
committed by Angus Gratton
parent 24d26fccde 51d811a71c
commit 04ae56806c
657 changed files with 6814 additions and 7534 deletions
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30
components/spi_flash/cache_utils.c
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@@ -51,18 +51,18 @@ static volatile bool s_flash_op_complete = false;
static volatile int s_flash_op_cpu = -1;
#endif
void spi_flash_init_lock()
void spi_flash_init_lock(void)
{
s_flash_op_mutex = xSemaphoreCreateRecursiveMutex();
assert(s_flash_op_mutex != NULL);
}
void spi_flash_op_lock()
void spi_flash_op_lock(void)
{
xSemaphoreTakeRecursive(s_flash_op_mutex, portMAX_DELAY);
}
void spi_flash_op_unlock()
void spi_flash_op_unlock(void)
{
xSemaphoreGiveRecursive(s_flash_op_mutex);
}
@@ -96,7 +96,7 @@ void IRAM_ATTR spi_flash_op_block_func(void* arg)
xTaskResumeAll();
}
void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu()
void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu(void)
{
spi_flash_op_lock();
@@ -147,7 +147,7 @@ void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu()
spi_flash_disable_cache(other_cpuid, &s_flash_op_cache_state[other_cpuid]);
}
void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu()
void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu(void)
{
const uint32_t cpuid = xPortGetCoreID();
const uint32_t other_cpuid = (cpuid == 0) ? 1 : 0;
@@ -184,7 +184,7 @@ void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu()
spi_flash_op_unlock();
}
void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu_no_os()
void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu_no_os(void)
{
const uint32_t cpuid = xPortGetCoreID();
const uint32_t other_cpuid = (cpuid == 0) ? 1 : 0;
@@ -197,7 +197,7 @@ void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu_no_os()
spi_flash_disable_cache(cpuid, &s_flash_op_cache_state[cpuid]);
}
void IRAM_ATTR spi_flash_enable_interrupts_caches_no_os()
void IRAM_ATTR spi_flash_enable_interrupts_caches_no_os(void)
{
const uint32_t cpuid = xPortGetCoreID();
@@ -209,36 +209,36 @@ void IRAM_ATTR spi_flash_enable_interrupts_caches_no_os()
#else // CONFIG_FREERTOS_UNICORE
void spi_flash_init_lock()
void spi_flash_init_lock(void)
{
}
void spi_flash_op_lock()
void spi_flash_op_lock(void)
{
vTaskSuspendAll();
}
void spi_flash_op_unlock()
void spi_flash_op_unlock(void)
{
xTaskResumeAll();
}
void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu()
void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu(void)
{
spi_flash_op_lock();
esp_intr_noniram_disable();
spi_flash_disable_cache(0, &s_flash_op_cache_state[0]);
}
void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu()
void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu(void)
{
spi_flash_restore_cache(0, s_flash_op_cache_state[0]);
esp_intr_noniram_enable();
spi_flash_op_unlock();
}
void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu_no_os()
void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu_no_os(void)
{
// Kill interrupts that aren't located in IRAM
esp_intr_noniram_disable();
@@ -246,7 +246,7 @@ void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu_no_os()
spi_flash_disable_cache(0, &s_flash_op_cache_state[0]);
}
void IRAM_ATTR spi_flash_enable_interrupts_caches_no_os()
void IRAM_ATTR spi_flash_enable_interrupts_caches_no_os(void)
{
// Re-enable cache on this CPU
spi_flash_restore_cache(0, s_flash_op_cache_state[0]);
@@ -322,7 +322,7 @@ static void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_sta
}
IRAM_ATTR bool spi_flash_cache_enabled()
IRAM_ATTR bool spi_flash_cache_enabled(void)
{
#if CONFIG_IDF_TARGET_ESP32
bool result = (DPORT_REG_GET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE) != 0);