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Merge branch 'feature/support_i2s_on_esp32c6' into 'master'

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i2s: support i2s on esp32c6

See merge request espressif/esp-idf!19989
This commit is contained in:
Kevin (Lao Kaiyao)
2022-09-16 12:31:24 +08:00
parent 4f1a9e436e bae4944b90
commit 04b4bc6cb5
33 changed files with 1358 additions and 84 deletions
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4
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
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@@ -431,6 +431,10 @@ config SOC_I2S_HW_VERSION_2
bool
default y
config SOC_I2S_SUPPORTS_XTAL
bool
default y
config SOC_I2S_SUPPORTS_PCM
bool
default y

3
components/soc/esp32s3/include/soc/clk_tree_defs.h
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@@ -252,7 +252,7 @@ typedef enum {
/**
* @brief Array initializer for all supported clock sources of I2S
*/
#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M}
#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
/**
* @brief I2S clock source enum
@@ -260,6 +260,7 @@ typedef enum {
typedef enum {
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */
I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
} soc_periph_i2s_clk_src_t;
/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////

4
components/soc/esp32s3/include/soc/i2s_struct.h
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@@ -142,7 +142,7 @@ typedef volatile struct i2s_dev_s {
uint32_t rx_clkm_div_num : 8; /*Integral I2S clock divider value*/
uint32_t reserved8 : 18; /* Reserved*/
uint32_t rx_clk_active : 1; /*I2S Rx module clock enable signal.*/
uint32_t rx_clk_sel : 2; /*Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/
uint32_t rx_clk_sel : 2; /*Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
uint32_t mclk_sel : 1; /* 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT. */
uint32_t reserved30 : 2; /* Reserved*/
};
@@ -153,7 +153,7 @@ typedef volatile struct i2s_dev_s {
uint32_t tx_clkm_div_num : 8; /*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. */
uint32_t reserved8 : 18; /* Reserved*/
uint32_t tx_clk_active : 1; /*I2S Tx module clock enable signal.*/
uint32_t tx_clk_sel : 2; /*Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/
uint32_t tx_clk_sel : 2; /*Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
uint32_t clk_en : 1; /*Set this bit to enable clk gate*/
uint32_t reserved30 : 2; /* Reserved*/
};

1
components/soc/esp32s3/include/soc/soc_caps.h
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@@ -182,6 +182,7 @@
/*-------------------------- I2S CAPS ----------------------------------------*/
#define SOC_I2S_NUM (2)
#define SOC_I2S_HW_VERSION_2 (1)
#define SOC_I2S_SUPPORTS_XTAL (1)
#define SOC_I2S_SUPPORTS_PCM (1)
#define SOC_I2S_SUPPORTS_PDM (1)
#define SOC_I2S_SUPPORTS_PDM_TX (1)