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feat(sdmmc): supported UHS-I SDR50 (100Mhz) and DDR50 mode

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This commit is contained in:
Armando
2024-11-06 12:09:25 +08:00
parent 31dc34a909
commit 04cd469e4a
26 changed files with 650 additions and 131 deletions
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8
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
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@@ -1359,6 +1359,10 @@ config SOC_SDMMC_PSRAM_DMA_CAPABLE
bool
default y
config SOC_SDMMC_UHS_I_SUPPORTED
bool
default y
config SOC_SHA_DMA_MAX_BUFFER_SIZE
int
default 3968
@@ -1947,6 +1951,10 @@ config SOC_CLK_MPLL_SUPPORTED
bool
default y
config SOC_CLK_SDIO_PLL_SUPPORTED
bool
default y
config SOC_CLK_XTAL32K_SUPPORTED
bool
default y

5
components/soc/esp32p4/include/soc/clk_tree_defs.h
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@@ -151,6 +151,7 @@ typedef enum {
SOC_MOD_CLK_CPLL, /*!< CPLL is from 40MHz XTAL oscillator frequency multipliers */
SOC_MOD_CLK_SPLL, /*!< SPLL is from 40MHz XTAL oscillator frequency multipliers, it has a "fixed" frequency of 480MHz */
SOC_MOD_CLK_MPLL, /*!< MPLL is from 40MHz XTAL oscillator frequency multipliers */
SOC_MOD_CLK_SDIO_PLL, /*!< SDIO PLL is from 40MHz XTAL oscillator frequency multipliers, it has a "fixed" frequency of 200MHz */
SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */
@@ -706,7 +707,7 @@ typedef enum {
/**
* @brief Array initializer for all supported clock sources of SDMMC
*/
#define SOC_SDMMC_CLKS {SOC_MOD_CLK_PLL_F160M}
#define SOC_SDMMC_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_SDIO_PLL}
/**
* @brief Type of SDMMC clock source
@@ -714,7 +715,7 @@ typedef enum {
typedef enum {
SDMMC_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_160M as the default choice */
SDMMC_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_160M as the source clock */
// SOC_MOD_CLK_SDIO_PLL TODO:IDF-8886
SDMMC_CLK_SRC_SDIO_200M = SOC_MOD_CLK_SDIO_PLL,
} soc_periph_sdmmc_clk_src_t;
//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////

2
components/soc/esp32p4/include/soc/soc_caps.h
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@@ -499,6 +499,7 @@
#define SOC_SDMMC_DELAY_PHASE_NUM 4
#define SOC_SDMMC_IO_POWER_EXTERNAL 1 ///< SDMMC IO power controlled by external power supply
#define SOC_SDMMC_PSRAM_DMA_CAPABLE 1 ///< SDMMC peripheral can do DMA transfer to/from PSRAM
#define SOC_SDMMC_UHS_I_SUPPORTED 1
// TODO: IDF-5353 (Copy from esp32c3, need check)
/*--------------------------- SHA CAPS ---------------------------------------*/
@@ -732,6 +733,7 @@
#define SOC_CLK_APLL_SUPPORTED (1) /*!< Support Audio PLL */
#define SOC_CLK_MPLL_SUPPORTED (1) /*!< Support MSPI PLL */
#define SOC_CLK_SDIO_PLL_SUPPORTED (1) /*!< Support SDIO PLL */
#define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */
#define SOC_CLK_RC32K_SUPPORTED (1) /*!< Support an internal 32kHz RC oscillator */

2
components/soc/esp32p4/register/soc/sdmmc_struct.h
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@@ -914,7 +914,7 @@ typedef union {
typedef union {
struct {
/** volt: R/W; bitpos: [1:0]; default: 0;
* Voltage mode selection, 1 bit for each card.
* Voltage mode selection, 1 bit for each card. On the ESP32-P4, this bit doesn't do anything, I/O voltage is controlled using LDO API instead.
* 0: 3.3V mode.
* 1: 1.8V mode.
*/