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Merge branch 'feature/esp32s2beta_merge' into 'master'

Browse Source 
esp32s2beta: Merge support to master

Closes IDF-513, IDF-756, IDF-758, IDF-999, IDF-753, IDF-749, IDF-754, IDF-840, and IDF-755

See merge request espressif/esp-idf!6100
This commit is contained in:
Angus Gratton
2019-10-29 13:02:01 +08:00
parent d2e62a1602 36cd75d7ed
commit 055cc251b7
800 changed files with 95480 additions and 3273 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
components/esp32/CMakeLists.txt
View File

@@ -1,4 +1,10 @@
idf_build_get_property(target IDF_TARGET)
if(NOT "${target}" STREQUAL "esp32")
return()
endif()
idf_build_get_property(sdkconfig_header SDKCONFIG_HEADER)
if(BOOTLOADER_BUILD)
# For bootloader, all we need from esp32 is headers
idf_component_register(INCLUDE_DIRS include)

121
components/esp32/Kconfig
View File

@@ -1,4 +1,8 @@
menu "ESP32-specific"
# TODO: this component simply shouldn't be included
# in the build at the CMake level, but this is currently
# not working so we just hide all items here
visible if IDF_TARGET_ESP32
choice ESP32_REV_MIN
prompt "Minimum Supported ESP32 Revision"
@@ -48,9 +52,12 @@ menu "ESP32-specific"
default 160 if ESP32_DEFAULT_CPU_FREQ_160
default 240 if ESP32_DEFAULT_CPU_FREQ_240
# Note: to support SPIRAM across multiple chips, check CONFIG_SPIRAM
# instead
config ESP32_SPIRAM_SUPPORT
bool "Support for external, SPI-connected RAM"
default "n"
select SPIRAM
help
This enables support for an external SPI RAM chip, connected in parallel with the
main SPI flash chip.
@@ -58,41 +65,6 @@ menu "ESP32-specific"
menu "SPI RAM config"
depends on ESP32_SPIRAM_SUPPORT
config SPIRAM_BOOT_INIT
bool "Initialize SPI RAM when booting the ESP32"
default "y"
help
If this is enabled, the SPI RAM will be enabled during initial boot. Unless you
have specific requirements, you'll want to leave this enabled so memory allocated
during boot-up can also be placed in SPI RAM.
config SPIRAM_IGNORE_NOTFOUND
bool "Ignore PSRAM when not found"
default "n"
depends on SPIRAM_BOOT_INIT && !SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
help
Normally, if psram initialization is enabled during compile time but not found at runtime, it
is seen as an error making the ESP32 panic. If this is enabled, the ESP32 will keep on
running but will not add the (non-existing) RAM to any allocator.
choice SPIRAM_USE
prompt "SPI RAM access method"
default SPIRAM_USE_MALLOC
help
The SPI RAM can be accessed in multiple methods: by just having it available as an unmanaged
memory region in the ESP32 memory map, by integrating it in the ESP32s heap as 'special' memory
needing heap_caps_malloc to allocate, or by fully integrating it making malloc() also able to
return SPI RAM pointers.
config SPIRAM_USE_MEMMAP
bool "Integrate RAM into ESP32 memory map"
config SPIRAM_USE_CAPS_ALLOC
bool "Make RAM allocatable using heap_caps_malloc(..., MALLOC_CAP_SPIRAM)"
config SPIRAM_USE_MALLOC
bool "Make RAM allocatable using malloc() as well"
select FREERTOS_SUPPORT_STATIC_ALLOCATION
endchoice
choice SPIRAM_TYPE
prompt "Type of SPI RAM chip in use"
default SPIRAM_TYPE_AUTO
@@ -139,13 +111,8 @@ menu "ESP32-specific"
bool "80MHz clock speed"
endchoice
config SPIRAM_MEMTEST
bool "Run memory test on SPI RAM initialization"
default "y"
depends on SPIRAM_BOOT_INIT
help
Runs a rudimentary memory test on initialization. Aborts when memory test fails. Disable this for
slightly faster startop.
# insert non-chip-specific items here
source "$IDF_PATH/components/esp_common/Kconfig.spiram.common"
config SPIRAM_CACHE_WORKAROUND
bool "Enable workaround for bug in SPI RAM cache for Rev1 ESP32s"
@@ -187,47 +154,6 @@ menu "ESP32-specific"
any himem calls, the reservation is not done and the original amount of memory will be available
to malloc/esp_heap_alloc_caps.
config SPIRAM_MALLOC_ALWAYSINTERNAL
int "Maximum malloc() size, in bytes, to always put in internal memory"
depends on SPIRAM_USE_MALLOC
default 16384
range 0 131072
help
If malloc() is capable of also allocating SPI-connected ram, its allocation strategy will prefer to
allocate chunks less than this size in internal memory, while allocations larger than this will be
done from external RAM. If allocation from the preferred region fails, an attempt is made to allocate
from the non-preferred region instead, so malloc() will not suddenly fail when either internal or
external memory is full.
config SPIRAM_TRY_ALLOCATE_WIFI_LWIP
bool "Try to allocate memories of WiFi and LWIP in SPIRAM firstly. If failed, allocate internal memory"
depends on SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC
default "n"
help
Try to allocate memories of WiFi and LWIP in SPIRAM firstly. If failed, try to allocate internal
memory then.
config SPIRAM_MALLOC_RESERVE_INTERNAL
int "Reserve this amount of bytes for data that specifically needs to be in DMA or internal memory"
depends on SPIRAM_USE_MALLOC
default 32768
range 0 262144
help
Because the external/internal RAM allocation strategy is not always perfect, it sometimes may happen
that the internal memory is entirely filled up. This causes allocations that are specifically done in
internal memory, for example the stack for new tasks or memory to service DMA or have memory that's
also available when SPI cache is down, to fail. This option reserves a pool specifically for requests
like that; the memory in this pool is not given out when a normal malloc() is called.
Set this to 0 to disable this feature.
Note that because FreeRTOS stacks are forced to internal memory, they will also use this memory pool;
be sure to keep this in mind when adjusting this value.
Note also that the DMA reserved pool may not be one single contiguous memory region, depending on the
configured size and the static memory usage of the app.
config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
bool "Allow external memory as an argument to xTaskCreateStatic"
default n
@@ -240,15 +166,6 @@ menu "ESP32-specific"
and does not call on ROM code in any way (no direct calls, but also no Bluetooth/WiFi), you can try to
disable this and use xTaskCreateStatic to create the tasks stack in external memory.
config SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
bool "Allow .bss segment placed in external memory"
default n
depends on ESP32_SPIRAM_SUPPORT
help
If enabled the option,and add EXT_RAM_ATTR defined your variable,then your variable will be placed in
PSRAM instead of internal memory, and placed most of variables of lwip,net802.11,pp,bluedroid library
to external memory defaultly.
choice SPIRAM_OCCUPY_SPI_HOST
prompt "SPI host to use for 32MBit PSRAM"
default SPIRAM_OCCUPY_VSPI_HOST
@@ -477,8 +394,6 @@ menu "ESP32-specific"
e.g. GCOV data dump.
config ESP32_BROWNOUT_DET
#The brownout detector code is disabled (by making it depend on a nonexisting symbol) because the current
#revision of ESP32 silicon has a bug in the brown-out detector, rendering it unusable for resetting the CPU.
bool "Hardware brownout detect & reset"
default y
help
@@ -783,23 +698,13 @@ menu "ESP32-specific"
To prevent interrupting DPORT workarounds,
need to disable interrupt with a maximum used level in the system.
config ESP32_PANIC_HANDLER_IRAM
bool "Place panic handler code in IRAM"
default n
help
If this option is disabled (default), the panic handler code is placed in flash not IRAM.
This means that if ESP-IDF crashes while flash cache is disabled, the panic handler will
automatically re-enable flash cache before running GDB Stub or Core Dump. This adds some minor
risk, if the flash cache status is also corrupted during the crash.
If this option is enabled, the panic handler code is placed in IRAM. This allows the panic
handler to run without needing to re-enable cache first. This may be necessary to debug some
complex issues with crashes while flash cache is disabled (for example, when writing to
SPI flash.)
endmenu # ESP32-Specific
menu "Power Management"
# TODO: this component simply shouldn't be included
# in the build at the CMake level, but this is currently
# not working so we just hide all items here
visible if IDF_TARGET_ESP32
config PM_ENABLE
bool "Support for power management"

123
components/esp32/include/esp_attr.h
View File

@@ -1,123 +0,0 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_ATTR_H__
#define __ESP_ATTR_H__
#include "sdkconfig.h"
#define ROMFN_ATTR
//Normally, the linker script will put all code and rodata in flash,
//and all variables in shared RAM. These macros can be used to redirect
//particular functions/variables to other memory regions.
// Forces code into IRAM instead of flash
#define IRAM_ATTR _SECTION_ATTR_IMPL(".iram1", __COUNTER__)
// Forces data into DRAM instead of flash
#define DRAM_ATTR _SECTION_ATTR_IMPL(".dram1", __COUNTER__)
// Forces data to be 4 bytes aligned
#define WORD_ALIGNED_ATTR __attribute__((aligned(4)))
// Forces data to be placed to DMA-capable places
#define DMA_ATTR WORD_ALIGNED_ATTR DRAM_ATTR
// Forces a function to be inlined
#define FORCE_INLINE_ATTR static inline __attribute__((always_inline))
// Forces a string into DRAM instead of flash
// Use as ets_printf(DRAM_STR("Hello world!\n"));
#define DRAM_STR(str) (__extension__({static const DRAM_ATTR char __c[] = (str); (const char *)&__c;}))
// Forces code into RTC fast memory. See "docs/deep-sleep-stub.rst"
#define RTC_IRAM_ATTR _SECTION_ATTR_IMPL(".rtc.text", __COUNTER__)
#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
// Forces bss variable into external memory. "
#define EXT_RAM_ATTR _SECTION_ATTR_IMPL(".ext_ram.bss", __COUNTER__)
#else
#define EXT_RAM_ATTR
#endif
// Forces data into RTC slow memory. See "docs/deep-sleep-stub.rst"
// Any variable marked with this attribute will keep its value
// during a deep sleep / wake cycle.
#define RTC_DATA_ATTR _SECTION_ATTR_IMPL(".rtc.data", __COUNTER__)
// Forces read-only data into RTC memory. See "docs/deep-sleep-stub.rst"
#define RTC_RODATA_ATTR _SECTION_ATTR_IMPL(".rtc.rodata", __COUNTER__)
// Allows to place data into RTC_SLOW memory.
#define RTC_SLOW_ATTR _SECTION_ATTR_IMPL(".rtc.force_slow", __COUNTER__)
// Allows to place data into RTC_FAST memory.
#define RTC_FAST_ATTR _SECTION_ATTR_IMPL(".rtc.force_fast", __COUNTER__)
// Forces data into noinit section to avoid initialization after restart.
#define __NOINIT_ATTR _SECTION_ATTR_IMPL(".noinit", __COUNTER__)
// Forces data into RTC slow memory of .noinit section.
// Any variable marked with this attribute will keep its value
// after restart or during a deep sleep / wake cycle.
#define RTC_NOINIT_ATTR _SECTION_ATTR_IMPL(".rtc_noinit", __COUNTER__)
// Forces to not inline function
#define NOINLINE_ATTR __attribute__((noinline))
// This allows using enum as flags in C++
// Format: FLAG_ATTR(flag_enum_t)
#ifdef __cplusplus
#define FLAG_ATTR_IMPL(TYPE, INT_TYPE) \
constexpr TYPE operator~ (TYPE a) { return (TYPE)~(INT_TYPE)a; } \
constexpr TYPE operator| (TYPE a, TYPE b) { return (TYPE)((INT_TYPE)a | (INT_TYPE)b); } \
constexpr TYPE operator& (TYPE a, TYPE b) { return (TYPE)((INT_TYPE)a & (INT_TYPE)b); } \
constexpr TYPE operator^ (TYPE a, TYPE b) { return (TYPE)((INT_TYPE)a ^ (INT_TYPE)b); } \
constexpr TYPE operator>> (TYPE a, int b) { return (TYPE)((INT_TYPE)a >> b); } \
constexpr TYPE operator<< (TYPE a, int b) { return (TYPE)((INT_TYPE)a << b); } \
TYPE& operator|=(TYPE& a, TYPE b) { a = a | b; return a; } \
TYPE& operator&=(TYPE& a, TYPE b) { a = a & b; return a; } \
TYPE& operator^=(TYPE& a, TYPE b) { a = a ^ b; return a; } \
TYPE& operator>>=(TYPE& a, int b) { a >>= b; return a; } \
TYPE& operator<<=(TYPE& a, int b) { a <<= b; return a; }
#define FLAG_ATTR_U32(TYPE) FLAG_ATTR_IMPL(TYPE, uint32_t)
#define FLAG_ATTR FLAG_ATTR_U32
#else
#define FLAG_ATTR(TYPE)
#endif
// Implementation for a unique custom section
//
// This prevents gcc producing "x causes a section type conflict with y"
// errors if two variables in the same source file have different linkage (maybe const & non-const) but are placed in the same custom section
//
// Using unique sections also means --gc-sections can remove unused
// data with a custom section type set
#define _SECTION_ATTR_IMPL(SECTION, COUNTER) __attribute__((section(SECTION "." _COUNTER_STRINGIFY(COUNTER))))
#define _COUNTER_STRINGIFY(COUNTER) #COUNTER
/* Use IDF_DEPRECATED attribute to mark anything deprecated from use in
ESP-IDF's own source code, but not deprecated for external users.
*/
#ifdef IDF_CI_BUILD
#define IDF_DEPRECATED(REASON) __attribute__((deprecated(REASON)))
#else
#define IDF_DEPRECATED(REASON)
#endif
#endif /* __ESP_ATTR_H__ */

24
components/esp32/intr_alloc.c
View File

@@ -30,10 +30,13 @@
#include "esp_attr.h"
#include <limits.h>
#include <assert.h>
#include "soc/soc.h"
#if !CONFIG_FREERTOS_UNICORE
#include "esp_ipc.h"
#endif
static const char* TAG = "intr_alloc";
#define ETS_INTERNAL_TIMER0_INTR_NO 6
@@ -342,7 +345,7 @@ static bool is_vect_desc_usable(vector_desc_t *vd, int flags, int cpu, int force
ALCHLOG("....Unusable: reserved at runtime.");
return false;
}
//Ints can't be both shared and non-shared.
assert(!((vd->flags&VECDESC_FL_SHARED)&&(vd->flags&VECDESC_FL_NONSHARED)));
//check if interrupt already is in use by a non-shared interrupt
@@ -370,7 +373,7 @@ static bool is_vect_desc_usable(vector_desc_t *vd, int flags, int cpu, int force
ALCHLOG("....Unusable: already allocated");
return false;
}
return true;
}
@@ -387,7 +390,7 @@ static int get_available_int(int flags, int cpu, int force, int source)
vector_desc_t empty_vect_desc;
memset(&empty_vect_desc, 0, sizeof(vector_desc_t));
//Level defaults to any low/med interrupt
if (!(flags&ESP_INTR_FLAG_LEVELMASK)) flags|=ESP_INTR_FLAG_LOWMED;
@@ -412,13 +415,13 @@ static int get_available_int(int flags, int cpu, int force, int source)
if (vd == NULL ) {
//if existing vd not found, just check the default state for the intr.
empty_vect_desc.intno = force;
vd = &empty_vect_desc;
vd = &empty_vect_desc;
}
if ( is_vect_desc_usable(vd, flags, cpu, force) ) {
best = vd->intno;
} else {
ALCHLOG("get_avalible_int: forced vd invalid.");
}
}
return best;
}
@@ -435,12 +438,12 @@ static int get_available_int(int flags, int cpu, int force, int source)
ALCHLOG("Int %d reserved %d level %d %s hasIsr %d",
x, int_desc[x].cpuflags[cpu]==INTDESC_RESVD, int_desc[x].level,
int_desc[x].type==INTTP_LEVEL?"LEVEL":"EDGE", int_has_handler(x, cpu));
if ( !is_vect_desc_usable(vd, flags, cpu, force) ) continue;
if (flags&ESP_INTR_FLAG_SHARED) {
//We're allocating a shared int.
//See if int already is used as a shared interrupt.
if (vd->flags&VECDESC_FL_SHARED) {
//We can use this already-marked-as-shared interrupt. Count the already attached isrs in order to see
@@ -550,9 +553,12 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
//Statusreg should have a mask
if (intrstatusreg && !intrstatusmask) return ESP_ERR_INVALID_ARG;
//If the ISR is marked to be IRAM-resident, the handler must not be in the cached region
//ToDo: if we are to allow placing interrupt handlers into the 0x400c0000—0x400c2000 region,
//we need to make sure the interrupt is connected to the CPU0.
//CPU1 does not have access to the RTC fast memory through this region.
if ((flags&ESP_INTR_FLAG_IRAM) &&
(ptrdiff_t) handler >= 0x400C0000 &&
(ptrdiff_t) handler < 0x50000000 ) {
(ptrdiff_t) handler >= SOC_RTC_IRAM_HIGH &&
(ptrdiff_t) handler < SOC_RTC_DATA_LOW ) {
return ESP_ERR_INVALID_ARG;
}

14
components/esp32/ld/esp32.ld
View File

@@ -52,12 +52,14 @@ MEMORY
#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/* Even though the segment name is iram, it is actually mapped to flash
*/
iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000-0x18
iram0_2_seg (RX) : org = 0x400D0020, len = 0x330000-0x20
/*
(0x18 offset above is a convenience for the app binary image generation. Flash cache has 64KB pages. The .bin file
which is flashed to the chip has a 0x18 byte file header. Setting this offset makes it simple to meet the flash
cache MMU's constraint that (paddr % 64KB == vaddr % 64KB).)
(0x20 offset above is a convenience for the app binary image generation.
Flash cache has 64KB pages. The .bin file which is flashed to the chip
has a 0x18 byte file header, and each segment has a 0x08 byte segment
header. Setting this offset makes it simple to meet the flash cache MMU's
constraint that (paddr % 64KB == vaddr % 64KB).)
*/
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
@@ -76,9 +78,9 @@ MEMORY
#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/* Flash mapped constant data */
drom0_0_seg (R) : org = 0x3F400018, len = 0x400000-0x18
drom0_0_seg (R) : org = 0x3F400020, len = 0x400000-0x20
/* (See iram0_2_seg for meaning of 0x18 offset in the above.) */
/* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/* RTC fast memory (executable). Persists over deep sleep.

2
components/esp32/panic.c
View File

@@ -608,7 +608,7 @@ static __attribute__((noreturn)) void commonErrorHandler(XtExcFrame *frame)
reconfigureAllWdts();
#endif
#if !CONFIG_ESP32_PANIC_HANDLER_IRAM
#if !CONFIG_ESP_PANIC_HANDLER_IRAM
// Re-enable CPU cache for current CPU if it was disabled
if (!spi_flash_cache_enabled()) {
spi_flash_enable_cache(core_id);

4
components/esp32/sleep_modes.c
View File

@@ -302,7 +302,7 @@ esp_err_t esp_light_sleep_start(void)
const uint32_t flash_enable_time_us = VDD_SDIO_POWERUP_TO_FLASH_READ_US
+ CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY;
#ifndef CONFIG_ESP32_SPIRAM_SUPPORT
#ifndef CONFIG_SPIRAM
const uint32_t vddsdio_pd_sleep_duration = MAX(FLASH_PD_MIN_SLEEP_TIME_US,
flash_enable_time_us + LIGHT_SLEEP_TIME_OVERHEAD_US + LIGHT_SLEEP_MIN_TIME_US);
@@ -310,7 +310,7 @@ esp_err_t esp_light_sleep_start(void)
pd_flags |= RTC_SLEEP_PD_VDDSDIO;
s_config.sleep_time_adjustment += flash_enable_time_us;
}
#endif //CONFIG_ESP32_SPIRAM_SUPPORT
#endif //CONFIG_SPIRAM
rtc_vddsdio_config_t vddsdio_config = rtc_vddsdio_get_config();

2
components/esp32/spiram.c
View File

@@ -46,7 +46,7 @@ we add more types of external RAM memory, this can be made into a more intellige
#endif
#endif
#if CONFIG_ESP32_SPIRAM_SUPPORT
#if CONFIG_SPIRAM
static const char* TAG = "spiram";

4
components/esp32/spiram_psram.c
View File

@@ -37,7 +37,7 @@
#include "driver/periph_ctrl.h"
#include "bootloader_common.h"
#if CONFIG_ESP32_SPIRAM_SUPPORT
#if CONFIG_SPIRAM
#include "soc/rtc.h"
//Commands for PSRAM chip
@@ -847,4 +847,4 @@ static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psra
CLEAR_PERI_REG_MASK(SPI_PIN_REG(0), SPI_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)
}
#endif // CONFIG_ESP32_SPIRAM_SUPPORT
#endif // CONFIG_SPIRAM

25
components/esp32/test/CMakeLists.txt
View File

@@ -1,16 +1,19 @@
idf_component_register(SRC_DIRS "."
INCLUDE_DIRS "." "${CMAKE_CURRENT_BINARY_DIR}"
REQUIRES unity test_utils nvs_flash ulp esp_common)
if(IDF_TARGET STREQUAL "esp32")
idf_component_register(SRC_DIRS .
INCLUDE_DIRS . ${CMAKE_CURRENT_BINARY_DIR}
REQUIRES unity test_utils nvs_flash ulp esp_common
)
add_custom_command(OUTPUT "${CMAKE_CURRENT_BINARY_DIR}/test_tjpgd_logo.h"
COMMAND xxd -i "logo.jpg" "${CMAKE_CURRENT_BINARY_DIR}/test_tjpgd_logo.h"
WORKING_DIRECTORY ${COMPONENT_DIR}
DEPENDS "${CMAKE_CURRENT_LIST_DIR}/logo.jpg")
add_custom_command(OUTPUT "${CMAKE_CURRENT_BINARY_DIR}/test_tjpgd_logo.h"
COMMAND xxd -i "logo.jpg" "${CMAKE_CURRENT_BINARY_DIR}/test_tjpgd_logo.h"
WORKING_DIRECTORY ${COMPONENT_DIR}
DEPENDS "${CMAKE_CURRENT_LIST_DIR}/logo.jpg")
add_custom_target(esp32_test_logo DEPENDS "${CMAKE_CURRENT_BINARY_DIR}/test_tjpgd_logo.h")
add_custom_target(esp32_test_logo DEPENDS "${CMAKE_CURRENT_BINARY_DIR}/test_tjpgd_logo.h")
add_dependencies(${COMPONENT_LIB} esp32_test_logo)
add_dependencies(${COMPONENT_LIB} esp32_test_logo)
idf_build_set_property(COMPILE_DEFINITIONS "-DESP_TIMER_DYNAMIC_OVERFLOW_VAL" APPEND)
idf_build_set_property(COMPILE_DEFINITIONS "-DESP_TIMER_DYNAMIC_OVERFLOW_VAL" APPEND)
target_link_libraries(${COMPONENT_LIB} INTERFACE "-u ld_include_test_dport_xt_highint5")
endif()
target_link_libraries(${COMPONENT_LIB} INTERFACE "-u ld_include_test_dport_xt_highint5")

6
components/esp32/test/test_4mpsram.c
View File

@@ -6,7 +6,7 @@
static const char TAG[] = "test_psram";
#ifdef CONFIG_ESP32_SPIRAM_SUPPORT
#ifdef CONFIG_SPIRAM
static void test_psram_content(void)
{
const int test_size = 2048;
@@ -40,7 +40,7 @@ static void test_psram_content(void)
TEST_CASE("can use spi when not being used by psram", "[psram_4m]")
{
spi_host_device_t host;
#if !CONFIG_ESP32_SPIRAM_SUPPORT || !CONFIG_SPIRAM_SPEED_80M || CONFIG_SPIRAM_BANKSWITCH_ENABLE
#if !CONFIG_SPIRAM || !CONFIG_SPIRAM_SPEED_80M || CONFIG_SPIRAM_BANKSWITCH_ENABLE
//currently all 8M psram don't need more SPI peripherals
host = -1;
#elif CONFIG_SPIRAM_OCCUPY_HSPI_HOST
@@ -66,7 +66,7 @@ TEST_CASE("can use spi when not being used by psram", "[psram_4m]")
TEST_ASSERT(claim_vspi==true);
}
#ifdef CONFIG_ESP32_SPIRAM_SUPPORT
#ifdef CONFIG_SPIRAM
test_psram_content();
#endif
}

1
components/esp32/test/test_aes_sha_rsa.c
View File

@@ -2,7 +2,6 @@
#include <stdlib.h>
#include <string.h>
#include "esp_types.h"
#include "esp32/clk.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"

5
components/esp32/test/test_intr_alloc.c
View File

@@ -4,8 +4,11 @@
#include <esp_types.h>
#include <stdio.h>
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#include "esp32s2beta/rom/ets_sys.h"
#endif
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"

25
components/esp32/test/test_sleep.c
View File

@@ -18,6 +18,7 @@
#include "test_utils.h"
#include "sdkconfig.h"
#define ESP_EXT0_WAKEUP_LEVEL_LOW 0
#define ESP_EXT0_WAKEUP_LEVEL_HIGH 1
@@ -330,7 +331,7 @@ TEST_CASE("wake up using ext1 when RTC_PERIPH is on (13 low)", "[deepsleep][igno
static float get_time_ms(void)
{
gettimeofday(&tv_stop, NULL);
float dt = (tv_stop.tv_sec - tv_start.tv_sec) * 1e3f +
(tv_stop.tv_usec - tv_start.tv_usec) * 1e-3f;
return fabs(dt);
@@ -343,20 +344,20 @@ static uint32_t get_cause(void)
return wakeup_cause;
}
// This test case verifies deactivation of trigger for wake up sources
// This test case verifies deactivation of trigger for wake up sources
TEST_CASE("disable source trigger behavior", "[deepsleep]")
{
float dt = 0;
printf("Setup timer and ext0 to wake up immediately from GPIO_13 \n");
// Setup ext0 configuration to wake up almost immediately
// The wakeup time is proportional to input capacitance * pullup resistance
ESP_ERROR_CHECK(rtc_gpio_init(GPIO_NUM_13));
ESP_ERROR_CHECK(gpio_pullup_en(GPIO_NUM_13));
ESP_ERROR_CHECK(gpio_pulldown_dis(GPIO_NUM_13));
ESP_ERROR_CHECK(esp_sleep_enable_ext0_wakeup(GPIO_NUM_13, ESP_EXT0_WAKEUP_LEVEL_HIGH));
// Setup timer to wakeup with timeout
esp_sleep_enable_timer_wakeup(2000000);
@@ -367,22 +368,22 @@ TEST_CASE("disable source trigger behavior", "[deepsleep]")
dt = get_time_ms();
printf("Ext0 sleep time = %d \n", (int) dt);
// Check wakeup from Ext0 using time measurement because wakeup cause is
// Check wakeup from Ext0 using time measurement because wakeup cause is
// not available in light sleep mode
TEST_ASSERT_INT32_WITHIN(100, 100, (int) dt);
TEST_ASSERT((get_cause() & RTC_EXT0_TRIG_EN) != 0);
// Disable Ext0 source. Timer source should be triggered
ESP_ERROR_CHECK(esp_sleep_disable_wakeup_source(ESP_SLEEP_WAKEUP_EXT0));
printf("Disable ext0 trigger and leave timer active.\n");
gettimeofday(&tv_start, NULL);
esp_light_sleep_start();
dt = get_time_ms();
printf("Timer sleep time = %d \n", (int) dt);
TEST_ASSERT_INT32_WITHIN(500, 2000, (int) dt);
// Additionally check wakeup cause
@@ -407,8 +408,8 @@ TEST_CASE("disable source trigger behavior", "[deepsleep]")
TEST_ASSERT_INT32_WITHIN(100, 100, (int) dt);
TEST_ASSERT((get_cause() & RTC_EXT0_TRIG_EN) != 0);
// Check error message when source is already disabled
// Check error message when source is already disabled
esp_err_t err_code = esp_sleep_disable_wakeup_source(ESP_SLEEP_WAKEUP_TIMER);
TEST_ASSERT(err_code == ESP_ERR_INVALID_STATE);
}
@@ -429,7 +430,7 @@ static void trigger_deepsleep(void)
// Save start time. Deep sleep.
gettimeofday(&start, NULL);
esp_sleep_enable_timer_wakeup(1000);
// In function esp_deep_sleep_start() uses function esp_sync_counters_rtc_and_frc()
// In function esp_deep_sleep_start() uses function esp_sync_counters_rtc_and_frc()
// to prevent a negative time after wake up.
esp_deep_sleep_start();
}

15
components/esp32/test/test_spiram_cache_flush.c
View File

@@ -20,8 +20,9 @@ This code tests the interaction between PSRAM and SPI flash routines.
#include "esp_spi_flash.h"
#include "esp_partition.h"
#include "test_utils.h"
#include "soc/soc.h"
#if CONFIG_ESP32_SPIRAM_SUPPORT
#if CONFIG_SPIRAM
#if CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC
#define USE_CAPS_ALLOC 1
@@ -61,8 +62,8 @@ TEST_CASE("Spiram cache flush on mmap", "[spiram]")
mem[0]=heap_caps_malloc(TSTSZ, MALLOC_CAP_SPIRAM);
mem[1]=heap_caps_malloc(TSTSZ, MALLOC_CAP_SPIRAM);
#else
mem[0]=(void*)0x3f800000;
mem[1]=(void*)0x3f800000+TSTSZ;
mem[0]=(void*)SOC_EXTRAM_DATA_LOW;
mem[1]=(void*)SOC_EXTRAM_DATA_LOW+TSTSZ;
#endif
assert(mem[0]);
assert(mem[1]);
@@ -105,8 +106,8 @@ TEST_CASE("Spiram cache flush on write/read", "[spiram]")
mem[0]=heap_caps_malloc(TSTSZ, MALLOC_CAP_SPIRAM);
mem[1]=heap_caps_malloc(TSTSZ, MALLOC_CAP_SPIRAM);
#else
mem[0]=(void*)0x3f800000;
mem[1]=(void*)0x3f800000+TSTSZ;
mem[0]=(void*)SOC_EXTRAM_DATA_LOW;
mem[1]=(void*)SOC_EXTRAM_DATA_LOW+TSTSZ;
#endif
assert(mem[0]);
assert(mem[1]);
@@ -148,7 +149,7 @@ IRAM_ATTR TEST_CASE("Spiram memcmp weirdness at 80MHz", "[spiram]") {
#if USE_CAPS_ALLOC
char *mem2=heap_caps_malloc(0x10000, MALLOC_CAP_SPIRAM);
#else
char *mem2=(void*)0x3f800000;
char *mem2=(void*)SOC_EXTRAM_DATA_LOW;
#endif
#if !CONFIG_SPIRAM_SPEED_80M
@@ -179,4 +180,4 @@ IRAM_ATTR TEST_CASE("Spiram memcmp weirdness at 80MHz", "[spiram]") {
#endif
}
#endif // CONFIG_ESP32_SPIRAM_SUPPORT
#endif // CONFIG_SPIRAM