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uart: seperate sclk and baudrate setting

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Armando
2020-11-23 19:31:50 +08:00
parent fb8b905539
commit 05a4a8d864
9 changed files with 66 additions and 35 deletions
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5
components/hal/esp32s3/include/hal/uart_ll.h
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@@ -129,17 +129,14 @@ static inline uint32_t uart_ll_get_sclk_freq(uart_dev_t *hw)
* @brief Configure the baud-rate.
*
* @param hw Beginning address of the peripheral registers.
* @param source_clk The UART source clock. The source clock can be APB clock, RTC clock or XTAL clock.
* If the source clock is RTC/XTAL, the UART can still work when the APB changes.
* @param baud The baud rate to be set. When the source clock is APB, the max baud rate is `UART_LL_BITRATE_MAX`
*
* @return None
*/
static inline void uart_ll_set_baudrate(uart_dev_t *hw, uart_sclk_t source_clk, uint32_t baud)
static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud)
{
uint32_t sclk_freq, clk_div;
uart_ll_set_sclk(hw, source_clk);
sclk_freq = uart_ll_get_sclk_freq(hw);
clk_div = ((sclk_freq) << 4) / baud;
// The baud rate configuration register is divided into