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feat(esp_system): gate some clock by default to optmize esp32p4 active power

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This commit is contained in:
wuzhenghui
2024-08-20 13:32:02 +08:00
parent fba9b50456
commit 05e74480f5
66 changed files with 769 additions and 189 deletions
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33
components/hal/esp32/include/hal/uart_ll.h
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@@ -131,6 +131,26 @@ static inline void uart_ll_reset_register(uart_port_t uart_num)
// SYSTEM.perip_rst_enx are shared registers, so this function must be used in an atomic way
#define uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_reset_register(__VA_ARGS__)
/**
* @brief Enable the UART clock.
*
* @param hw Beginning address of the peripheral registers.
*/
FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw)
{
(void)hw;
}
/**
* @brief Disable the UART clock.
*
* @param hw Beginning address of the peripheral registers.
*/
FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
{
(void)hw;
}
/**
* @brief Set the UART source clock.
*
@@ -697,6 +717,19 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_t
hw->sleep_conf.active_threshold = wakeup_thrd - (UART_LL_MIN_WAKEUP_THRESH - 1);
}
/**
* @brief Enable/disable the UART pad clock in sleep_state
*
* @param hw Beginning address of the peripheral registers.
* @param enable enable or disable
*/
FORCE_INLINE_ATTR void _uart_ll_enable_pad_sleep_clock(uart_dev_t *hw, bool enable)
{
(void)hw; (void)enable;
}
#define uart_ll_enable_pad_sleep_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uart_ll_enable_pad_sleep_clock(__VA_ARGS__)
/**
* @brief Configure the UART work in normal mode.
*