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feat(esp_system): gate some clock by default to optmize esp32p4 active power

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This commit is contained in:
wuzhenghui
2024-08-20 13:32:02 +08:00
parent fba9b50456
commit 05e74480f5
66 changed files with 769 additions and 189 deletions
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1
components/hal/esp32p4/include/hal/adc_ll.h
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@@ -223,6 +223,7 @@ static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
HP_SYS_CLKRST.peri_clk_ctrl22.reg_adc_clk_src_sel = 1;
break;
case ADC_DIGI_CLK_SRC_PLL_F80M:
HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_80m_clk_en = 1;
HP_SYS_CLKRST.peri_clk_ctrl22.reg_adc_clk_src_sel = 2;
break;
default:

4
components/hal/esp32p4/include/hal/aes_ll.h
View File

@@ -31,14 +31,14 @@ typedef enum {
*
* @param enable true to enable the module, false to disable the module
*/
static inline void aes_ll_enable_bus_clock(bool enable)
static inline void _aes_ll_enable_bus_clock(bool enable)
{
HP_SYS_CLKRST.peri_clk_ctrl25.reg_crypto_aes_clk_en = enable;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define aes_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; aes_ll_enable_bus_clock(__VA_ARGS__)
#define aes_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _aes_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset the AES peripheral module

9
components/hal/esp32p4/include/hal/assist_debug_ll.h
View File

@@ -114,14 +114,15 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(uint32_t core_id)
return REG_READ(core_id ? ASSIST_DEBUG_CORE_1_SP_PC_REG : ASSIST_DEBUG_CORE_0_SP_PC_REG);
}
FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(bool enable)
FORCE_INLINE_ATTR void _assist_debug_ll_enable_bus_clock(bool enable)
{
HP_SYS_CLKRST.soc_clk_ctrl0.reg_busmon_cpu_clk_en = enable;
REG_SET_FIELD(ASSIST_DEBUG_CLOCK_GATE_REG, ASSIST_DEBUG_CLK_EN, enable);
}
#define assist_debug_ll_enable_bus_clock(...) \
(void)__DECLARE_RCC_ATOMIC_ENV; assist_debug_ll_enable_bus_clock(__VA_ARGS__)
(void)__DECLARE_RCC_ATOMIC_ENV; _assist_debug_ll_enable_bus_clock(__VA_ARGS__)
FORCE_INLINE_ATTR void assist_debug_ll_reset_register(void)
FORCE_INLINE_ATTR void _assist_debug_ll_reset_register(void)
{
/* esp32p4 has no assist_debug reset register: disable & clear interrupts manually. */
for (int i = 0; i < CONFIG_SOC_CPU_CORES_NUM; i++) {
@@ -134,7 +135,7 @@ FORCE_INLINE_ATTR void assist_debug_ll_reset_register(void)
}
}
#define assist_debug_ll_reset_register(...) \
(void)__DECLARE_RCC_ATOMIC_ENV; assist_debug_ll_reset_register(__VA_ARGS__)
(void)__DECLARE_RCC_ATOMIC_ENV; _assist_debug_ll_reset_register(__VA_ARGS__)
#ifdef __cplusplus
}

1
components/hal/esp32p4/include/hal/cam_ll.h
View File

@@ -96,6 +96,7 @@ static inline void cam_ll_select_clk_src(int group_id, cam_clock_source_t src)
HP_SYS_CLKRST.peri_clk_ctrl119.reg_cam_clk_src_sel = 0;
break;
case CAM_CLK_SRC_PLL160M:
HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_160m_clk_en = 1;
HP_SYS_CLKRST.peri_clk_ctrl119.reg_cam_clk_src_sel = 1;
break;
case CAM_CLK_SRC_APLL:

4
components/hal/esp32p4/include/hal/clk_tree_ll.h
View File

@@ -13,6 +13,7 @@
#include "soc/clk_tree_defs.h"
#include "soc/hp_sys_clkrst_reg.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "soc/lp_clkrst_reg.h"
#include "soc/lp_clkrst_struct.h"
#include "soc/pmu_reg.h"
#include "hal/regi2c_ctrl.h"
@@ -114,6 +115,7 @@ static inline __attribute__((always_inline)) void clk_ll_cpll_disable(void)
*/
static inline __attribute__((always_inline)) void clk_ll_apll_enable(void)
{
SET_PERI_REG_MASK(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_AUDIO_PLL_CLK_EN);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XPD_APLL | PMU_TIE_HIGH_XPD_APLL_I2C);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_GLOBAL_APLL_ICG);
}
@@ -123,6 +125,7 @@ static inline __attribute__((always_inline)) void clk_ll_apll_enable(void)
*/
static inline __attribute__((always_inline)) void clk_ll_apll_disable(void)
{
CLEAR_PERI_REG_MASK(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_AUDIO_PLL_CLK_EN);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_APLL_ICG) ;
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_APLL | PMU_TIE_LOW_XPD_APLL_I2C);
}
@@ -151,6 +154,7 @@ static inline __attribute__((always_inline)) void clk_ll_lp_pll_disable(void)
static inline __attribute__((always_inline)) void clk_ll_mpll_enable(void)
{
REG_SET_BIT(PMU_RF_PWC_REG, PMU_MSPI_PHY_XPD);
REG_SET_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_MPLL_500M_CLK_EN);
}
/**

4
components/hal/esp32p4/include/hal/ds_ll.h
View File

@@ -30,14 +30,14 @@ extern "C" {
*
* @param true to enable the module, false to disable the module
*/
static inline void ds_ll_enable_bus_clock(bool enable)
static inline void _ds_ll_enable_bus_clock(bool enable)
{
HP_SYS_CLKRST.peri_clk_ctrl25.reg_crypto_ds_clk_en = enable;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define ds_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; ds_ll_enable_bus_clock(__VA_ARGS__)
#define ds_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _ds_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset the DS peripheral module

4
components/hal/esp32p4/include/hal/ecc_ll.h
View File

@@ -30,14 +30,14 @@ typedef enum {
*
* @param true to enable the module, false to disable the module
*/
static inline void ecc_ll_enable_bus_clock(bool enable)
static inline void _ecc_ll_enable_bus_clock(bool enable)
{
HP_SYS_CLKRST.peri_clk_ctrl25.reg_crypto_ecc_clk_en = enable;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define ecc_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; ecc_ll_enable_bus_clock(__VA_ARGS__)
#define ecc_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _ecc_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset the ECC peripheral module

4
components/hal/esp32p4/include/hal/etm_ll.h
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@@ -26,7 +26,7 @@ extern "C" {
* @param group_id Group ID
* @param enable true to enable, false to disable
*/
static inline void etm_ll_enable_bus_clock(int group_id, bool enable)
static inline void _etm_ll_enable_bus_clock(int group_id, bool enable)
{
(void)group_id;
HP_SYS_CLKRST.soc_clk_ctrl3.reg_etm_apb_clk_en = enable;
@@ -35,7 +35,7 @@ static inline void etm_ll_enable_bus_clock(int group_id, bool enable)
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define etm_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; etm_ll_enable_bus_clock(__VA_ARGS__)
#define etm_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _etm_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset the ETM module

4
components/hal/esp32p4/include/hal/gdma_ll.h
View File

@@ -95,7 +95,7 @@ extern "C" {
/**
* @brief Enable the bus clock for the DMA module
*/
static inline void gdma_ll_enable_bus_clock(int group_id, bool enable)
static inline void _gdma_ll_enable_bus_clock(int group_id, bool enable)
{
if (group_id == 0) {
HP_SYS_CLKRST.soc_clk_ctrl1.reg_ahb_pdma_sys_clk_en = enable;
@@ -106,7 +106,7 @@ static inline void gdma_ll_enable_bus_clock(int group_id, bool enable)
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define gdma_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; gdma_ll_enable_bus_clock(__VA_ARGS__)
#define gdma_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _gdma_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset the DMA module

1
components/hal/esp32p4/include/hal/gpio_ll.h
View File

@@ -637,6 +637,7 @@ static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src)
HP_SYS_CLKRST.peri_clk_ctrl26.reg_iomux_clk_src_sel = 0;
break;
case SOC_MOD_CLK_PLL_F80M:
HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_80m_clk_en = 1;
HP_SYS_CLKRST.peri_clk_ctrl26.reg_iomux_clk_src_sel = 1;
break;
default:

4
components/hal/esp32p4/include/hal/hmac_ll.h
View File

@@ -37,14 +37,14 @@ extern "C" {
*
* @param true to enable the module, false to disable the module
*/
static inline void hmac_ll_enable_bus_clock(bool enable)
static inline void _hmac_ll_enable_bus_clock(bool enable)
{
HP_SYS_CLKRST.peri_clk_ctrl25.reg_crypto_hmac_clk_en = enable;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define hmac_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; hmac_ll_enable_bus_clock(__VA_ARGS__)
#define hmac_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _hmac_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset the HMAC peripheral module

4
components/hal/esp32p4/include/hal/i2s_ll.h
View File

@@ -19,6 +19,7 @@
#include "soc/i2s_struct.h"
#include "soc/soc_etm_struct.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "soc/lp_clkrst_struct.h"
#include "soc/soc_etm_source.h"
#include "hal/i2s_types.h"
#include "hal/hal_utils.h"
@@ -122,12 +123,15 @@ static inline void i2s_ll_enable_bus_clock(int i2s_id, bool enable)
switch (i2s_id) {
case 0:
HP_SYS_CLKRST.soc_clk_ctrl2.reg_i2s0_apb_clk_en = enable;
LP_AON_CLKRST.hp_clk_ctrl.hp_pad_i2s0_mclk_en = enable;
return;
case 1:
HP_SYS_CLKRST.soc_clk_ctrl2.reg_i2s1_apb_clk_en = enable;
LP_AON_CLKRST.hp_clk_ctrl.hp_pad_i2s1_mclk_en = enable;
return;
case 2:
HP_SYS_CLKRST.soc_clk_ctrl2.reg_i2s2_apb_clk_en = enable;
LP_AON_CLKRST.hp_clk_ctrl.hp_pad_i2s2_mclk_en = enable;
return;
}
}

2
components/hal/esp32p4/include/hal/isp_ll.h
View File

@@ -198,9 +198,11 @@ static inline void isp_ll_select_clk_source(isp_dev_t *hw, soc_periph_isp_clk_sr
clk_val = 0;
break;
case ISP_CLK_SRC_PLL160:
HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_160m_clk_en = 1;
clk_val = 1;
break;
case ISP_CLK_SRC_PLL240:
HP_SYS_CLKRST.ref_clk_ctrl1.reg_ref_240m_clk_en = 1;
clk_val = 2;
break;
default:

1
components/hal/esp32p4/include/hal/lcd_ll.h
View File

@@ -102,6 +102,7 @@ static inline void lcd_ll_select_clk_src(lcd_cam_dev_t *dev, lcd_clock_source_t
HP_SYS_CLKRST.peri_clk_ctrl19.reg_lcd_clk_src_sel = 0;
break;
case LCD_CLK_SRC_PLL160M:
HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_160m_clk_en = 1;
HP_SYS_CLKRST.peri_clk_ctrl19.reg_lcd_clk_src_sel = 1;
break;
case LCD_CLK_SRC_APLL:

1
components/hal/esp32p4/include/hal/ledc_ll.h
View File

@@ -103,6 +103,7 @@ static inline void ledc_ll_set_slow_clk_sel(ledc_dev_t *hw, ledc_slow_clk_sel_t
clk_sel_val = 1;
break;
case LEDC_SLOW_CLK_PLL_DIV:
HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_80m_clk_en = 1;
clk_sel_val = 2;
break;
default:

1
components/hal/esp32p4/include/hal/mcpwm_ll.h
View File

@@ -168,6 +168,7 @@ static inline void mcpwm_ll_group_set_clock_source(int group_id, soc_module_clk_
clk_id = 1;
break;
case SOC_MOD_CLK_PLL_F160M:
HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_160m_clk_en = 1;
clk_id = 2;
break;
default:

30
components/hal/esp32p4/include/hal/mipi_csi_ll.h
View File

@@ -69,12 +69,14 @@ static inline void mipi_csi_ll_set_phy_clock_source(int group_id, mipi_csi_phy_c
(void)group_id;
switch (source) {
case MIPI_CSI_PHY_CLK_SRC_PLL_F20M:
HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_20m_clk_en = 1;
HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_csi_dphy_clk_src_sel = 0;
break;
case MIPI_CSI_PHY_CLK_SRC_RC_FAST:
HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_csi_dphy_clk_src_sel = 1;
break;
case MIPI_CSI_PHY_CLK_SRC_PLL_F25M:
HP_SYS_CLKRST.ref_clk_ctrl1.reg_ref_25m_clk_en = 1;
HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_csi_dphy_clk_src_sel = 2;
break;
default:
@@ -111,7 +113,7 @@ static inline void mipi_csi_ll_enable_phy_config_clock(int group_id, bool en)
* @param group_id Group ID
* @param en true to enable, false to disable
*/
static inline void mipi_csi_ll_enable_host_bus_clock(int group_id, bool en)
static inline void _mipi_csi_ll_enable_host_bus_clock(int group_id, bool en)
{
(void)group_id;
HP_SYS_CLKRST.soc_clk_ctrl1.reg_csi_host_sys_clk_en = en;
@@ -119,7 +121,31 @@ static inline void mipi_csi_ll_enable_host_bus_clock(int group_id, bool en)
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define mipi_csi_ll_enable_host_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; mipi_csi_ll_enable_host_bus_clock(__VA_ARGS__)
#define mipi_csi_ll_enable_host_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _mipi_csi_ll_enable_host_bus_clock(__VA_ARGS__)
/**
* @brief Enable the clock for MIPI CSI host
*
* @param group_id Group ID
* @param en true to enable, false to disable
*/
static inline void mipi_csi_ll_enable_host_clock(int group_id, bool en)
{
(void)group_id;
MIPI_CSI_BRIDGE.host_ctrl.csi_enableclk = en;
}
/**
* @brief Enable the config clock for MIPI CSI host
*
* @param group_id Group ID
* @param en true to enable, false to disable
*/
static inline void mipi_csi_ll_enable_host_config_clock(int group_id, bool en)
{
(void)group_id;
MIPI_CSI_BRIDGE.host_ctrl.csi_cfg_clk_en = en;
}
/**
* @brief Reset the MIPI CSI host CLK

32
components/hal/esp32p4/include/hal/mipi_dsi_ll.h
View File

@@ -27,7 +27,7 @@ extern "C" {
* @param group_id Group ID
* @param enable true to enable, false to disable
*/
static inline void mipi_dsi_ll_enable_bus_clock(int group_id, bool enable)
static inline void _mipi_dsi_ll_enable_bus_clock(int group_id, bool enable)
{
(void)group_id;
HP_SYS_CLKRST.soc_clk_ctrl1.reg_dsi_sys_clk_en = enable;
@@ -35,7 +35,31 @@ static inline void mipi_dsi_ll_enable_bus_clock(int group_id, bool enable)
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define mipi_dsi_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; mipi_dsi_ll_enable_bus_clock(__VA_ARGS__)
#define mipi_dsi_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _mipi_dsi_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Enable the clock for MIPI DSI host
*
* @param group_id Group ID
* @param en true to enable, false to disable
*/
static inline void mipi_dsi_ll_enable_host_clock(int group_id, bool en)
{
(void)group_id;
MIPI_DSI_BRIDGE.clk_en.clk_en = en;
}
/**
* @brief Enable the config clock for MIPI DSI host
*
* @param group_id Group ID
* @param en true to enable, false to disable
*/
static inline void mipi_dsi_ll_enable_host_config_clock(int group_id, bool en)
{
(void)group_id;
MIPI_DSI_BRIDGE.host_ctrl.dsi_cfg_ref_clk_en = en;
}
/**
* @brief Reset the MIPI DSI module
@@ -83,9 +107,11 @@ static inline void mipi_dsi_ll_set_dpi_clock_source(int group_id, mipi_dsi_dpi_c
HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dpiclk_src_sel = 0;
break;
case MIPI_DSI_DPI_CLK_SRC_PLL_F160M:
HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_160m_clk_en = 1;
HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dpiclk_src_sel = 2;
break;
case MIPI_DSI_DPI_CLK_SRC_PLL_F240M:
// PLL240 has no gating by default in esp_perip_clk_init.
HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dpiclk_src_sel = 1;
break;
default:
@@ -156,12 +182,14 @@ static inline void mipi_dsi_ll_set_phy_clock_source(int group_id, mipi_dsi_phy_c
(void)group_id;
switch (source) {
case MIPI_DSI_PHY_CLK_SRC_PLL_F20M:
HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_20m_clk_en = 1;
HP_SYS_CLKRST.peri_clk_ctrl02.reg_mipi_dsi_dphy_clk_src_sel = 0;
break;
case MIPI_DSI_PHY_CLK_SRC_RC_FAST:
HP_SYS_CLKRST.peri_clk_ctrl02.reg_mipi_dsi_dphy_clk_src_sel = 1;
break;
case MIPI_DSI_PHY_CLK_SRC_PLL_F25M:
HP_SYS_CLKRST.ref_clk_ctrl1.reg_ref_25m_clk_en = 1;
HP_SYS_CLKRST.peri_clk_ctrl02.reg_mipi_dsi_dphy_clk_src_sel = 2;
break;
default:

4
components/hal/esp32p4/include/hal/mpi_ll.h
View File

@@ -23,14 +23,14 @@ extern "C" {
*
* @param enable true to enable the module, false to disable the module
*/
static inline void mpi_ll_enable_bus_clock(bool enable)
static inline void _mpi_ll_enable_bus_clock(bool enable)
{
HP_SYS_CLKRST.peri_clk_ctrl25.reg_crypto_rsa_clk_en = enable;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define mpi_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; mpi_ll_enable_bus_clock(__VA_ARGS__)
#define mpi_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _mpi_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset the MPI peripheral module

5
components/hal/esp32p4/include/hal/parlio_ll.h
View File

@@ -15,6 +15,7 @@
#include "hal/parlio_types.h"
#include "hal/hal_utils.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "soc/lp_clkrst_struct.h"
#include "soc/parl_io_struct.h"
#define PARLIO_LL_RX_MAX_BYTES_PER_FRAME 0xFFFF
@@ -102,6 +103,7 @@ static inline void _parlio_ll_rx_set_clock_source(parl_io_dev_t *dev, parlio_clo
clk_sel = 1;
break;
case PARLIO_CLK_SRC_PLL_F160M:
HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_160m_clk_en = 1;
clk_sel = 2;
break;
case PARLIO_CLK_SRC_EXTERNAL:
@@ -164,6 +166,7 @@ __attribute__((always_inline))
static inline void _parlio_ll_rx_enable_clock(parl_io_dev_t *dev, bool en)
{
(void)dev;
LP_AON_CLKRST.hp_clk_ctrl.hp_pad_parlio_rx_clk_en = en;
HP_SYS_CLKRST.peri_clk_ctrl117.reg_parlio_rx_clk_en = en;
}
@@ -425,6 +428,7 @@ static inline void _parlio_ll_tx_set_clock_source(parl_io_dev_t *dev, parlio_clo
clk_sel = 1;
break;
case PARLIO_CLK_SRC_PLL_F160M:
HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_160m_clk_en = 1;
clk_sel = 2;
break;
case PARLIO_CLK_SRC_EXTERNAL:
@@ -488,6 +492,7 @@ __attribute__((always_inline))
static inline void _parlio_ll_tx_enable_clock(parl_io_dev_t *dev, bool en)
{
(void)dev;
LP_AON_CLKRST.hp_clk_ctrl.hp_pad_parlio_tx_clk_en = en;
HP_SYS_CLKRST.peri_clk_ctrl118.reg_parlio_tx_clk_en = en;
}

6
components/hal/esp32p4/include/hal/pau_ll.h
View File

@@ -22,7 +22,7 @@
extern "C" {
#endif
static inline void pau_ll_enable_bus_clock(bool enable)
static inline void _pau_ll_enable_bus_clock(bool enable)
{
if (enable) {
HP_SYS_CLKRST.soc_clk_ctrl1.reg_regdma_sys_clk_en = 1;
@@ -33,6 +33,10 @@ static inline void pau_ll_enable_bus_clock(bool enable)
}
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define pau_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _pau_ll_enable_bus_clock(__VA_ARGS__)
static inline uint32_t pau_ll_get_regdma_backup_flow_error(pau_dev_t *dev)
{
return dev->regdma_conf.flow_err;

1
components/hal/esp32p4/include/hal/rmt_ll.h
View File

@@ -98,6 +98,7 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel,
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl22, reg_rmt_clk_div_denominator, divider_denominator);
switch (src) {
case RMT_CLK_SRC_PLL_F80M:
HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_80m_clk_en = 1;
HP_SYS_CLKRST.peri_clk_ctrl22.reg_rmt_clk_src_sel = 2;
break;
case RMT_CLK_SRC_RC_FAST:

15
components/hal/esp32p4/include/hal/rtc_io_ll.h
View File

@@ -103,6 +103,21 @@ static inline void rtcio_ll_iomux_func_sel(int rtcio_num, int func)
}
}
/**
* @brief Enable/Disable LP_GPIO peripheral clock.
*
* @param enable true to enable the clock / false to disable the clock
*/
static inline void _rtcio_ll_enable_io_clock(bool enable)
{
LP_GPIO.clk_en.reg_clk_en = enable;
while (LP_GPIO.clk_en.reg_clk_en != enable) {
;
}
}
#define rtcio_ll_enable_io_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _rtcio_ll_enable_io_clock(__VA_ARGS__)
/**
* @brief Select the lp_gpio/hp_gpio function to control the pad.
*

1
components/hal/esp32p4/include/hal/sdmmc_ll.h
View File

@@ -135,6 +135,7 @@ static inline void sdmmc_ll_select_clk_source(sdmmc_dev_t *hw, soc_periph_sdmmc_
uint32_t clk_val = 0;
switch (clk_src) {
case SDMMC_CLK_SRC_PLL160M:
HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_160m_clk_en = 1;
clk_val = 0;
break;
// case SDMMC_CLK_SRC_PLL200M: // TODO: IDF-8886

4
components/hal/esp32p4/include/hal/sha_ll.h
View File

@@ -19,14 +19,14 @@ extern "C" {
*
* @param enable true to enable the module, false to disable the module
*/
static inline void sha_ll_enable_bus_clock(bool enable)
static inline void _sha_ll_enable_bus_clock(bool enable)
{
HP_SYS_CLKRST.peri_clk_ctrl25.reg_crypto_sha_clk_en = enable;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define sha_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; sha_ll_enable_bus_clock(__VA_ARGS__)
#define sha_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _sha_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset the SHA peripheral module

8
components/hal/esp32p4/include/hal/spi_ll.h
View File

@@ -98,7 +98,7 @@ typedef enum {
* @param host_id Peripheral index number, see `spi_host_device_t`
* @param enable Enable/Disable
*/
static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) {
static inline void _spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) {
switch (host_id)
{
case SPI2_HOST:
@@ -115,7 +115,7 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define spi_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; spi_ll_enable_bus_clock(__VA_ARGS__)
#define spi_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _spi_ll_enable_bus_clock(__VA_ARGS__)
/**
* Reset whole peripheral register to init value defined by HW design
@@ -147,7 +147,7 @@ static inline void spi_ll_reset_register(spi_host_device_t host_id) {
* @param host_id Peripheral index number, see `spi_host_device_t`
* @param enable Enable/Disable
*/
static inline void spi_ll_enable_clock(spi_host_device_t host_id, bool enable)
static inline void _spi_ll_enable_clock(spi_host_device_t host_id, bool enable)
{
switch (host_id)
{
@@ -165,7 +165,7 @@ static inline void spi_ll_enable_clock(spi_host_device_t host_id, bool enable)
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define spi_ll_enable_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; spi_ll_enable_clock(__VA_ARGS__)
#define spi_ll_enable_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _spi_ll_enable_clock(__VA_ARGS__)
/**
* Select SPI peripheral clock source (master).

19
components/hal/esp32p4/include/hal/spimem_flash_ll.h
View File

@@ -753,6 +753,7 @@ static inline void _spimem_flash_ll_select_clk_source(uint32_t mspi_id, soc_peri
break;
}
HP_SYS_CLKRST.soc_clk_ctrl0.reg_flash_sys_clk_en = 1;
HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_pll_clk_en = 1;
HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_clk_src_sel = clk_val;
}
@@ -779,6 +780,24 @@ static inline void _spimem_ctrlr_ll_set_core_clock(uint8_t mspi_id, uint32_t fre
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define spimem_ctrlr_ll_set_core_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _spimem_ctrlr_ll_set_core_clock(__VA_ARGS__)
/**
* @brief Disable FLASH MSPI clock
*
* @param mspi_id mspi_id
*/
__attribute__((always_inline))
static inline void _spimem_ctrlr_ll_unset_clock(uint8_t mspi_id)
{
(void)mspi_id;
HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_core_clk_en = 0;
HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_pll_clk_en = 0;
HP_SYS_CLKRST.soc_clk_ctrl0.reg_flash_sys_clk_en = 0;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define spimem_ctrlr_ll_unset_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _spimem_ctrlr_ll_unset_clock(__VA_ARGS__)
/**
* @brief Reset whole memory spi
*/

5
components/hal/esp32p4/include/hal/timer_ll.h
View File

@@ -142,6 +142,7 @@ static inline void timer_ll_set_clock_source(timg_dev_t *hw, uint32_t timer_num,
clk_id = 0;
break;
case GPTIMER_CLK_SRC_PLL_F80M:
HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_80m_clk_en = 1;
clk_id = 2;
break;
case GPTIMER_CLK_SRC_RC_FAST:
@@ -177,7 +178,7 @@ static inline void timer_ll_set_clock_source(timg_dev_t *hw, uint32_t timer_num,
* @param timer_num Timer index in the group
* @param en true to enable, false to disable
*/
static inline void timer_ll_enable_clock(timg_dev_t *hw, uint32_t timer_num, bool en)
static inline void _timer_ll_enable_clock(timg_dev_t *hw, uint32_t timer_num, bool en)
{
if (hw == &TIMERG0) {
if (timer_num == 0) {
@@ -196,7 +197,7 @@ static inline void timer_ll_enable_clock(timg_dev_t *hw, uint32_t timer_num, boo
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define timer_ll_enable_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; timer_ll_enable_clock(__VA_ARGS__)
#define timer_ll_enable_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _timer_ll_enable_clock(__VA_ARGS__)
/**
* @brief Enable alarm event

69
components/hal/esp32p4/include/hal/uart_ll.h
View File

@@ -174,14 +174,38 @@ FORCE_INLINE_ATTR void lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, ui
* @param hw_id LP UART instance ID
* @param enable True to enable, False to disable
*/
static inline void lp_uart_ll_enable_bus_clock(int hw_id, bool enable)
static inline void _lp_uart_ll_enable_bus_clock(int hw_id, bool enable)
{
(void)hw_id;
LPPERI.clk_en.ck_en_lp_uart = enable;
}
// LPPERI.clk_en is a shared register, so this function must be used in an atomic way
#define lp_uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_uart_ll_enable_bus_clock(__VA_ARGS__)
#define lp_uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _lp_uart_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Enable the UART clock.
*
* @param hw_id LP UART instance ID
*/
FORCE_INLINE_ATTR void lp_uart_ll_sclk_enable(int hw_id)
{
(void)hw_id;
LP_UART.clk_conf.tx_sclk_en = 1;
LP_UART.clk_conf.rx_sclk_en = 1;
}
/**
* @brief Disable the UART clock.
*
* @param hw_id LP UART instance ID
*/
FORCE_INLINE_ATTR void lp_uart_ll_sclk_disable(int hw_id)
{
(void)hw_id;
LP_UART.clk_conf.tx_sclk_en = 0;
LP_UART.clk_conf.rx_sclk_en = 0;
}
/**
* @brief Reset LP UART module
@@ -256,7 +280,7 @@ FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
* @param enable true to enable, false to disable
*/
static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable)
static inline void _uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable)
{
switch (uart_num) {
case 0:
@@ -288,7 +312,7 @@ static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable)
}
}
// HP_SYS_CLKRST.soc_clk_ctrlx are shared registers, so this function must be used in an atomic way
#define uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_enable_bus_clock(__VA_ARGS__)
#define uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uart_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset UART module
@@ -336,7 +360,7 @@ static inline void uart_ll_reset_register(uart_port_t uart_num)
* @return None.
*/
FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw)
FORCE_INLINE_ATTR void _uart_ll_sclk_enable(uart_dev_t *hw)
{
if ((hw) == &UART0) {
HP_SYS_CLKRST.peri_clk_ctrl110.reg_uart0_clk_en = 1;
@@ -352,9 +376,11 @@ FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw)
// Not going to implement LP_UART reset in this function, it will have its own LL function
abort();
}
hw->clk_conf.tx_sclk_en = 1;
hw->clk_conf.rx_sclk_en = 1;
}
// HP_SYS_CLKRST.peri_clk_ctrlxxx are shared registers, so this function must be used in an atomic way
#define uart_ll_sclk_enable(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_sclk_enable(__VA_ARGS__)
#define uart_ll_sclk_enable(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uart_ll_sclk_enable(__VA_ARGS__)
/**
* @brief Disable the UART clock.
@@ -363,7 +389,7 @@ FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw)
*
* @return None.
*/
FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
FORCE_INLINE_ATTR void _uart_ll_sclk_disable(uart_dev_t *hw)
{
if ((hw) == &UART0) {
HP_SYS_CLKRST.peri_clk_ctrl110.reg_uart0_clk_en = 0;
@@ -379,9 +405,11 @@ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
// Not going to implement LP_UART reset in this function, it will have its own LL function
abort();
}
hw->clk_conf.tx_sclk_en = 0;
hw->clk_conf.rx_sclk_en = 0;
}
// HP_SYS_CLKRST.peri_clk_ctrlxxx are shared registers, so this function must be used in an atomic way
#define uart_ll_sclk_disable(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_sclk_disable(__VA_ARGS__)
#define uart_ll_sclk_disable(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uart_ll_sclk_disable(__VA_ARGS__)
/**
* @brief Set the UART source clock.
@@ -403,6 +431,7 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_
sel_value = 1;
break;
case UART_SCLK_PLL_F80M:
HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_80m_clk_en = 1;
sel_value = 2;
break;
default:
@@ -991,6 +1020,30 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_t
hw->sleep_conf2.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH;
}
/**
* @brief Enable/disable the UART pad clock in sleep_state
*
* @param hw Beginning address of the peripheral registers.
* @param enable enable or disable
*/
FORCE_INLINE_ATTR void _uart_ll_enable_pad_sleep_clock(uart_dev_t *hw, bool enable)
{
if (hw == &UART0) {
LP_AON_CLKRST.hp_clk_ctrl.hp_pad_uart0_slp_clk_en = 1;
} else if (hw == &UART1) {
LP_AON_CLKRST.hp_clk_ctrl.hp_pad_uart1_slp_clk_en = 1;
} else if (hw == &UART2) {
LP_AON_CLKRST.hp_clk_ctrl.hp_pad_uart2_slp_clk_en = 1;
} else if (hw == &UART3) {
LP_AON_CLKRST.hp_clk_ctrl.hp_pad_uart3_slp_clk_en = 1;
} else if (hw == &UART4) {
LP_AON_CLKRST.hp_clk_ctrl.hp_pad_uart4_slp_clk_en = 1;
}
}
// LP_AON_CLKRST.hp_clk_ctrl is a shared register, so this function must be used in an atomic way
#define uart_ll_enable_pad_sleep_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uart_ll_enable_pad_sleep_clock(__VA_ARGS__)
/**
* @brief Configure the UART work in normal mode.
*

4
components/hal/esp32p4/include/hal/usb_serial_jtag_ll.h
View File

@@ -331,7 +331,7 @@ FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_pad(bool enable)
* @brief Enable the bus clock for USJ module
* @param clk_en True if enable the clock of USJ module
*/
FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_bus_clock(bool clk_en)
FORCE_INLINE_ATTR void _usb_serial_jtag_ll_enable_bus_clock(bool clk_en)
{
HP_SYS_CLKRST.soc_clk_ctrl2.reg_usb_device_apb_clk_en = clk_en;
// Enable PHY clock (48MHz) for USB FSLS PHY 0
@@ -339,7 +339,7 @@ FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_bus_clock(bool clk_en)
}
// HP_SYS_CLKRST.soc_clk_ctrlx and LP_AON_CLKRST.hp_usb_clkrst_ctrlx are shared registers, so this function must be used in an atomic way
#define usb_serial_jtag_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_serial_jtag_ll_enable_bus_clock(__VA_ARGS__)
#define usb_serial_jtag_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _usb_serial_jtag_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset the USJ module

4
components/hal/esp32p4/include/hal/usb_utmi_ll.h
View File

@@ -39,7 +39,7 @@ FORCE_INLINE_ATTR void usb_utmi_ll_configure_ls(usb_utmi_dev_t *hw, bool paralle
*
* @param[in] clk_en True to enable, false to disable
*/
FORCE_INLINE_ATTR void usb_utmi_ll_enable_bus_clock(bool clk_en)
FORCE_INLINE_ATTR void _usb_utmi_ll_enable_bus_clock(bool clk_en)
{
// Enable/disable system clock for USB_UTMI and USB_DWC_HS
HP_SYS_CLKRST.soc_clk_ctrl1.reg_usb_otg20_sys_clk_en = clk_en;
@@ -48,7 +48,7 @@ FORCE_INLINE_ATTR void usb_utmi_ll_enable_bus_clock(bool clk_en)
}
// HP_SYS_CLKRST.soc_clk_ctrlx and LP_AON_CLKRST.hp_usb_clkrst_ctrlx are shared registers, so this function must be used in an atomic way
#define usb_utmi_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_utmi_ll_enable_bus_clock(__VA_ARGS__)
#define usb_utmi_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _usb_utmi_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset the USB UTMI PHY and USB_DWC_HS controller