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feat(soc): added soc support for esp32p4, part3
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Armando
180
components/soc/esp32p4/include/soc/lp_wdt_struct.h
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180
components/soc/esp32p4/include/soc/lp_wdt_struct.h
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/**
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef volatile struct {
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union {
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struct {
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uint32_t reserved0 : 2;
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uint32_t wdt_chip_reset_width : 8; /*chip reset siginal pulse width*/
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uint32_t wdt_chip_reset_en : 1; /*wdt reset whole chip enable*/
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uint32_t wdt_pause_in_slp : 1; /*pause WDT in sleep*/
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uint32_t wdt_flashboot_mod_en : 1; /*enable WDT in flash boot*/
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uint32_t wdt_sys_reset_length : 3; /*system reset counter length*/
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uint32_t wdt_cpu_reset_length : 3; /*CPU reset counter length*/
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uint32_t wdt_stg3 : 3; /*1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC reset stage en*/
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uint32_t wdt_stg2 : 3; /*1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC reset stage en*/
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uint32_t wdt_stg1 : 3; /*1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC reset stage en*/
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uint32_t wdt_stg0 : 3; /*1: interrupt stage en; 2: CPU reset stage en; 3: system reset stage en ; 4: RTC reset stage en*/
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uint32_t wdt_en : 1;
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};
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uint32_t val;
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} wdtconfig0;
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union {
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struct {
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uint32_t reserved0 : 26;
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uint32_t wdt_lp_peri_reset_en : 1; /*enable WDT reset LP PERI*/
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uint32_t wdt_lp_cpu_reset_en : 1; /*enable WDT reset LP CPU*/
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uint32_t wdt_core3cpu_reset_en : 1; /*enable WDT reset CORE3 CPU*/
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uint32_t wdt_core2cpu_reset_en : 1; /*enable WDT reset CORE2 CPU*/
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uint32_t wdt_core1cpu_reset_en : 1; /*enable WDT reset CORE1 CPU*/
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uint32_t wdt_core0cpu_reset_en : 1; /*enable WDT reset CORE0 CPU*/
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};
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uint32_t val;
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} wdtcpurst;
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uint32_t wdtconfig1;
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uint32_t wdtconfig2;
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uint32_t wdtconfig3;
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uint32_t wdtconfig4;
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union {
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struct {
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uint32_t reserved0 : 31;
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uint32_t wdt_feed : 1;
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};
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uint32_t val;
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} wdtfeed;
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uint32_t wdtwprotect;
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union {
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struct {
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uint32_t swd_reset_flag : 1; /*swd reset flag*/
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uint32_t swd_feed_int : 1; /*swd interrupt for feeding*/
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uint32_t reserved2 : 16;
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uint32_t swd_signal_width : 10; /*adjust signal width send to swd*/
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uint32_t swd_rst_flag_clr : 1; /*reset swd reset flag*/
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uint32_t swd_feed : 1; /*Sw feed swd*/
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uint32_t swd_disable : 1; /*disabel SWD*/
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uint32_t swd_auto_feed_en : 1; /*automatically feed swd when int comes*/
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};
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uint32_t val;
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} swd_conf;
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uint32_t swd_wprotect;
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union {
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struct {
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uint32_t clk_en : 1;
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uint32_t reserved1 : 31;
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};
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uint32_t val;
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} wdt_clk_en;
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union {
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struct {
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uint32_t wdt : 1; /*enable RTC WDT interrupt*/
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uint32_t swd : 1; /*enable super watch dog interrupt*/
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uint32_t reserved2 : 30;
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};
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uint32_t val;
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} int_ena_w1ts;
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union {
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struct {
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uint32_t wdt : 1; /*enable RTC WDT interrupt*/
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uint32_t swd : 1; /*enable super watch dog interrupt*/
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uint32_t reserved2 : 30;
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};
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uint32_t val;
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} int_ena_w1tc;
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union {
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struct {
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uint32_t wdt : 1; /*enable RTC WDT interrupt*/
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uint32_t swd : 1; /*enable super watch dog interrupt*/
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uint32_t xtal32k_dead : 1; /*enable xtal32k_dead interrupt*/
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uint32_t reserved3 : 29;
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};
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uint32_t val;
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} int_ena;
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union {
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struct {
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uint32_t wdt : 1; /*RTC WDT interrupt raw*/
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uint32_t swd : 1; /*super watch dog interrupt raw*/
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uint32_t xtal32k_dead : 1; /*xtal32k dead detection interrupt raw*/
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uint32_t reserved3 : 29;
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};
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uint32_t val;
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} int_raw;
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union {
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struct {
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uint32_t wdt : 1; /*watch dog interrupt state*/
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uint32_t swd : 1; /*super watch dog interrupt state*/
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uint32_t xtal32k_dead : 1; /*xtal32k dead detection interrupt state*/
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uint32_t reserved3 : 29;
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};
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uint32_t val;
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} int_swd_st;
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union {
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struct {
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uint32_t wdt : 1; /*Clear RTC WDT interrupt state*/
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uint32_t swd : 1; /*Clear super watch dog interrupt state*/
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uint32_t xtal32k_dead : 1; /*Clear RTC WDT interrupt state*/
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uint32_t reserved3 : 29;
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};
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uint32_t val;
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} int_clr;
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union {
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struct {
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uint32_t xtal32k_wdt_en : 1; /*xtal 32k watch dog enable*/
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uint32_t xtal32k_wdt_clk_fo : 1; /*xtal 32k watch dog clock force on*/
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uint32_t xtal32k_wdt_reset : 1; /*xtal 32k watch dog sw reset*/
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uint32_t xtal32k_ext_clk_fo : 1; /*xtal 32k external xtal clock force on*/
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uint32_t xtal32k_auto_backup : 1; /*xtal 32k switch to back up clock when xtal is dead*/
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uint32_t xtal32k_auto_restart : 1; /*xtal 32k restart xtal when xtal is dead*/
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uint32_t xtal32k_auto_return : 1; /*xtal 32k switch back xtal when xtal is restarted*/
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uint32_t xtal32k_xpd_force : 1; /*Xtal 32k xpd control by sw or fsm*/
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uint32_t enckinit_xtal_32k : 1; /*apply an internal clock to help xtal 32k to start*/
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uint32_t dbuf_xtal_32k : 1; /*0: single-end buffer 1: differential buffer*/
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uint32_t dgm_xtal_32k : 3; /*xtal_32k gm control*/
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uint32_t dres_xtal_32k : 3; /*DRES_XTAL_32K*/
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uint32_t xpd_xtal_32k : 1; /*XPD_XTAL_32K*/
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uint32_t dac_xtal_32k : 3; /*DAC_XTAL_32K*/
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uint32_t wdt_state : 3; /*state of 32k_wdt*/
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uint32_t xtal32k_gpio_sel : 1; /*XTAL_32K sel. ; 0: external XTAL_32K; 1: CLK from RTC pad X32P_C*/
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uint32_t reserved24 : 6;
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uint32_t xtl_ext_ctr_lv : 1; /*0: power down XTAL at high level; 1: power down XTAL at low level*/
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uint32_t xtl_ext_ctr_en : 1;
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};
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uint32_t val;
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} ext_xtl_conf;
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uint32_t xtal32k_clk_factor;
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uint32_t reserved_4c;
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uint32_t reserved_50;
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uint32_t reserved_54;
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uint32_t reserved_58;
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union {
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struct {
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uint32_t xtal32k_return_wait : 4; /*cycles to wait to return noral xtal 32k*/
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uint32_t xtal32k_restart_wait : 16; /*cycles to wait to repower on xtal 32k*/
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uint32_t xtal32k_wdt_timeout : 8; /*If no clock detected for this amount of time,32k is regarded as dead*/
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uint32_t xtal32k_stable_thres : 4; /*if restarted xtal32k period is smaller than this, it is regarded as stable*/
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};
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uint32_t val;
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} xtal32k_conf;
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union {
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struct {
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uint32_t swd_disable_efuse_force : 1; /*swd disable default choose efuse control bit*/
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uint32_t wdt_flashboot_efuse_force : 1; /*lp_wdt flashboot en default choose efuse control bit*/
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uint32_t reserved2 : 30;
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};
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uint32_t val;
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} efuse_force;
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} lp_wdt_dev_t;
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extern lp_wdt_dev_t LP_WDT;
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#ifdef __cplusplus
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}
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#endif
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