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test(esp_flash): Enable test for spi_flash component for c61/c5

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C.S.M
2024-09-02 13:17:23 +08:00
parent ec3029ebb3
commit 0878ff90d6
10 changed files with 18 additions and 42 deletions
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2
components/hal/esp32c61/include/hal/gpspi_flash_ll.h
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@@ -24,8 +24,6 @@
#include <string.h> #include <string.h>
#include "hal/misc.h" #include "hal/misc.h"
// TODO: [ESP32C61] IDF-9314, inherit from c6
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif

24
components/spi_flash/test_apps/.build-test-rules.yml
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@@ -1,10 +1,6 @@
# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps # Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
components/spi_flash/test_apps/esp_flash: components/spi_flash/test_apps/esp_flash:
disable:
- if: IDF_TARGET in ["esp32c5", "esp32c61"]
temporary: true
reason: not support yet # TODO: [ESP32C5] IDF-8715, [esp32c61] IDF-9314
depends_filepatterns: depends_filepatterns:
- components/bootloader_support/bootloader_flash/**/* - components/bootloader_support/bootloader_flash/**/*
depends_components: depends_components:
@@ -16,10 +12,9 @@ components/spi_flash/test_apps/esp_flash:
- esptool_py # Some flash related kconfigs are listed here. - esptool_py # Some flash related kconfigs are listed here.
components/spi_flash/test_apps/esp_flash_stress: components/spi_flash/test_apps/esp_flash_stress:
disable: depends_components:
- if: IDF_TARGET == "esp32c5" - esp_mm
temporary: true - spi_flash
reason: not support yet # TODO: [ESP32C5] IDF-8715, IDF-10313
components/spi_flash/test_apps/flash_encryption: components/spi_flash/test_apps/flash_encryption:
disable_test: disable_test:
@@ -52,21 +47,8 @@ components/spi_flash/test_apps/flash_suspend:
components/spi_flash/test_apps/mspi_test: components/spi_flash/test_apps/mspi_test:
disable: disable:
- if: IDF_TARGET in ["esp32c5", "esp32c61"]
temporary: true
reason: not support yet # TODO: [ESP32C5] IDF-8715, [esp32c61] IDF9316
- if: CONFIG_NAME == "psram" and SOC_SPIRAM_SUPPORTED != 1 - if: CONFIG_NAME == "psram" and SOC_SPIRAM_SUPPORTED != 1
- if: CONFIG_NAME == "xip_psram" and SOC_SPIRAM_SUPPORTED != 1 - if: CONFIG_NAME == "xip_psram" and SOC_SPIRAM_SUPPORTED != 1
- if: CONFIG_NAME == "psram" and IDF_TARGET in ["esp32p4"]
temporary: true
reason: not supported yet #TODO: IDF-7499 for p4
- if: CONFIG_NAME == "xip_psram" and IDF_TARGET in ["esp32p4"]
temporary: true
reason: not supported yet #TODO: IDF-7556 for p4
disable_test:
- if: IDF_TARGET == "esp32p4"
temporary: true
reason: test not pass, should be re-enable # TODO: IDF-8985
depends_filepatterns: depends_filepatterns:
- components/bootloader_support/bootloader_flash/**/* - components/bootloader_support/bootloader_flash/**/*
depends_components: depends_components:

4
components/spi_flash/test_apps/esp_flash/README.md
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@@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |

2
components/spi_flash/test_apps/esp_flash/main/test_esp_flash_def.h
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@@ -68,7 +68,7 @@
#define HSPI_PIN_NUM_WP FSPI_PIN_NUM_WP #define HSPI_PIN_NUM_WP FSPI_PIN_NUM_WP
#define HSPI_PIN_NUM_CS FSPI_PIN_NUM_CS #define HSPI_PIN_NUM_CS FSPI_PIN_NUM_CS
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C6 #elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C61
#define SPI1_CS_IO 26 //the pin which is usually used by the PSRAM cs #define SPI1_CS_IO 26 //the pin which is usually used by the PSRAM cs
#define SPI1_HD_IO 27 //the pin which is usually used by the PSRAM hd #define SPI1_HD_IO 27 //the pin which is usually used by the PSRAM hd
#define SPI1_WP_IO 28 //the pin which is usually used by the PSRAM wp #define SPI1_WP_IO 28 //the pin which is usually used by the PSRAM wp

1
components/spi_flash/test_apps/esp_flash/pytest_esp_flash.py
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@@ -5,7 +5,6 @@ from pytest_embedded import Dut
@pytest.mark.supported_targets @pytest.mark.supported_targets
@pytest.mark.temp_skip_ci(targets=['esp32c5', 'esp32c61'], reason='not support yet') # TODO: [ESP32C5] IDF-8715, IDF-10313, [ESP32C61] IDF-9314 IDF-10991
@pytest.mark.generic @pytest.mark.generic
@pytest.mark.parametrize( @pytest.mark.parametrize(
'config', 'config',

4
components/spi_flash/test_apps/esp_flash_stress/README.md
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@@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |

1
components/spi_flash/test_apps/esp_flash_stress/pytest_esp_flash_stress.py
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@@ -5,7 +5,6 @@ from pytest_embedded import Dut
@pytest.mark.supported_targets @pytest.mark.supported_targets
@pytest.mark.temp_skip_ci(targets=['esp32c5'], reason='not support yet') # TODO: [ESP32C5] IDF-8715, IDF-10313
@pytest.mark.generic @pytest.mark.generic
@pytest.mark.parametrize( @pytest.mark.parametrize(
'config', 'config',

4
components/spi_flash/test_apps/mspi_test/README.md
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@@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | | Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | | ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |

14
components/spi_flash/test_apps/mspi_test/main/test_read_write.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -280,7 +280,12 @@ TEST_CASE("Test esp_flash_write", "[spi_flash][esp_flash]")
* NB: At the moment these only support aligned addresses, because memcpy * NB: At the moment these only support aligned addresses, because memcpy
* is not aware of the 32-but load requirements for these regions. * is not aware of the 32-but load requirements for these regions.
*/ */
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6 #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2
ESP_ERROR_CHECK(esp_flash_write(NULL, (char *) 0x40000000, start, 16));
ESP_ERROR_CHECK(esp_flash_write(NULL, (char *) 0x40070000, start, 16));
ESP_ERROR_CHECK(esp_flash_write(NULL, (char *) 0x40078000, start, 16));
ESP_ERROR_CHECK(esp_flash_write(NULL, (char *) 0x40080000, start, 16));
#else
#define TEST_SOC_IROM_ADDR (SOC_IROM_LOW) #define TEST_SOC_IROM_ADDR (SOC_IROM_LOW)
#define TEST_SOC_CACHE_RAM_BANK0_ADDR (SOC_IRAM_LOW) #define TEST_SOC_CACHE_RAM_BANK0_ADDR (SOC_IRAM_LOW)
#define TEST_SOC_CACHE_RAM_BANK1_ADDR (SOC_IRAM_LOW + 0x2000) #define TEST_SOC_CACHE_RAM_BANK1_ADDR (SOC_IRAM_LOW + 0x2000)
@@ -297,11 +302,6 @@ TEST_CASE("Test esp_flash_write", "[spi_flash][esp_flash]")
ESP_ERROR_CHECK(esp_flash_write(NULL, (char *) TEST_SOC_CACHE_RAM_BANK3_ADDR, start, 16)); ESP_ERROR_CHECK(esp_flash_write(NULL, (char *) TEST_SOC_CACHE_RAM_BANK3_ADDR, start, 16));
ESP_ERROR_CHECK(esp_flash_write(NULL, (char *) TEST_SOC_RTC_IRAM_ADDR, start, 16)); ESP_ERROR_CHECK(esp_flash_write(NULL, (char *) TEST_SOC_RTC_IRAM_ADDR, start, 16));
ESP_ERROR_CHECK(esp_flash_write(NULL, (char *) TEST_SOC_RTC_DRAM_ADDR, start, 16)); ESP_ERROR_CHECK(esp_flash_write(NULL, (char *) TEST_SOC_RTC_DRAM_ADDR, start, 16));
#else
ESP_ERROR_CHECK(esp_flash_write(NULL, (char *) 0x40000000, start, 16));
ESP_ERROR_CHECK(esp_flash_write(NULL, (char *) 0x40070000, start, 16));
ESP_ERROR_CHECK(esp_flash_write(NULL, (char *) 0x40078000, start, 16));
ESP_ERROR_CHECK(esp_flash_write(NULL, (char *) 0x40080000, start, 16));
#endif #endif
} }

4
components/spi_flash/test_apps/mspi_test/pytest_mspi_test.py
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@@ -1,11 +1,9 @@
# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD # SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
import pytest import pytest
from pytest_embedded import Dut from pytest_embedded import Dut
# TODO: [ESP32P4] IDF-8985 [ESP32C5] IDF-8715, IDF-10313, [ESP32C61] IDF-9314 IDF-10991
@pytest.mark.temp_skip_ci(targets=['esp32p4', 'esp32c5', 'esp32c61'], reason='esp32p4, esp32c5 support TBD')
@pytest.mark.supported_targets @pytest.mark.supported_targets
@pytest.mark.generic @pytest.mark.generic
@pytest.mark.parametrize( @pytest.mark.parametrize(