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wifi/bt coexistence: Fix disabled cache access race when writing to flash
Moves the ets_timer_arm() / ets_timer_disarm() code paths to RAM Overhead is 740 bytes of IRAM, 0 bytes DRAM (For comparison: If all of esp_timer.c is moved to RAM, overhead is 1068 bytes IRAM and 480 bytes DRAM.)
This commit is contained in:

committed by
Angus Gratton

parent
b013f5d490
commit
094cf4d79d
@@ -7,6 +7,7 @@
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "esp_spi_flash.h"
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TEST_CASE("ets_timer produces correct delay", "[ets_timer]")
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{
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@@ -192,3 +193,46 @@ TEST_CASE("multiple ETSTimers are ordered correctly", "[ets_timer]")
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#undef N
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}
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/* WiFi/BT coexistence will sometimes arm/disarm
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timers from an ISR where flash may be disabled. */
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IRAM_ATTR TEST_CASE("ETSTimers arm & disarm run from IRAM", "[ets_timer]")
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{
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void timer_func(void* arg)
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{
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volatile bool *b = (volatile bool *)arg;
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*b = true;
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}
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volatile bool flag = false;
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ETSTimer timer1;
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const int INTERVAL = 5;
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ets_timer_setfn(&timer1, &timer_func, (void *)&flag);
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/* arm a disabled timer, then disarm a live timer */
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g_flash_guard_default_ops.start(); // Disables flash cache
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ets_timer_arm(&timer1, INTERVAL, false);
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// redundant call is deliberate (test code path if already armed)
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ets_timer_arm(&timer1, INTERVAL, false);
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ets_timer_disarm(&timer1);
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g_flash_guard_default_ops.end(); // Re-enables flash cache
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TEST_ASSERT_FALSE(flag); // didn't expire yet
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/* do the same thing but wait for the timer to expire */
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g_flash_guard_default_ops.start();
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ets_timer_arm(&timer1, INTERVAL, false);
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g_flash_guard_default_ops.end();
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vTaskDelay(2 * INTERVAL / portTICK_PERIOD_MS);
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TEST_ASSERT_TRUE(flag);
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g_flash_guard_default_ops.start();
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ets_timer_disarm(&timer1);
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g_flash_guard_default_ops.end();
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}
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