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feat(rom): update rom for c5 eco2

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Breaking: Starting from this commit, ESP-IDF can only support ESP32-C5 v1.0 (ECO2)
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laokaiyao
2025-04-08 12:48:49 +08:00
parent 61064b442a
commit 0abc755342
24 changed files with 241 additions and 392 deletions
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26
components/bootloader/subproject/main/ld/esp32c5/bootloader.ld
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@@ -7,20 +7,20 @@
* Make sure the bootloader can load into main memory without overwriting itself.
*
* ESP32-C5 ROM static data usage is as follows:
* - 0x4084e9a0 - 0x4085c9a0: Shared buffers, used in UART/USB/SPI download mode only
* - 0x4085c9a0 - 0x4085e9a0: PRO CPU stack, can be reclaimed as heap after RTOS startup
* - 0x4085e9a0 - 0x40860000: ROM .bss and .data (not easily reclaimable)
* - 0x4084e5a0 - 0x4085c5a0: Shared buffers, used in UART/USB/SPI download mode only
* - 0x4085c5a0 - 0x4085e5a0: PRO CPU stack, can be reclaimed as heap after RTOS startup
* - 0x4085e5a0 - 0x40860000: ROM .bss and .data (not easily reclaimable)
*
* The 2nd stage bootloader can take space up to the end of ROM shared
* buffers area (0x4085c9a0).
* buffers area (0x4085c5a0).
*/
/* We consider 0x4085c9a0 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
/* We consider 0x4085c5a0 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
* and work out iram_seg and iram_loader_seg addresses from there, backwards.
*/
/* These lengths can be adjusted, if necessary: */
bootloader_usable_dram_end = 0x4085c9a0;
bootloader_usable_dram_end = 0x4085c5a0;
bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
bootloader_dram_seg_len = 0x5000;
bootloader_iram_loader_seg_len = 0x7000;
@@ -45,7 +45,7 @@ MEMORY
* 2. Update the value in this assert.
* 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32c5/memory.ld.in to the same value.
*/
ASSERT(bootloader_iram_loader_seg_start == 0x4084E9A0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
ASSERT(bootloader_iram_loader_seg_start == 0x4084e5a0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
/* Default entry point: */
ENTRY(call_start_cpu0);
@@ -277,32 +277,32 @@ SECTIONS
/**
* Appendix: Memory Usage of ROM bootloader
*
* 0x4084e9a0 ------------------> _dram0_0_start
* 0x4084e5a0 ------------------> _dram0_0_start
* | |
* | |
* | | 1. Large buffers that are only used in certain boot modes, see shared_buffers.h
* | |
* | |
* 0x4085c9a0 ------------------> __stack_sentry
* 0x4085c5a0 ------------------> __stack_sentry
* | |
* | | 2. Startup pro cpu stack (freed when IDF app is running)
* | |
* 0x4085e9a0 ------------------> __stack (pro cpu)
* 0x4085e5a0 ------------------> __stack (pro cpu)
* | |
* | |
* | | 3. Shared memory only used in startup code or nonos/early boot*
* | | (can be freed when IDF runs)
* | |
* | |
* 0x4085f500 ------------------> _dram0_rtos_reserved_start
* 0x4085f4f8 ------------------> _dram0_rtos_reserved_start
* | |
* | |
* | | 4. Shared memory used in startup code and when IDF runs
* | |
* | |
* 0x4085fc5c ------------------> _dram0_rtos_reserved_end
* 0x4085fbb4 ------------------> _dram0_rtos_reserved_end
* | |
* 0x4085fc70 ------------------> _data_start_interface
* 0x4085fc60 ------------------> _data_start_interface
* | |
* | | 5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
* | |