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feat(rom): update rom for c5 eco2

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Breaking: Starting from this commit, ESP-IDF can only support ESP32-C5 v1.0 (ECO2)
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laokaiyao
2025-04-08 12:48:49 +08:00
parent 61064b442a
commit 0abc755342
24 changed files with 241 additions and 392 deletions
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components/soc/esp32c5/include/soc/soc.h
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@@ -202,7 +202,7 @@
#define SOC_CPU_SUBSYSTEM_HIGH 0x30000000
// Start (highest address) of ROM boot stack, only relevant during early boot
#define SOC_ROM_STACK_START 0x4085e9a0
#define SOC_ROM_STACK_START 0x4085e5a0
#define SOC_ROM_STACK_SIZE 0x2000
//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.