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Rename Kconfig options (components/esp32)

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This commit is contained in:
Roland Dobai
2019-04-30 12:51:55 +02:00
parent d4af5e6fff
commit 0ae53691ba
116 changed files with 773 additions and 701 deletions
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10
components/soc/esp32/soc_memory_layout.c
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@@ -60,7 +60,7 @@ const soc_memory_type_desc_t soc_memory_types[] = {
{ "PID5DRAM", { MALLOC_CAP_PID5|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
{ "PID6DRAM", { MALLOC_CAP_PID6|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
{ "PID7DRAM", { MALLOC_CAP_PID7|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
#ifdef CONFIG_SPIRAM_SUPPORT
#ifdef CONFIG_ESP32_SPIRAM_SUPPORT
//Type 15: SPI SRAM data
{ "SPIRAM", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false},
#endif
@@ -75,7 +75,7 @@ Because of requirements in the coalescing code which merges adjacent regions, th
from low to high start address.
*/
const soc_memory_region_t soc_memory_regions[] = {
#ifdef CONFIG_SPIRAM_SUPPORT
#ifdef CONFIG_ESP32_SPIRAM_SUPPORT
{ 0x3F800000, 0x400000, 15, 0}, //SPI SRAM, if available
#endif
{ 0x3FFAE000, 0x2000, 0, 0}, //pool 16 <- used for rom code
@@ -158,15 +158,15 @@ SOC_RESERVE_MEMORY_REGION(0x3ffe3f20, 0x3ffe4350, rom_app_data); //Reserve ROM A
SOC_RESERVE_MEMORY_REGION(0x3ffae000, 0x3ffae6e0, rom_data);
#if CONFIG_MEMMAP_TRACEMEM
#if CONFIG_MEMMAP_TRACEMEM_TWOBANKS
#if CONFIG_ESP32_MEMMAP_TRACEMEM
#if CONFIG_ESP32_MEMMAP_TRACEMEM_TWOBANKS
SOC_RESERVE_MEMORY_REGION(0x3fff8000, 0x40000000, trace_mem); //Reserve trace mem region, 32K for both cpu
#else
SOC_RESERVE_MEMORY_REGION(0x3fffc000, 0x40000000, trace_mem); //Reserve trace mem region, 16K (upper-half) for pro cpu
#endif
#endif
#ifdef CONFIG_SPIRAM_SUPPORT
#ifdef CONFIG_ESP32_SPIRAM_SUPPORT
SOC_RESERVE_MEMORY_REGION(0x3f800000, 0x3fC00000, spi_ram); //SPI RAM gets added later if needed, in spiram.c; reserve it for now
#endif