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https://github.com/espressif/esp-idf.git
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efuse(c6): Adds adc calib efuses
This commit is contained in:
KonstantinKondrashov
committed by
laokaiyao
laokaiyao
parent
6336a9e2b5
commit
0b7485db02
@@ -799,49 +799,168 @@ extern "C" {
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* Register $n of BLOCK2 (system).
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*/
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#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
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/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0;
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* Stores the fourth 32 bits of the first part of system data.
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/** EFUSE_TEMP_CALIB : R; bitpos: [8:0]; default: 0;
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* Temperature calibration data
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*/
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#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S)
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#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_4_S 0
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#define EFUSE_TEMP_CALIB 0x000001FFU
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#define EFUSE_TEMP_CALIB_M (EFUSE_TEMP_CALIB_V << EFUSE_TEMP_CALIB_S)
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#define EFUSE_TEMP_CALIB_V 0x000001FFU
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#define EFUSE_TEMP_CALIB_S 0
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/** EFUSE_OCODE : R; bitpos: [16:9]; default: 0;
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* ADC OCode
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*/
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#define EFUSE_OCODE 0x000000FFU
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#define EFUSE_OCODE_M (EFUSE_OCODE_V << EFUSE_OCODE_S)
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#define EFUSE_OCODE_V 0x000000FFU
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#define EFUSE_OCODE_S 9
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/** EFUSE_ADC1_INIT_CODE_ATTEN0 : R; bitpos: [26:17]; default: 0;
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* ADC1 init code at atten0
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*/
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#define EFUSE_ADC1_INIT_CODE_ATTEN0 0x000003FFU
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_M (EFUSE_ADC1_INIT_CODE_ATTEN0_V << EFUSE_ADC1_INIT_CODE_ATTEN0_S)
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_V 0x000003FFU
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_S 17
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/** EFUSE_ADC1_INIT_CODE_ATTEN1 : R; bitpos: [31:27]; default: 0;
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* ADC1 init code at atten1
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*/
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#define EFUSE_ADC1_INIT_CODE_ATTEN1 0x0000001FU
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#define EFUSE_ADC1_INIT_CODE_ATTEN1_M (EFUSE_ADC1_INIT_CODE_ATTEN1_V << EFUSE_ADC1_INIT_CODE_ATTEN1_S)
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#define EFUSE_ADC1_INIT_CODE_ATTEN1_V 0x0000001FU
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#define EFUSE_ADC1_INIT_CODE_ATTEN1_S 27
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/** EFUSE_RD_SYS_PART1_DATA5_REG register
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* Register $n of BLOCK2 (system).
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*/
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#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
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/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0;
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* Stores the fifth 32 bits of the first part of system data.
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/** EFUSE_ADC1_INIT_CODE_ATTEN1_1 : R; bitpos: [4:0]; default: 0;
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* ADC1 init code at atten1
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*/
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#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S)
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#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_5_S 0
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#define EFUSE_ADC1_INIT_CODE_ATTEN1_1 0x0000001FU
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#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_M (EFUSE_ADC1_INIT_CODE_ATTEN1_1_V << EFUSE_ADC1_INIT_CODE_ATTEN1_1_S)
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#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_V 0x0000001FU
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#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_S 0
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/** EFUSE_ADC1_INIT_CODE_ATTEN2 : R; bitpos: [14:5]; default: 0;
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* ADC1 init code at atten2
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*/
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#define EFUSE_ADC1_INIT_CODE_ATTEN2 0x000003FFU
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#define EFUSE_ADC1_INIT_CODE_ATTEN2_M (EFUSE_ADC1_INIT_CODE_ATTEN2_V << EFUSE_ADC1_INIT_CODE_ATTEN2_S)
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#define EFUSE_ADC1_INIT_CODE_ATTEN2_V 0x000003FFU
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#define EFUSE_ADC1_INIT_CODE_ATTEN2_S 5
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/** EFUSE_ADC1_INIT_CODE_ATTEN3 : R; bitpos: [24:15]; default: 0;
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* ADC1 init code at atten3
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*/
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#define EFUSE_ADC1_INIT_CODE_ATTEN3 0x000003FFU
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#define EFUSE_ADC1_INIT_CODE_ATTEN3_M (EFUSE_ADC1_INIT_CODE_ATTEN3_V << EFUSE_ADC1_INIT_CODE_ATTEN3_S)
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#define EFUSE_ADC1_INIT_CODE_ATTEN3_V 0x000003FFU
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#define EFUSE_ADC1_INIT_CODE_ATTEN3_S 15
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/** EFUSE_ADC1_CAL_VOL_ATTEN0 : R; bitpos: [31:25]; default: 0;
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* ADC1 calibration voltage at atten0
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*/
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#define EFUSE_ADC1_CAL_VOL_ATTEN0 0x0000007FU
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#define EFUSE_ADC1_CAL_VOL_ATTEN0_M (EFUSE_ADC1_CAL_VOL_ATTEN0_V << EFUSE_ADC1_CAL_VOL_ATTEN0_S)
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#define EFUSE_ADC1_CAL_VOL_ATTEN0_V 0x0000007FU
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#define EFUSE_ADC1_CAL_VOL_ATTEN0_S 25
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/** EFUSE_RD_SYS_PART1_DATA6_REG register
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* Register $n of BLOCK2 (system).
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*/
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#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
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/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0;
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* Stores the sixth 32 bits of the first part of system data.
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/** EFUSE_ADC1_CAL_VOL_ATTEN0_1 : R; bitpos: [2:0]; default: 0;
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* ADC1 calibration voltage at atten0
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*/
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#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S)
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#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_6_S 0
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#define EFUSE_ADC1_CAL_VOL_ATTEN0_1 0x00000007U
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#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_M (EFUSE_ADC1_CAL_VOL_ATTEN0_1_V << EFUSE_ADC1_CAL_VOL_ATTEN0_1_S)
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#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_V 0x00000007U
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#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_S 0
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/** EFUSE_ADC1_CAL_VOL_ATTEN1 : R; bitpos: [12:3]; default: 0;
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* ADC1 calibration voltage at atten1
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*/
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#define EFUSE_ADC1_CAL_VOL_ATTEN1 0x000003FFU
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#define EFUSE_ADC1_CAL_VOL_ATTEN1_M (EFUSE_ADC1_CAL_VOL_ATTEN1_V << EFUSE_ADC1_CAL_VOL_ATTEN1_S)
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#define EFUSE_ADC1_CAL_VOL_ATTEN1_V 0x000003FFU
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#define EFUSE_ADC1_CAL_VOL_ATTEN1_S 3
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/** EFUSE_ADC1_CAL_VOL_ATTEN2 : R; bitpos: [22:13]; default: 0;
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* ADC1 calibration voltage at atten2
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*/
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#define EFUSE_ADC1_CAL_VOL_ATTEN2 0x000003FFU
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#define EFUSE_ADC1_CAL_VOL_ATTEN2_M (EFUSE_ADC1_CAL_VOL_ATTEN2_V << EFUSE_ADC1_CAL_VOL_ATTEN2_S)
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#define EFUSE_ADC1_CAL_VOL_ATTEN2_V 0x000003FFU
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#define EFUSE_ADC1_CAL_VOL_ATTEN2_S 13
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/** EFUSE_ADC1_CAL_VOL_ATTEN3 : R; bitpos: [31:23]; default: 0;
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* ADC1 calibration voltage at atten3
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*/
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#define EFUSE_ADC1_CAL_VOL_ATTEN3 0x000001FFU
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#define EFUSE_ADC1_CAL_VOL_ATTEN3_M (EFUSE_ADC1_CAL_VOL_ATTEN3_V << EFUSE_ADC1_CAL_VOL_ATTEN3_S)
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#define EFUSE_ADC1_CAL_VOL_ATTEN3_V 0x000001FFU
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#define EFUSE_ADC1_CAL_VOL_ATTEN3_S 23
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/** EFUSE_RD_SYS_PART1_DATA7_REG register
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* Register $n of BLOCK2 (system).
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*/
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#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
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/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0;
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* Stores the seventh 32 bits of the first part of system data.
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/** EFUSE_ADC1_CAL_VOL_ATTEN3_1 : R; bitpos: [0]; default: 0;
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* ADC1 calibration voltage at atten3
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*/
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#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S)
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#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_7_S 0
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#define EFUSE_ADC1_CAL_VOL_ATTEN3_1 (BIT(0))
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#define EFUSE_ADC1_CAL_VOL_ATTEN3_1_M (EFUSE_ADC1_CAL_VOL_ATTEN3_1_V << EFUSE_ADC1_CAL_VOL_ATTEN3_1_S)
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#define EFUSE_ADC1_CAL_VOL_ATTEN3_1_V 0x00000001U
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#define EFUSE_ADC1_CAL_VOL_ATTEN3_1_S 0
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/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH0 : R; bitpos: [4:1]; default: 0;
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* ADC1 init code at atten0 ch0
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*/
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH0 0x0000000FU
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH0_M (EFUSE_ADC1_INIT_CODE_ATTEN0_CH0_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH0_S)
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH0_V 0x0000000FU
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH0_S 1
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/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH1 : R; bitpos: [8:5]; default: 0;
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* ADC1 init code at atten0 ch1
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*/
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH1 0x0000000FU
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH1_M (EFUSE_ADC1_INIT_CODE_ATTEN0_CH1_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH1_S)
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH1_V 0x0000000FU
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH1_S 5
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/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH2 : R; bitpos: [12:9]; default: 0;
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* ADC1 init code at atten0 ch2
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*/
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH2 0x0000000FU
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH2_M (EFUSE_ADC1_INIT_CODE_ATTEN0_CH2_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH2_S)
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH2_V 0x0000000FU
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH2_S 9
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/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH3 : R; bitpos: [16:13]; default: 0;
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* ADC1 init code at atten0 ch3
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*/
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH3 0x0000000FU
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH3_M (EFUSE_ADC1_INIT_CODE_ATTEN0_CH3_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH3_S)
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH3_V 0x0000000FU
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH3_S 13
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/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH4 : R; bitpos: [20:17]; default: 0;
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* ADC1 init code at atten0 ch4
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*/
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH4 0x0000000FU
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH4_M (EFUSE_ADC1_INIT_CODE_ATTEN0_CH4_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH4_S)
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH4_V 0x0000000FU
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH4_S 17
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/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH5 : R; bitpos: [24:21]; default: 0;
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* ADC1 init code at atten0 ch5
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*/
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH5 0x0000000FU
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH5_M (EFUSE_ADC1_INIT_CODE_ATTEN0_CH5_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH5_S)
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH5_V 0x0000000FU
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH5_S 21
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/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH6 : R; bitpos: [28:25]; default: 0;
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* ADC1 init code at atten0 ch6
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*/
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH6 0x0000000FU
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH6_M (EFUSE_ADC1_INIT_CODE_ATTEN0_CH6_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH6_S)
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH6_V 0x0000000FU
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#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH6_S 25
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/** EFUSE_RESERVED_2_253 : R; bitpos: [31:29]; default: 0;
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* reserved
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*/
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#define EFUSE_RESERVED_2_253 0x00000007U
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#define EFUSE_RESERVED_2_253_M (EFUSE_RESERVED_2_253_V << EFUSE_RESERVED_2_253_S)
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#define EFUSE_RESERVED_2_253_V 0x00000007U
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#define EFUSE_RESERVED_2_253_S 29
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/** EFUSE_RD_USR_DATA0_REG register
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* Register $n of BLOCK3 (user).
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@@ -639,10 +639,22 @@ typedef union {
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*/
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typedef union {
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struct {
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/** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0;
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* Stores the fourth 32 bits of the first part of system data.
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/** temp_calib : R; bitpos: [8:0]; default: 0;
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* Temperature calibration data
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*/
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uint32_t sys_data_part1_4:32;
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uint32_t temp_calib:9;
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/** ocode : R; bitpos: [16:9]; default: 0;
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* ADC OCode
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*/
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uint32_t ocode:8;
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/** adc1_init_code_atten0 : R; bitpos: [26:17]; default: 0;
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* ADC1 init code at atten0
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*/
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uint32_t adc1_init_code_atten0:10;
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/** adc1_init_code_atten1 : R; bitpos: [31:27]; default: 0;
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* ADC1 init code at atten1
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*/
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uint32_t adc1_init_code_atten1:5;
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};
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uint32_t val;
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} efuse_rd_sys_part1_data4_reg_t;
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@@ -652,10 +664,22 @@ typedef union {
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*/
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typedef union {
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struct {
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/** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0;
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* Stores the fifth 32 bits of the first part of system data.
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/** adc1_init_code_atten1_1 : R; bitpos: [4:0]; default: 0;
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* ADC1 init code at atten1
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*/
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uint32_t sys_data_part1_5:32;
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uint32_t adc1_init_code_atten1_1:5;
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/** adc1_init_code_atten2 : R; bitpos: [14:5]; default: 0;
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* ADC1 init code at atten2
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*/
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uint32_t adc1_init_code_atten2:10;
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/** adc1_init_code_atten3 : R; bitpos: [24:15]; default: 0;
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* ADC1 init code at atten3
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*/
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uint32_t adc1_init_code_atten3:10;
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/** adc1_cal_vol_atten0 : R; bitpos: [31:25]; default: 0;
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* ADC1 calibration voltage at atten0
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*/
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uint32_t adc1_cal_vol_atten0:7;
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};
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uint32_t val;
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} efuse_rd_sys_part1_data5_reg_t;
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@@ -665,10 +689,22 @@ typedef union {
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*/
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typedef union {
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struct {
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/** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0;
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* Stores the sixth 32 bits of the first part of system data.
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/** adc1_cal_vol_atten0_1 : R; bitpos: [2:0]; default: 0;
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* ADC1 calibration voltage at atten0
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*/
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uint32_t sys_data_part1_6:32;
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uint32_t adc1_cal_vol_atten0_1:3;
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/** adc1_cal_vol_atten1 : R; bitpos: [12:3]; default: 0;
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* ADC1 calibration voltage at atten1
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*/
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uint32_t adc1_cal_vol_atten1:10;
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/** adc1_cal_vol_atten2 : R; bitpos: [22:13]; default: 0;
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* ADC1 calibration voltage at atten2
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*/
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uint32_t adc1_cal_vol_atten2:10;
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/** adc1_cal_vol_atten3 : R; bitpos: [31:23]; default: 0;
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* ADC1 calibration voltage at atten3
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*/
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uint32_t adc1_cal_vol_atten3:9;
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};
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uint32_t val;
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} efuse_rd_sys_part1_data6_reg_t;
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@@ -678,10 +714,42 @@ typedef union {
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*/
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typedef union {
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struct {
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/** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0;
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* Stores the seventh 32 bits of the first part of system data.
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/** adc1_cal_vol_atten3_1 : R; bitpos: [0]; default: 0;
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* ADC1 calibration voltage at atten3
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*/
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uint32_t sys_data_part1_7:32;
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uint32_t adc1_cal_vol_atten3_1:1;
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/** adc1_init_code_atten0_ch0 : R; bitpos: [4:1]; default: 0;
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* ADC1 init code at atten0 ch0
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*/
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uint32_t adc1_init_code_atten0_ch0:4;
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/** adc1_init_code_atten0_ch1 : R; bitpos: [8:5]; default: 0;
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* ADC1 init code at atten0 ch1
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*/
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uint32_t adc1_init_code_atten0_ch1:4;
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/** adc1_init_code_atten0_ch2 : R; bitpos: [12:9]; default: 0;
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* ADC1 init code at atten0 ch2
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*/
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uint32_t adc1_init_code_atten0_ch2:4;
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/** adc1_init_code_atten0_ch3 : R; bitpos: [16:13]; default: 0;
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* ADC1 init code at atten0 ch3
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*/
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uint32_t adc1_init_code_atten0_ch3:4;
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/** adc1_init_code_atten0_ch4 : R; bitpos: [20:17]; default: 0;
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* ADC1 init code at atten0 ch4
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*/
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uint32_t adc1_init_code_atten0_ch4:4;
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/** adc1_init_code_atten0_ch5 : R; bitpos: [24:21]; default: 0;
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* ADC1 init code at atten0 ch5
|
||||
*/
|
||||
uint32_t adc1_init_code_atten0_ch5:4;
|
||||
/** adc1_init_code_atten0_ch6 : R; bitpos: [28:25]; default: 0;
|
||||
* ADC1 init code at atten0 ch6
|
||||
*/
|
||||
uint32_t adc1_init_code_atten0_ch6:4;
|
||||
/** reserved_2_253 : R; bitpos: [31:29]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t reserved_2_253:3;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data7_reg_t;
|
||||
|
||||
Reference in New Issue
Block a user