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fix(parlio_tx): add clock and fifo reset in disable function

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This commit is contained in:
Chen Jichang
2024-12-19 14:50:36 +08:00
parent 2c31596a3b
commit 0c2c142134
6 changed files with 39 additions and 21 deletions
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5
components/hal/esp32c5/include/hal/parlio_ll.h
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@@ -488,8 +488,11 @@ static inline void parlio_ll_tx_enable_clock_gating(parl_io_dev_t *dev, bool en)
/**
* @brief Start TX unit to transmit data
*
* @note The hardware monitors the rising edge of tx_start as the trigger signal.
* Once the transmission starts, it cannot be stopped by clearing tx_start.
*
* @param dev Parallel IO register base address
* @param en True to start, False to stop
* @param en True to start, False to reset the reg state (not meaning the TX unit will be stopped)
*/
__attribute__((always_inline))
static inline void parlio_ll_tx_start(parl_io_dev_t *dev, bool en)