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Merge branch 'refactor/cache_disable_enable_interface' into 'master'

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refactor(cache): abstract cache rom API in cache_ll.h

Closes IDF-7922

See merge request espressif/esp-idf!25040
This commit is contained in:
Gao Xu
2023-08-15 19:43:47 +08:00
parent 005640d12d fd759d65b0
commit 0ceb5f2648
9 changed files with 1331 additions and 172 deletions
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117
components/hal/esp32c3/include/hal/cache_ll.h
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@@ -13,6 +13,7 @@
#include "soc/ext_mem_defs.h"
#include "hal/cache_types.h"
#include "hal/assert.h"
#include "esp32c3/rom/cache.h"
#ifdef __cplusplus
extern "C" {
@@ -35,20 +36,120 @@ extern "C" {
#define CACHE_LL_L1_ILG_EVENT_PRELOAD_OP_FAULT (1<<1)
#define CACHE_LL_L1_ILG_EVENT_SYNC_OP_FAULT (1<<0)
#define CACHE_LL_L1_ICACHE_AUTOLOAD (1<<2)
/**
* @brief Get the status of cache if it is enabled or not
* @brief Check if Cache auto preload is enabled or not. On ESP32C3, instructions and data share Cache
*
* @param cache_id cache ID (when l1 cache is per core)
* @param type see `cache_type_t`
* @return enabled or not
* @param type see `cache_type_t`
*
* @return true: enabled; false: disabled
*/
__attribute__((always_inline))
static inline bool cache_ll_l1_is_cache_enabled(uint32_t cache_id, cache_type_t type)
static inline bool cache_ll_is_cache_autoload_enabled(cache_type_t type)
{
HAL_ASSERT(cache_id == 0);
(void) type; // On C3 there's only ICache
return REG_GET_BIT(EXTMEM_ICACHE_CTRL_REG, EXTMEM_ICACHE_ENABLE);
bool enabled = false;
if (REG_GET_BIT(EXTMEM_ICACHE_AUTOLOAD_CTRL_REG, EXTMEM_ICACHE_AUTOLOAD_ENA)) {
enabled = true;
}
return enabled;
}
/**
* @brief Disable Cache. On ESP32C3, instructions and data share Cache
*
* @param type see `cache_type_t`
*/
__attribute__((always_inline))
static inline void cache_ll_disable_cache(cache_type_t type)
{
(void) type;
Cache_Disable_ICache();
}
/**
* @brief Enable Cache. On ESP32C3, instructions and data share Cache
*
* @param type see `cache_type_t`
*
* @param data_autoload_en Dcache auto preload enabled
*
* @param inst_autoload_en Icache auto preload enabled
*/
__attribute__((always_inline))
static inline void cache_ll_enable_cache(cache_type_t type, bool inst_autoload_en, bool data_autoload_en)
{
Cache_Enable_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
}
/**
* @brief Suspend Cache. On ESP32C3, instructions and data share Cache
*
* @param type see `cache_type_t`
*/
__attribute__((always_inline))
static inline void cache_ll_suspend_cache(cache_type_t type)
{
Cache_Suspend_ICache();
}
/**
* @brief Resume Cache. On ESP32C3, instructions and data share Cache
*
* @param type see `cache_type_t`
*
* @param data_autoload_en Dcache auto preload enabled
*
* @param inst_autoload_en Icache auto preload enabled
*/
__attribute__((always_inline))
static inline void cache_ll_resume_cache(cache_type_t type, bool inst_autoload_en, bool data_autoload_en)
{
Cache_Resume_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
}
/**
* @brief Check if Cache is enabled or not. On ESP32C3, instructions and data share Cache
*
* @param type see `cache_type_t`
*
* @return true: enabled; false: disabled
*/
__attribute__((always_inline))
static inline bool cache_ll_is_cache_enabled(cache_type_t type)
{
bool enabled = false;
enabled = REG_GET_BIT(EXTMEM_ICACHE_CTRL_REG, EXTMEM_ICACHE_ENABLE);
return enabled;
}
/**
* @brief Invalidate cache supported addr
*
* Invalidate a Cache
*
* @param vaddr Start address of the region to be invalidated
* @param size Size of the region to be invalidated
*/
__attribute__((always_inline))
static inline void cache_ll_invalidate_addr(uint32_t vaddr, uint32_t size)
{
Cache_Invalidate_Addr(vaddr, size);
}
/**
* @brief Get Cache line size, in bytes
*
* @param type see `cache_type_t`
*
* @return Cache line size, in bytes
*/
__attribute__((always_inline))
static inline uint32_t cache_ll_get_line_size(cache_type_t type)
{
uint32_t size = 0;
size = Cache_Get_ICache_Line_Size();
return size;
}
/**