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efuse(esp32-c6): Update efuse_table and rs coding error func

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KonstantinKondrashov
2022-11-18 19:26:58 +08:00
parent 4867928160
commit 0eee228700
4 changed files with 65 additions and 60 deletions
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14
components/hal/esp32c6/efuse_hal.c
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@@ -78,17 +78,11 @@ bool efuse_hal_is_coding_error_in_block(unsigned block)
}
}
} else if (block <= 10) {
// The order of error in these regs is different only for the C3 chip.
// Fail bit (mask=0x8):
// EFUSE_RD_RS_ERR0_REG: (hi) BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1, ------ (low)
// EFUSE_RD_RS_ERR1_REG: BLOCK9, BLOCK8
// Error num bits (mask=0x7):
// EFUSE_RD_RS_ERR0_REG: (hi) BLOCK8, BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1 (low)
// EFUSE_RD_RS_ERR1_REG: BLOCK10, BLOCK9
// BLOCK10 is not presented in the error regs.
uint32_t err_fail_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + (block / 8) * 4);
uint32_t err_num_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + ((block - 1) / 8) * 4);
return (ESP_EFUSE_BLOCK_ERROR_BITS(err_fail_reg, block % 8) != 0) || (ESP_EFUSE_BLOCK_ERROR_NUM_BITS(err_num_reg, (block - 1) % 8) != 0);
// EFUSE_RD_RS_ERR1_REG: BLOCK10, BLOCK9
block--;
uint32_t error_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + (block / 8) * 4);
return ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block % 8) != 0;
}
return false;
}