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Merge branch 'feature/esp32c5_ledc_support' into 'master'

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feat(ledc): support ledc on esp32c5

Closes IDF-8684

See merge request espressif/esp-idf!30836
This commit is contained in:
Wan Lei
2024-05-27 17:43:12 +08:00
parent 7278d06c4f 33fa42ca74
commit 0fc3f68ff4
13 changed files with 2816 additions and 42 deletions
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28
components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in
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@@ -59,6 +59,10 @@ config SOC_GPSPI_SUPPORTED
bool
default y
config SOC_LEDC_SUPPORTED
bool
default y
config SOC_SYSTIMER_SUPPORTED
bool
default y
@@ -287,6 +291,26 @@ config SOC_LEDC_CHANNEL_NUM
int
default 6
config SOC_LEDC_TIMER_BIT_WIDTH
int
default 20
config SOC_LEDC_SUPPORT_FADE_STOP
bool
default y
config SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED
bool
default y
config SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX
int
default 16
config SOC_LEDC_FADE_PARAMS_BIT_WIDTH
int
default 10
config SOC_MMU_PERIPH_NUM
int
default 1
@@ -571,10 +595,6 @@ config SOC_PM_SUPPORT_RTC_PERIPH_PD
bool
default y
config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
bool
default y
config SOC_MODEM_CLOCK_IS_INDEPENDENT
bool
default y

2
components/soc/esp32c5/mp/include/soc/clk_tree_defs.h
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@@ -473,7 +473,7 @@ typedef enum { // TODO: [ESP32C5] IDF-8650 (inherit from C6)
/**
* @brief Type of LEDC clock source, reserved for the legacy LEDC driver
*/
typedef enum { // TODO: [ESP32C5] IDF-8684 (inherit from C6)
typedef enum {
LEDC_AUTO_CLK = 0, /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/
LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */

2120
components/soc/esp32c5/mp/include/soc/ledc_reg.h
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File diff suppressed because it is too large Load Diff

70
components/soc/esp32c5/mp/include/soc/ledc_struct.h
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@@ -20,38 +20,38 @@ typedef union {
* Configures which timer is channel n selected.\\0: Select timer0\\1: Select
* timer1\\2: Select timer2\\3: Select timer3
*/
uint32_t timer_sel_chn:2;
uint32_t timer_sel:2;
/** sig_out_en_chn : R/W; bitpos: [2]; default: 0;
* Configures whether or not to enable signal output on channel n.\\0: Signal output
* disable\\1: Signal output enable
*/
uint32_t sig_out_en_chn:1;
uint32_t sig_out_en:1;
/** idle_lv_chn : R/W; bitpos: [3]; default: 0;
* Configures the output value when channel n is inactive. Valid only when
* LEDC_SIG_OUT_EN_CHn is 0.\\0: Output level is low\\1: Output level is high
*/
uint32_t idle_lv_chn:1;
uint32_t idle_lv:1;
/** para_up_chn : WT; bitpos: [4]; default: 0;
* Configures whether or not to update LEDC_HPOINT_CHn, LEDC_DUTY_START_CHn,
* LEDC_SIG_OUT_EN_CHn, LEDC_TIMER_SEL_CHn, LEDC_OVF_CNT_EN_CHn fields and duty cycle
* range configuration for channel n, and will be automatically cleared by
* hardware.\\0: Invalid. No effect\\1: Update
*/
uint32_t para_up_chn:1;
uint32_t para_up:1;
/** ovf_num_chn : R/W; bitpos: [14:5]; default: 0;
* Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CHn_INT interrupt
* will be triggered when channel n overflows for (LEDC_OVF_NUM_CHn + 1) times.
*/
uint32_t ovf_num_chn:10;
uint32_t ovf_num:10;
/** ovf_cnt_en_chn : R/W; bitpos: [15]; default: 0;
* Configures whether or not to enable the ovf_cnt of channel n.\\0: Disable\\1: Enable
*/
uint32_t ovf_cnt_en_chn:1;
uint32_t ovf_cnt_en:1;
/** ovf_cnt_reset_chn : WT; bitpos: [16]; default: 0;
* Configures whether or not to reset the ovf_cnt of channel n.\\0: Invalid. No
* effect\\1: Reset the ovf_cnt
*/
uint32_t ovf_cnt_reset_chn:1;
uint32_t ovf_cnt_reset:1;
uint32_t reserved_17:15;
};
uint32_t val;
@@ -66,7 +66,7 @@ typedef union {
* Configures high point of signal output on channel n. The output value changes to
* high when the selected timers has reached the value specified by this register.
*/
uint32_t hpoint_chn:20;
uint32_t hpoint:20;
uint32_t reserved_20:12;
};
uint32_t val;
@@ -80,7 +80,7 @@ typedef union {
/** duty_chn : R/W; bitpos: [24:0]; default: 0;
* Configures the duty of signal output on channel n.
*/
uint32_t duty_chn:25;
uint32_t duty:25;
uint32_t reserved_25:7;
};
uint32_t val;
@@ -96,7 +96,7 @@ typedef union {
* Configures whether the duty cycle fading configurations take effect.\\0: Not take
* effect\\1: Take effect
*/
uint32_t duty_start_chn:1;
uint32_t duty_start:1;
};
uint32_t val;
} ledc_chn_conf1_reg_t;
@@ -109,30 +109,30 @@ typedef union {
/** timern_duty_res : R/W; bitpos: [4:0]; default: 0;
* Configures the bit width of the counter in timer n. Valid values are 1 to 20.
*/
uint32_t timern_duty_res:5;
uint32_t duty_res:5;
/** clk_div_timern : R/W; bitpos: [22:5]; default: 0;
* Configures the divisor for the divider in timer n.The least significant eight bits
* represent the fractional part.
*/
uint32_t clk_div_timern:18;
uint32_t clk_div:18;
/** timern_pause : R/W; bitpos: [23]; default: 0;
* Configures whether or not to pause the counter in timer n.\\0: Normal\\1: Pause
*/
uint32_t timern_pause:1;
uint32_t pause:1;
/** timern_rst : R/W; bitpos: [24]; default: 1;
* Configures whether or not to reset timer n. The counter will show 0 after
* reset.\\0: Not reset\\1: Reset
*/
uint32_t timern_rst:1;
uint32_t rst:1;
/** tick_sel_timern : R/W; bitpos: [25]; default: 0;
* Configures which clock is timer n selected. Unused.
*/
uint32_t tick_sel_timern:1;
uint32_t tick_sel:1;
/** timern_para_up : WT; bitpos: [26]; default: 0;
* Configures whether or not to update LEDC_CLK_DIV_TIMERn and
* LEDC_TIMERn_DUTY_RES.\\0: Invalid. No effect\\1: Update
*/
uint32_t timern_para_up:1;
uint32_t para_up:1;
uint32_t reserved_27:5;
};
uint32_t val;
@@ -146,17 +146,17 @@ typedef union {
/** chn_gamma_entry_num : R/W; bitpos: [4:0]; default: 0;
* Configures the number of duty cycle fading rages for LEDC chn.
*/
uint32_t chn_gamma_entry_num:5;
uint32_t gamma_entry_num:5;
/** chn_gamma_pause : WT; bitpos: [5]; default: 0;
* Configures whether or not to pause duty cycle fading of LEDC chn.\\0: Invalid. No
* effect\\1: Pause
*/
uint32_t chn_gamma_pause:1;
uint32_t gamma_pause:1;
/** chn_gamma_resume : WT; bitpos: [6]; default: 0;
* Configures whether or nor to resume duty cycle fading of LEDC chn.\\0: Invalid. No
* effect\\1: Resume
*/
uint32_t chn_gamma_resume:1;
uint32_t gamma_resume:1;
uint32_t reserved_7:25;
};
uint32_t val;
@@ -633,7 +633,7 @@ typedef union {
/** duty_chn_r : RO; bitpos: [24:0]; default: 0;
* Represents the current duty of output signal on channel n.
*/
uint32_t duty_chn_r:25;
uint32_t duty:25;
uint32_t reserved_25:7;
};
uint32_t val;
@@ -1020,9 +1020,9 @@ typedef union {
typedef struct {
volatile ledc_chn_conf0_reg_t conf0;
volatile ledc_chn_hpoint_reg_t hpoint;
volatile ledc_chn_duty_reg_t duty;
volatile ledc_chn_duty_reg_t duty_init;
volatile ledc_chn_conf1_reg_t conf1;
volatile ledc_chn_duty_r_reg_t duty_rd;
volatile ledc_chn_duty_r_reg_t duty_r;
} ledc_chn_reg_t;
typedef struct {
@@ -1072,10 +1072,36 @@ typedef struct {
volatile ledc_date_reg_t date;
} ledc_dev_t;
/**
* Gamma fade param group ram type
*/
typedef union {
struct {
uint32_t duty_inc :1;
uint32_t duty_cycle :10;
uint32_t scale :10;
uint32_t duty_num :10;
uint32_t reserved :1;
};
uint32_t val;
} ledc_channel_gamma_fade_param_t;
typedef struct {
volatile ledc_channel_gamma_fade_param_t entry[16];
} ledc_gamma_channel_t;
typedef struct {
volatile ledc_gamma_channel_t channel[6];
} ledc_gamma_ram_t;
extern ledc_dev_t LEDC;
extern ledc_gamma_ram_t LEDC_GAMMA_RAM;
#ifndef __cplusplus
_Static_assert(sizeof(ledc_dev_t) == 0x178, "Invalid size of ledc_dev_t structure");
_Static_assert(sizeof(ledc_gamma_ram_t) == 0x180, "Invalid size of ledc_gamma_ram_t structure");
#endif
#ifdef __cplusplus

15
components/soc/esp32c5/mp/include/soc/soc_caps.h
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@@ -42,7 +42,7 @@
#define SOC_RMT_SUPPORTED 1
// #define SOC_SDM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8687
#define SOC_GPSPI_SUPPORTED 1
// #define SOC_LEDC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8684
#define SOC_LEDC_SUPPORTED 1
// #define SOC_I2C_SUPPORTED 1 // TODO: [ESP32C5] IDF-8694, IDF-8696
#define SOC_SYSTIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8707
// #define SOC_AES_SUPPORTED 1 // TODO: [ESP32C5] IDF-8627
@@ -274,15 +274,14 @@
#define SOC_I2S_TDM_FULL_DATA_WIDTH (1) /*!< No limitation to data bit width when using multiple slots */
/*-------------------------- LEDC CAPS ---------------------------------------*/
// TODO: [ESP32C5] 8684
#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)
#define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
#define SOC_LEDC_CHANNEL_NUM (6)
// #define SOC_LEDC_TIMER_BIT_WIDTH (20)
// #define SOC_LEDC_SUPPORT_FADE_STOP (1)
// #define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1)
// #define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16)
// #define SOC_LEDC_FADE_PARAMS_BIT_WIDTH (10)
#define SOC_LEDC_TIMER_BIT_WIDTH (20)
#define SOC_LEDC_SUPPORT_FADE_STOP (1)
#define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1)
#define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16)
#define SOC_LEDC_FADE_PARAMS_BIT_WIDTH (10)
/*-------------------------- MMU CAPS ----------------------------------------*/
// TODO: [ESP32C5] IDF-8658
@@ -540,7 +539,7 @@
// #define SOC_PM_PAU_LINK_NUM (4)
/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
// #define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1) // TODO: IDF-8642
#define SOC_MODEM_CLOCK_IS_INDEPENDENT (1)
#define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */

1
components/soc/esp32c5/mp/ld/esp32c5.peripherals.ld
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@@ -13,6 +13,7 @@ PROVIDE ( UHCI = 0x60005000 );
PROVIDE ( RMT = 0x60006000 );
PROVIDE ( RMTMEM = 0x60006400 );
PROVIDE ( LEDC = 0x60007000 );
PROVIDE ( LEDC_GAMMA_RAM = 0x60007400 );
PROVIDE ( TIMERG0 = 0x60008000 );
PROVIDE ( TIMERG1 = 0x60009000 );
PROVIDE ( SYSTIMER = 0x6000A000 );

17
components/soc/esp32c5/mp/ledc_periph.c Normal file
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@@ -0,0 +1,17 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/ledc_periph.h"
#include "soc/gpio_sig_map.h"
/*
Bunch of constants for every LEDC peripheral: GPIO signals
*/
const ledc_signal_conn_t ledc_periph_signal[1] = {
{
.sig_out0_idx = LEDC_LS_SIG_OUT0_IDX,
}
};