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refactor(riscv): added a new API for the interrupts

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This commit is contained in:
Omar Chebib
2023-12-29 10:59:55 +08:00
parent 5cdf145f55
commit 102d5bbf72
46 changed files with 754 additions and 237 deletions
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2
components/freertos/FreeRTOS-Kernel/portable/riscv/port.c
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@@ -145,7 +145,7 @@ BaseType_t xPortStartScheduler(void)
/* Setup the hardware to generate the tick. */
vPortSetupTimer();
esprv_intc_int_set_threshold(RVHAL_INTR_ENABLE_THRESH); /* set global interrupt masking level */
esprv_int_set_threshold(RVHAL_INTR_ENABLE_THRESH); /* set global interrupt masking level */
rv_utils_intr_global_enable();
vPortYield();