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refactor(riscv): added a new API for the interrupts

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This commit is contained in:
Omar Chebib
2023-12-29 10:59:55 +08:00
parent 5cdf145f55
commit 102d5bbf72
46 changed files with 754 additions and 237 deletions
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4
components/freertos/test_apps/freertos/performance/test_isr_latency.c
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@@ -23,8 +23,8 @@
#define TEST_CLR_INT_MASK(mask) xt_set_intclear(mask)
#elif CONFIG_IDF_TARGET_ARCH_RISCV
#include "riscv/interrupt.h"
#define TEST_SET_INT_MASK(mask) esprv_intc_int_enable(mask)
#define TEST_CLR_INT_MASK(mask) esprv_intc_int_disable(mask)
#define TEST_SET_INT_MASK(mask) esprv_int_enable(mask)
#define TEST_CLR_INT_MASK(mask) esprv_int_disable(mask)
#endif
#ifndef __riscv // TODO: IDF-4416