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spi_flash: support working on differnt buses and frequency
This commit is contained in:
Michael (XIAO Xufeng)
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bot
bot
parent
ce4de867d6
commit
1036a091fe
39
components/soc/include/hal/esp_flash_err.h
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39
components/soc/include/hal/esp_flash_err.h
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <stdint.h>
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#include "esp_err.h"
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/*
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* Possible errors returned from esp flash internal functions, these error codes
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* should be consistent with esp_err_t codes. But in order to make the source
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* files less dependent to esp_err_t, they use the error codes defined in this
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* replacable header. This header should ensure the consistency to esp_err_t.
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*/
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/* These should be consistent with esp_err_t errors */
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#define ESP_ERR_FLASH_SIZE_NOT_MATCH ESP_ERR_INVALID_SIZE ///< The chip doesn't have enough space for the current partition table
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#define ESP_ERR_FLASH_NO_RESPONSE ESP_ERR_INVALID_RESPONSE ///< Chip did not respond to the command, or timed out.
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#define ESP_ERR_FLASH_ERR_BASE 0x6000 ///< Starting number of Flash error codes */
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//The ROM code has already taken 1 and 2, to avoid possible conflicts, start from 3.
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#define ESP_ERR_FLASH_NOT_INITIALISED (ESP_ERR_FLASH_ERR_BASE+3) ///< esp_flash_chip_t structure not correctly initialised by esp_flash_init().
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#define ESP_ERR_FLASH_UNSUPPORTED_HOST (ESP_ERR_FLASH_ERR_BASE+4) ///< Requested operation isn't supported via this host SPI bus (chip->spi field).
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#define ESP_ERR_FLASH_UNSUPPORTED_CHIP (ESP_ERR_FLASH_ERR_BASE+5) ///< Requested operation isn't supported by this model of SPI flash chip.
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#define ESP_ERR_FLASH_PROTECTED (ESP_ERR_FLASH_ERR_BASE+6) ///< Write operation failed due to chip's write protection being enabled.
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243
components/soc/include/hal/spi_flash_hal.h
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243
components/soc/include/hal/spi_flash_hal.h
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// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*******************************************************************************
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* NOTICE
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* The HAL is not public api, don't use in application code.
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* See readme.md in soc/include/hal/readme.md
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******************************************************************************/
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// The HAL layer for SPI Flash (common part)
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#pragma once
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#include "hal/spi_flash_ll.h"
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#include "hal/spi_flash_host_drv.h"
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#include "soc/soc_memory_layout.h"
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#define ESP_FLASH_DEFAULT_FREQ ESP_FLASH_20MHZ
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/* Hardware host-specific constants */
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#define SPI_FLASH_HAL_MAX_WRITE_BYTES 64
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#define SPI_FLASH_HAL_MAX_READ_BYTES 64
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///Lowest speed supported by the driver, currently 5 MHz
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#define ESP_FLASH_SPEED_MIN ESP_FLASH_5MHZ
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/**
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* @brief SPI flash clock speed values, always refer to them by the enum rather
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* than the actual value (more speed may be appended into the list).
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*
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* A strategy to select the maximum allowed speed is to enumerate from the
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* ``ESP_FLSH_SPEED_MAX-1`` or highest frequency supported by your flash, and
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* decrease the speed until the probing success.
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*/
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typedef enum {
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ESP_FLASH_5MHZ = 0, ///< The flash runs under 5MHz
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ESP_FLASH_10MHZ, ///< The flash runs under 10MHz
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ESP_FLASH_20MHZ, ///< The flash runs under 20MHz
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ESP_FLASH_26MHZ, ///< The flash runs under 26MHz
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ESP_FLASH_40MHZ, ///< The flash runs under 40MHz
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ESP_FLASH_80MHZ, ///< The flash runs under 80MHz
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ESP_FLASH_SPEED_MAX, ///< The maximum frequency supported by the host is ``ESP_FLASH_SPEED_MAX-1``.
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} esp_flash_speed_t;
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/**
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* Generic driver context structure for all chips using the SPI peripheral.
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* Include this into the HEAD of the driver data for other driver
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* implementations that also use the SPI peripheral.
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*/
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typedef struct {
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spi_dev_t *spi; ///< Pointer to SPI peripheral registers (SP1, SPI2 or SPI3). Set before initialisation.
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int cs_num; ///< Which cs pin is used, 0-2.
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int extra_dummy;
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spi_flash_ll_clock_reg_t clock_conf;
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} spi_flash_memspi_data_t;
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/// Configuration structure for the SPI driver.
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typedef struct {
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int host_id; ///< SPI peripheral ID, 1 for SPI1, 2 for SPI2 (HSPI), 3 for SPI3 (VSPI)
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int cs_num; ///< Which cs pin is used, 0-2.
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bool iomux; ///< Whether the IOMUX is used, used for timing compensation.
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int input_delay_ns; ///< Input delay on the MISO pin after the launch clock， used for timing compensation.
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esp_flash_speed_t speed;///< SPI flash clock speed to work at.
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} spi_flash_memspi_config_t;
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/**
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* Configure SPI flash hal settings.
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*
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* @param data Buffer to hold configured data, the buffer should be in DRAM to be available when cache disabled
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* @param cfg Configurations to set
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*
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* @return
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* - ESP_OK: success
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* - ESP_ERR_INVALID_ARG: the data buffer is not in the DRAM.
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*/
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esp_err_t spi_flash_hal_init(spi_flash_memspi_data_t *data_out, const spi_flash_memspi_config_t *cfg);
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/**
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* Configure the device-related register before transactions.
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*
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* @param driver The driver context.
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*
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* @return always return ESP_OK.
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*/
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esp_err_t spi_flash_hal_device_config(spi_flash_host_driver_t *driver);
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/**
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* Send an user-defined spi transaction to the device.
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*
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* @note This is usually used when the memspi interface doesn't support some
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* particular commands. Since this function supports timing compensation, it is
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* also used to receive some data when the frequency is high.
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*
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* @param driver The driver context.
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* @param trans The transaction to send, also holds the received data.
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*
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* @return always return ESP_OK.
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*/
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esp_err_t spi_flash_hal_common_command(spi_flash_host_driver_t *driver, spi_flash_trans_t *trans);
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/**
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* Erase whole flash chip.
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*
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* @param driver The driver context.
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*/
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void spi_flash_hal_erase_chip(spi_flash_host_driver_t *driver);
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/**
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* Erase a specific sector by its start address.
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*
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* @param driver The driver context.
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* @param start_address Start address of the sector to erase.
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*/
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void spi_flash_hal_erase_sector(spi_flash_host_driver_t *driver, uint32_t start_address);
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/**
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* Erase a specific block by its start address.
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*
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* @param driver The driver context.
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* @param start_address Start address of the block to erase.
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*/
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void spi_flash_hal_erase_block(spi_flash_host_driver_t *driver, uint32_t start_address);
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/**
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* Program a page of the flash.
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*
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* @param driver The driver context.
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* @param address Address of the page to program
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* @param buffer Data to program
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* @param length Size of the buffer in bytes, no larger than ``SPI_FLASH_HAL_MAX_WRITE_BYTES`` (64) bytes.
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*/
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void spi_flash_hal_program_page(spi_flash_host_driver_t *driver, const void *buffer, uint32_t address, uint32_t length);
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/**
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* Read from the flash. The read command should be set by ``spi_flash_hal_configure_host_read_mode`` before.
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*
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* @param driver The driver context.
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* @param buffer Buffer to store the read data
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* @param address Address to read
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* @param length Length to read, no larger than ``SPI_FLASH_HAL_MAX_READ_BYTES`` (64) bytes.
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*
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* @return always return ESP_OK.
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*/
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esp_err_t spi_flash_hal_read(spi_flash_host_driver_t *driver, void *buffer, uint32_t address, uint32_t read_len);
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/**
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* Enable or disable the write protection of the flash chip.
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*
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* @param driver The driver context.
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* @param wp true to enable the write protection, otherwise false.
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*
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* @return always return ESP_OK.
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*/
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esp_err_t spi_flash_hal_set_write_protect(spi_flash_host_driver_t *chip_drv, bool wp);
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/**
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* Check whether the SPI host is idle and can perform other operations.
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*
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* @param driver The driver context.
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*
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* @return ture if idle, otherwise false.
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*/
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bool spi_flash_hal_host_idle(spi_flash_host_driver_t *driver);
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/**
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* Configure the SPI host hardware registers for the specified read mode.
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*
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* Note that calling this configures SPI host registers, so if running any
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* other commands as part of set_read_mode() then these must be run before
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* calling this function.
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*
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* @param driver The driver context
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* @param read_mode The HW read mode to use
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* @param addr_bitlen Length of the address phase, in bits
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* @param dummy_cyclelen_base Base cycles of the dummy phase, some extra dummy cycles may be appended to compensate the timing.
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* @param read_command Actual reading command to send to flash chip on the bus.
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*
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* @return always return ESP_OK.
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*/
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esp_err_t spi_flash_hal_configure_host_read_mode(spi_flash_host_driver_t *driver, esp_flash_read_mode_t read_mode,
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uint32_t addr_bitlen, uint32_t dummy_cyclelen_base,
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uint32_t read_command);
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/**
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* Poll until the last operation is done.
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*
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* @param driver The driver context.
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*/
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void spi_flash_hal_poll_cmd_done(spi_flash_host_driver_t *driver);
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/**
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* Check whether the given buffer can be used as the write buffer directly. If 'chip' is connected to the main SPI bus, we can only write directly from
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* regions that are accessible ith cache disabled. *
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*
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* @param driver The driver context
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* @param p The buffer holding data to send.
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*
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* @return True if the buffer can be used to send data, otherwise false.
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*/
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static inline bool spi_flash_hal_supports_direct_write(spi_flash_host_driver_t *driver, const void *p)
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{
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#ifdef ESP_PLATFORM
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bool direct_write = ( ((spi_flash_memspi_data_t *)driver->driver_data)->spi != &SPI1
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|| esp_ptr_in_dram(p) );
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#else
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//If it is not on real chips, there is no limitation that the data has to be in DRAM.
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bool direct_write = true;
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#endif
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return direct_write;
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}
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/**
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* Check whether the given buffer can be used as the read buffer directly. If 'chip' is connected to the main SPI bus, we can only read directly from
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* regions that are accessible ith cache disabled. *
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*
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* @param driver The driver context
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* @param p The buffer to hold the received data.
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*
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* @return True if the buffer can be used to receive data, otherwise false.
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*/
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static inline bool spi_flash_hal_supports_direct_read(spi_flash_host_driver_t *driver, const void *p)
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{
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#ifdef ESP_PLATFORM
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//currently the driver doesn't support to read through DMA, no word-aligned requirements
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bool direct_read = ( ((spi_flash_memspi_data_t *)driver->driver_data)->spi != &SPI1
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|| esp_ptr_in_dram(p) );
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#else
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//If it is not on real chips, there is no limitation that the data has to be in DRAM.
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bool direct_read = true;
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#endif
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return direct_read;
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}
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112
components/soc/include/hal/spi_flash_host_drv.h
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112
components/soc/include/hal/spi_flash_host_drv.h
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@@ -0,0 +1,112 @@
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// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include "hal/spi_flash_ll.h"
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#include "hal/esp_flash_err.h"
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/** Definition of a common transaction. Also holds the return value. */
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typedef struct {
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uint8_t command; ///< Command to send, always 8bits
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uint8_t mosi_len; ///< Output data length, in bits
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uint8_t miso_len; ///< Input data length, in bits
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uint32_t mosi_data; ///< Output data to slave
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uint32_t miso_data[2]; ///< [out] Input data from slave, little endian
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} spi_flash_trans_t;
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struct spi_flash_host_driver_t;
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typedef struct spi_flash_host_driver_t spi_flash_host_driver_t;
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/** Host driver configuration and context structure. */
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struct spi_flash_host_driver_t {
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/**
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* Configuration and static data used by the specific host driver. The type
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* is determined by the host driver.
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*/
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void *driver_data;
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/**
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* Configure the device-related register before transactions. This saves
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* some time to re-configure those registers when we send continuously
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*/
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esp_err_t (*dev_config)(spi_flash_host_driver_t *driver);
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/**
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* Send an user-defined spi transaction to the device.
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*/
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esp_err_t (*common_command)(spi_flash_host_driver_t *driver, spi_flash_trans_t *t);
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/**
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* Read flash ID.
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*/
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esp_err_t (*read_id)(spi_flash_host_driver_t *driver, uint32_t *id);
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/**
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* Erase whole flash chip.
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*/
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void (*erase_chip)(spi_flash_host_driver_t *driver);
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/**
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* Erase a specific sector by its start address.
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*/
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void (*erase_sector)(spi_flash_host_driver_t *driver, uint32_t start_address);
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/**
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* Erase a specific block by its start address.
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*/
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void (*erase_block)(spi_flash_host_driver_t *driver, uint32_t start_address);
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/**
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* Read the status of the flash chip.
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*/
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esp_err_t (*read_status)(spi_flash_host_driver_t *driver, uint8_t *out_sr);
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/**
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* Disable write protection.
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*/
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esp_err_t (*set_write_protect)(spi_flash_host_driver_t *driver, bool wp);
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/**
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* Program a page of the flash. Check ``max_write_bytes`` for the maximum allowed writing length.
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*/
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void (*program_page)(spi_flash_host_driver_t *driver, const void *buffer, uint32_t address, uint32_t length);
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/** Check whether need to allocate new buffer to write */
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bool (*supports_direct_write)(spi_flash_host_driver_t *driver, const void *p);
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/** Check whether need to allocate new buffer to read */
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bool (*supports_direct_read)(spi_flash_host_driver_t *driver, const void *p);
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/** maximum length of program_page */
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int max_write_bytes;
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/**
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* Read data from the flash. Check ``max_read_bytes`` for the maximum allowed reading length.
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*/
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esp_err_t (*read)(spi_flash_host_driver_t *driver, void *buffer, uint32_t address, uint32_t read_len);
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/** maximum length of read */
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int max_read_bytes;
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/**
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* Check whether the host is idle to perform new operations.
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*/
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bool (*host_idle)(spi_flash_host_driver_t *driver);
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/**
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* Configure the host to work at different read mode.
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*/
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esp_err_t (*configure_host_read_mode)(spi_flash_host_driver_t *driver, esp_flash_read_mode_t read_mode, uint32_t addr_bitlen, uint32_t dummy_bitlen_base, uint32_t read_command);
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/**
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* Internal use, poll the HW until the last operation is done.
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*/
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void (*poll_cmd_done)(spi_flash_host_driver_t *driver);
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/**
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* For some host (SPI1), they are shared with a cache. When the data is
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* modified, the cache needs to be flushed. Left NULL if not supported.
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*/
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esp_err_t (*flush_cache)(spi_flash_host_driver_t* driver, uint32_t addr, uint32_t size);
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/**
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* Check if the given region is protected (e.g. is the bootloader). Left
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* NULL if current host doesn't need protection.
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*/
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bool (*region_protected)(spi_flash_host_driver_t* driver, uint32_t addr, uint32_t size);
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};
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