mirror of
https://github.com/espressif/esp-idf.git
synced 2025-08-11 13:00:19 +00:00
rename APB_CTRL ro SYS_CON
save
This commit is contained in:
Wu Zheng Hui
committed by
Jiang Jiang Jian
Jiang Jiang Jian
parent
b59902f4d1
commit
1080e4f6a2
@@ -13,6 +13,8 @@
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_SYSCON_STRUCT_H_
|
||||
#define _SOC_SYSCON_STRUCT_H_
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@@ -21,304 +23,310 @@ extern "C" {
|
||||
typedef volatile struct syscon_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t apb_ctrl_pre_div_cnt: 10;
|
||||
uint32_t apb_ctrl_clk_320m_en: 1;
|
||||
uint32_t clk_en: 1;
|
||||
uint32_t apb_ctrl_rst_tick_cnt: 1;
|
||||
uint32_t reserved13: 19;
|
||||
uint32_t pre_div : 10;
|
||||
uint32_t clk_320m_en : 1;
|
||||
uint32_t clk_en : 1;
|
||||
uint32_t rst_tick : 1;
|
||||
uint32_t reserved13 : 19;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_ctrl_sysclk_conf;
|
||||
} clk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t apb_ctrl_xtal_tick_num: 8;
|
||||
uint32_t apb_ctrl_ck8m_tick_num: 8;
|
||||
uint32_t apb_ctrl_tick_enable: 1;
|
||||
uint32_t reserved17: 15;
|
||||
uint32_t xtal_tick : 8;
|
||||
uint32_t ck8m_tick : 8;
|
||||
uint32_t tick_enable : 1;
|
||||
uint32_t reserved17 : 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_ctrl_tick_conf;
|
||||
} tick_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk20_oen: 1;
|
||||
uint32_t clk22_oen: 1;
|
||||
uint32_t clk44_oen: 1;
|
||||
uint32_t clk_bb_oen: 1;
|
||||
uint32_t clk80_oen: 1;
|
||||
uint32_t clk160_oen: 1;
|
||||
uint32_t clk_320m_oen: 1;
|
||||
uint32_t clk_adc_inf_oen: 1;
|
||||
uint32_t clk_dac_cpu_oen: 1;
|
||||
uint32_t clk40x_bb_oen: 1;
|
||||
uint32_t clk_xtal_oen: 1;
|
||||
uint32_t reserved11: 21;
|
||||
uint32_t clk20_oen : 1;
|
||||
uint32_t clk22_oen : 1;
|
||||
uint32_t clk44_oen : 1;
|
||||
uint32_t clk_bb_oen : 1;
|
||||
uint32_t clk80_oen : 1;
|
||||
uint32_t clk160_oen : 1;
|
||||
uint32_t clk_320m_oen : 1;
|
||||
uint32_t clk_adc_inf_oen : 1;
|
||||
uint32_t clk_dac_cpu_oen : 1;
|
||||
uint32_t clk40x_bb_oen : 1;
|
||||
uint32_t clk_xtal_oen : 1;
|
||||
uint32_t reserved11 : 21;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_ctrl_clk_out_en;
|
||||
uint32_t wifi_bb_cfg; /**/
|
||||
uint32_t wifi_bb_cfg_2; /**/
|
||||
uint32_t wifi_clk_en; /**/
|
||||
uint32_t wifi_rst_en; /**/
|
||||
} clk_out_en;
|
||||
uint32_t wifi_bb_cfg;
|
||||
uint32_t wifi_bb_cfg_2;
|
||||
uint32_t wifi_clk_en;
|
||||
uint32_t wifi_rst_en;
|
||||
union {
|
||||
struct {
|
||||
uint32_t peri_io_swap: 8;
|
||||
uint32_t reserved8: 24;
|
||||
uint32_t peri_io_swap : 8;
|
||||
uint32_t reserved8 : 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} host_inf_sel;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ext_mem_pms_lock: 1;
|
||||
uint32_t reserved1: 31;
|
||||
uint32_t ext_mem_pms_lock : 1;
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ext_mem_pms_lock;
|
||||
union {
|
||||
struct {
|
||||
uint32_t writeback_bypass: 1; /*Set 1 to bypass cache writeback request to external memory so that spi will not check its attribute.*/
|
||||
uint32_t reserved1: 31;
|
||||
uint32_t writeback_bypass : 1; /*Set 1 to bypass cache writeback request to external memory so that spi will not check its attribute.*/
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ext_mem_writeback_bypass;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace0_attr: 9;
|
||||
uint32_t reserved9: 23;
|
||||
uint32_t flash_ace0_attr : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace0_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace1_attr: 9;
|
||||
uint32_t reserved9: 23;
|
||||
uint32_t flash_ace1_attr : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace1_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace2_attr: 9;
|
||||
uint32_t reserved9: 23;
|
||||
uint32_t flash_ace2_attr : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace2_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace3_attr: 9;
|
||||
uint32_t reserved9: 23;
|
||||
uint32_t flash_ace3_attr : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace3_attr;
|
||||
uint32_t flash_ace0_addr; /**/
|
||||
uint32_t flash_ace1_addr; /**/
|
||||
uint32_t flash_ace2_addr; /**/
|
||||
uint32_t flash_ace3_addr; /**/
|
||||
uint32_t flash_ace0_addr;
|
||||
uint32_t flash_ace1_addr;
|
||||
uint32_t flash_ace2_addr;
|
||||
uint32_t flash_ace3_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace0_size:16;
|
||||
uint32_t reserved16: 16;
|
||||
uint32_t flash_ace0_size : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace0_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace1_size:16;
|
||||
uint32_t reserved16: 16;
|
||||
uint32_t flash_ace1_size : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace1_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace2_size:16;
|
||||
uint32_t reserved16: 16;
|
||||
uint32_t flash_ace2_size : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace2_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace3_size:16;
|
||||
uint32_t reserved16: 16;
|
||||
uint32_t flash_ace3_size : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace3_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace0_attr: 9;
|
||||
uint32_t reserved9: 23;
|
||||
uint32_t sram_ace0_attr : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace0_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace1_attr: 9;
|
||||
uint32_t reserved9: 23;
|
||||
uint32_t sram_ace1_attr : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace1_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace2_attr: 9;
|
||||
uint32_t reserved9: 23;
|
||||
uint32_t sram_ace2_attr : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace2_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace3_attr: 9;
|
||||
uint32_t reserved9: 23;
|
||||
uint32_t sram_ace3_attr : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace3_attr;
|
||||
uint32_t sram_ace0_addr; /**/
|
||||
uint32_t sram_ace1_addr; /**/
|
||||
uint32_t sram_ace2_addr; /**/
|
||||
uint32_t sram_ace3_addr; /**/
|
||||
uint32_t sram_ace0_addr;
|
||||
uint32_t sram_ace1_addr;
|
||||
uint32_t sram_ace2_addr;
|
||||
uint32_t sram_ace3_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace0_size:16;
|
||||
uint32_t reserved16: 16;
|
||||
uint32_t sram_ace0_size : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace0_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace1_size:16;
|
||||
uint32_t reserved16: 16;
|
||||
uint32_t sram_ace1_size : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace1_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace2_size:16;
|
||||
uint32_t reserved16: 16;
|
||||
uint32_t sram_ace2_size : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace2_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace3_size:16;
|
||||
uint32_t reserved16: 16;
|
||||
uint32_t sram_ace3_size : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace3_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t spi_mem_reject_int: 1;
|
||||
uint32_t spi_mem_reject_clr: 1;
|
||||
uint32_t spi_mem_reject_cde: 5;
|
||||
uint32_t reserved7: 25;
|
||||
uint32_t spi_mem_reject_int : 1;
|
||||
uint32_t spi_mem_reject_clr : 1;
|
||||
uint32_t spi_mem_reject_cde : 5;
|
||||
uint32_t reserved7 : 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} spi_mem_pms_ctrl;
|
||||
uint32_t spi_mem_reject_addr; /**/
|
||||
uint32_t spi_mem_reject_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sdio_win_access_en: 1;
|
||||
uint32_t reserved1: 31;
|
||||
uint32_t sdio_win_access_en : 1;
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_ctrl_sdio_ctrl;
|
||||
} sdio_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t redcy_sig0: 31;
|
||||
uint32_t redcy_andor: 1;
|
||||
uint32_t redcy_sig0 : 31;
|
||||
uint32_t redcy_andor : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} redcy_sig0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t redcy_sig1: 31;
|
||||
uint32_t redcy_nandor: 1;
|
||||
uint32_t redcy_sig1 : 31;
|
||||
uint32_t redcy_nandor : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} redcy_sig1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t agc_mem_force_pu: 1;
|
||||
uint32_t agc_mem_force_pd: 1;
|
||||
uint32_t pbus_mem_force_pu: 1;
|
||||
uint32_t pbus_mem_force_pd: 1;
|
||||
uint32_t dc_mem_force_pu: 1;
|
||||
uint32_t dc_mem_force_pd: 1;
|
||||
uint32_t freq_mem_force_pu: 1;
|
||||
uint32_t freq_mem_force_pd: 1;
|
||||
uint32_t reserved8: 24;
|
||||
uint32_t agc_mem_force_pu : 1;
|
||||
uint32_t agc_mem_force_pd : 1;
|
||||
uint32_t pbus_mem_force_pu : 1;
|
||||
uint32_t pbus_mem_force_pd : 1;
|
||||
uint32_t dc_mem_force_pu : 1;
|
||||
uint32_t dc_mem_force_pd : 1;
|
||||
uint32_t freq_mem_force_pu : 1;
|
||||
uint32_t freq_mem_force_pd : 1;
|
||||
uint32_t reserved8 : 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} front_end_mem_pd;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 18; /*reserved*/
|
||||
uint32_t flash_page_size: 2; /*Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
|
||||
uint32_t sram_page_size: 2; /*Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
|
||||
uint32_t reserved22: 10; /*reserved*/
|
||||
uint32_t reserved0 : 18; /*reserved*/
|
||||
uint32_t flash_page_size : 2; /*Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
|
||||
uint32_t sram_page_size : 2; /*Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
|
||||
uint32_t reserved22 : 10; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} spi_mem_ecc_ctrl;
|
||||
uint32_t reserved_a4;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rom_clkgate_force_on: 3;
|
||||
uint32_t sram_clkgate_force_on:11;
|
||||
uint32_t reserved14: 18;
|
||||
uint32_t rom_clkgate_force_on : 3;
|
||||
uint32_t sram_clkgate_force_on : 11;
|
||||
uint32_t reserved14 : 18;
|
||||
};
|
||||
uint32_t val;
|
||||
} clkgate_force_on;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rom_power_down: 3;
|
||||
uint32_t sram_power_down:11;
|
||||
uint32_t reserved14: 18;
|
||||
uint32_t rom_power_down : 3;
|
||||
uint32_t sram_power_down : 11;
|
||||
uint32_t reserved14 : 18;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_power_down;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rom_power_up: 3;
|
||||
uint32_t sram_power_up:11;
|
||||
uint32_t reserved14: 18;
|
||||
uint32_t rom_power_up : 3;
|
||||
uint32_t sram_power_up : 11;
|
||||
uint32_t reserved14 : 18;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_power_up;
|
||||
union {
|
||||
struct {
|
||||
uint32_t retention_cpu_link_addr:27;
|
||||
uint32_t nobypass_cpu_iso_rst: 1;
|
||||
uint32_t reserved28: 4;
|
||||
uint32_t retention_cpu_link_addr : 27;
|
||||
uint32_t nobypass_cpu_iso_rst : 1;
|
||||
uint32_t reserved28 : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} retention_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t retention_tag_link_addr:27;
|
||||
uint32_t reserved27: 5;
|
||||
uint32_t retention_tag_link_addr : 27;
|
||||
uint32_t reserved27 : 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} retention_ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 4;
|
||||
uint32_t ret_icache_size: 8;
|
||||
uint32_t reserved12: 1;
|
||||
uint32_t ret_icache_vld_size: 8;
|
||||
uint32_t reserved21: 1;
|
||||
uint32_t ret_icache_start_point: 8;
|
||||
uint32_t reserved30: 1;
|
||||
uint32_t ret_icache_enable: 1;
|
||||
uint32_t reserved0 : 4;
|
||||
uint32_t ret_icache_size : 8;
|
||||
uint32_t reserved12 : 1;
|
||||
uint32_t ret_icache_vld_size : 8;
|
||||
uint32_t reserved21 : 1;
|
||||
uint32_t ret_icache_start_point : 8;
|
||||
uint32_t reserved30 : 1;
|
||||
uint32_t ret_icache_enable : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} retention_ctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 4;
|
||||
uint32_t ret_dcache_size: 9;
|
||||
uint32_t ret_dcache_vld_size: 9;
|
||||
uint32_t ret_dcache_start_point: 9;
|
||||
uint32_t ret_dcache_enable: 1;
|
||||
uint32_t reserved0 : 4;
|
||||
uint32_t ret_dcache_size : 9;
|
||||
uint32_t ret_dcache_vld_size : 9;
|
||||
uint32_t ret_dcache_start_point : 9;
|
||||
uint32_t ret_dcache_enable : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} retention_ctrl3;
|
||||
uint32_t reserved_c4;
|
||||
uint32_t reserved_c8;
|
||||
uint32_t retention_ctrl4;
|
||||
union {
|
||||
struct {
|
||||
uint32_t retention_disable : 1;
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} retention_ctrl5;
|
||||
uint32_t reserved_cc;
|
||||
uint32_t reserved_d0;
|
||||
uint32_t reserved_d4;
|
||||
@@ -523,11 +531,13 @@ typedef volatile struct syscon_dev_s {
|
||||
uint32_t reserved_3f0;
|
||||
uint32_t reserved_3f4;
|
||||
uint32_t reserved_3f8;
|
||||
uint32_t apb_ctrl_date; /*Version control*/
|
||||
uint32_t date;
|
||||
} syscon_dev_t;
|
||||
extern syscon_dev_t SYSCON;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_SYSCON_STRUCT_H_ */
|
||||
|
||||
|
||||
#endif /*_SOC_SYSCON_STRUCT_H_ */
|
||||
|
||||
Reference in New Issue
Block a user