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feat(xip_psram): support xip psram feature on esp32p4

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This commit is contained in:
Armando
2024-05-10 16:11:39 +08:00
parent 862aca1fcc
commit 10d3912c70
51 changed files with 965 additions and 158 deletions
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3
components/hal/esp32p4/clk_tree_hal.c
View File

@@ -4,6 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "esp_attr.h"
#include "hal/clk_tree_hal.h"
#include "hal/clk_tree_ll.h"
#include "hal/assert.h"
@@ -70,7 +71,7 @@ uint32_t clk_hal_lp_slow_get_freq_hz(void)
}
}
uint32_t clk_hal_xtal_get_freq_mhz(void)
IRAM_ATTR uint32_t clk_hal_xtal_get_freq_mhz(void)
{
uint32_t freq = clk_ll_xtal_load_freq_mhz();
if (freq == 0) {

26
components/hal/esp32p4/include/hal/ldo_ll.h
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@@ -42,17 +42,6 @@ extern "C" {
#define LDO_LL_EXT_LDO_MUL_VOL_BASE 1000
#define LDO_LL_EXT_LDO_MUL_VOL_STEP 250
/**
* Trick to be adapted to the LDO register structure
*
* In pmu_ext_ldo_info_t ext_ldo[6] registers:
* - ext_ldo[0] is LDO1
* - ext_ldo[3] is LDO2
* - ext_ldo[1] is LDO3
* - ext_ldo[4] is LDO4
*/
#define LDO_ID2INDEX(id) (uint8_t[]){0,3,1,4}[id]
/**
* LDO ID to real unit ID
*/
@@ -79,8 +68,8 @@ __attribute__((always_inline))
static inline void ldo_ll_enable(int ldo_id, bool enable)
{
HAL_ASSERT(ldo_id < LDO_LL_UNIT_NUM);
PMU.ext_ldo[LDO_ID2INDEX(ldo_id)].pmu_ext_ldo.xpd = enable;
uint8_t index_array[LDO_LL_UNIT_NUM] = {0,3,1,4};
PMU.ext_ldo[index_array[ldo_id]].pmu_ext_ldo.xpd = enable;
}
/**
@@ -138,11 +127,12 @@ static inline void ldo_ll_set_output_voltage_mv(int ldo_id, int voltage_mv)
* - 0: efuse
* - 1: tieh_sel
*/
PMU.ext_ldo[LDO_ID2INDEX(ldo_id)].pmu_ext_ldo.tieh_sel = 0;
PMU.ext_ldo[LDO_ID2INDEX(ldo_id)].pmu_ext_ldo.tieh = 0;
PMU.ext_ldo[LDO_ID2INDEX(ldo_id)].pmu_ext_ldo.force_tieh_sel = 1;
PMU.ext_ldo[LDO_ID2INDEX(ldo_id)].pmu_ext_ldo_ana.dref = dref;
PMU.ext_ldo[LDO_ID2INDEX(ldo_id)].pmu_ext_ldo_ana.mul = mul;
uint8_t index_array[LDO_LL_UNIT_NUM] = {0,3,1,4};
PMU.ext_ldo[index_array[ldo_id]].pmu_ext_ldo.tieh_sel = 0;
PMU.ext_ldo[index_array[ldo_id]].pmu_ext_ldo.tieh = 0;
PMU.ext_ldo[index_array[ldo_id]].pmu_ext_ldo.force_tieh_sel = 1;
PMU.ext_ldo[index_array[ldo_id]].pmu_ext_ldo_ana.dref = dref;
PMU.ext_ldo[index_array[ldo_id]].pmu_ext_ldo_ana.mul = mul;
}
#ifdef __cplusplus

9
components/hal/esp32p4/include/hal/mmu_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -20,11 +20,12 @@
extern "C" {
#endif
///< MMU is per target
#define MMU_LL_MMU_PER_TARGET 1
#define MMU_LL_FLASH_MMU_ID 0
#define MMU_LL_PSRAM_MMU_ID 1
#define MMU_LL_FLASH_VADDR_TO_PSRAM_VADDR(flash_vaddr) ((flash_vaddr) + SOC_IRAM_FLASH_PSRAM_OFFSET)
#define MMU_LL_PSRAM_VADDR_TO_FLASH_VADDR(psram_vaddr) ((psram_vaddr) - SOC_IRAM_FLASH_PSRAM_OFFSET)
#define MMU_LL_END_DROM_ENTRY_VADDR (SOC_DRAM_FLASH_ADDRESS_HIGH - SOC_MMU_PAGE_SIZE)
#define MMU_LL_END_DROM_ENTRY_ID (SOC_MMU_ENTRY_NUM - 1)
/**
* Convert MMU virtual address to linear address