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feat(xip_psram): support xip psram feature on esp32p4
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@@ -42,17 +42,6 @@ extern "C" {
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#define LDO_LL_EXT_LDO_MUL_VOL_BASE 1000
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#define LDO_LL_EXT_LDO_MUL_VOL_STEP 250
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/**
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* Trick to be adapted to the LDO register structure
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*
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* In pmu_ext_ldo_info_t ext_ldo[6] registers:
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* - ext_ldo[0] is LDO1
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* - ext_ldo[3] is LDO2
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* - ext_ldo[1] is LDO3
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* - ext_ldo[4] is LDO4
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*/
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#define LDO_ID2INDEX(id) (uint8_t[]){0,3,1,4}[id]
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/**
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* LDO ID to real unit ID
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*/
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@@ -79,8 +68,8 @@ __attribute__((always_inline))
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static inline void ldo_ll_enable(int ldo_id, bool enable)
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{
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HAL_ASSERT(ldo_id < LDO_LL_UNIT_NUM);
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PMU.ext_ldo[LDO_ID2INDEX(ldo_id)].pmu_ext_ldo.xpd = enable;
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uint8_t index_array[LDO_LL_UNIT_NUM] = {0,3,1,4};
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PMU.ext_ldo[index_array[ldo_id]].pmu_ext_ldo.xpd = enable;
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}
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/**
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@@ -138,11 +127,12 @@ static inline void ldo_ll_set_output_voltage_mv(int ldo_id, int voltage_mv)
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* - 0: efuse
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* - 1: tieh_sel
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*/
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PMU.ext_ldo[LDO_ID2INDEX(ldo_id)].pmu_ext_ldo.tieh_sel = 0;
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PMU.ext_ldo[LDO_ID2INDEX(ldo_id)].pmu_ext_ldo.tieh = 0;
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PMU.ext_ldo[LDO_ID2INDEX(ldo_id)].pmu_ext_ldo.force_tieh_sel = 1;
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PMU.ext_ldo[LDO_ID2INDEX(ldo_id)].pmu_ext_ldo_ana.dref = dref;
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PMU.ext_ldo[LDO_ID2INDEX(ldo_id)].pmu_ext_ldo_ana.mul = mul;
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uint8_t index_array[LDO_LL_UNIT_NUM] = {0,3,1,4};
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PMU.ext_ldo[index_array[ldo_id]].pmu_ext_ldo.tieh_sel = 0;
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PMU.ext_ldo[index_array[ldo_id]].pmu_ext_ldo.tieh = 0;
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PMU.ext_ldo[index_array[ldo_id]].pmu_ext_ldo.force_tieh_sel = 1;
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PMU.ext_ldo[index_array[ldo_id]].pmu_ext_ldo_ana.dref = dref;
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PMU.ext_ldo[index_array[ldo_id]].pmu_ext_ldo_ana.mul = mul;
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}
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#ifdef __cplusplus
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