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esp32s2: put static .data and .bss directly after .iram.text
This results in a single large heap section instead of two smaller ones. Closes IDF-1354
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@@ -26,16 +26,16 @@
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#define RAM_IRAM_START 0x40020000
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#define RAM_DRAM_START 0x3FFB0000
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#define DATA_RAM_END 0x3FFF0000 /* start address of bootloader */
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#define DATA_RAM_END 0x3FFE4000 /* 2nd stage bootloader iram_loader_seg starts at block 15 */
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#define IRAM_ORG (RAM_IRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \
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+ CONFIG_ESP32S2_DATA_CACHE_SIZE)
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#define IRAM_SIZE 0x18000
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#define DRAM_ORG (RAM_DRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \
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+ CONFIG_ESP32S2_DATA_CACHE_SIZE \
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+ IRAM_SIZE)
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#define DRAM_SIZE DATA_RAM_END - DRAM_ORG
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+ CONFIG_ESP32S2_DATA_CACHE_SIZE)
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#define I_D_RAM_SIZE DATA_RAM_END - DRAM_ORG
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MEMORY
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{
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@@ -44,7 +44,7 @@ MEMORY
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are connected to the data port of the CPU and eg allow bytewise access. */
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/* IRAM for CPU.*/
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iram0_0_seg (RX) : org = IRAM_ORG, len = IRAM_SIZE
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iram0_0_seg (RX) : org = IRAM_ORG, len = I_D_RAM_SIZE
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#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/* Even though the segment name is iram, it is actually mapped to flash
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@@ -62,7 +62,7 @@ MEMORY
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/* Shared data RAM, excluding memory reserved for bootloader and ROM bss/data/stack. */
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dram0_0_seg (RW) : org = DRAM_ORG, len = DRAM_SIZE
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dram0_0_seg (RW) : org = DRAM_ORG, len = I_D_RAM_SIZE
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#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/* Flash mapped constant data */
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