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soc: update the csv headers for esp32s3
This commit is contained in:
Cao Sen Miao
@@ -1,4 +1,4 @@
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// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
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// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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@@ -11,398 +11,399 @@
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#ifndef _SOC_ASSIST_DEBUG_STRUCT_H_
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#define _SOC_ASSIST_DEBUG_STRUCT_H_
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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typedef volatile struct {
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union {
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struct {
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uint32_t core_0_area_dram0_0_rd_ena: 1;
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uint32_t core_0_area_dram0_0_wr_ena: 1;
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uint32_t core_0_area_dram0_1_rd_ena: 1;
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uint32_t core_0_area_dram0_1_wr_ena: 1;
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uint32_t core_0_area_pif_0_rd_ena: 1;
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uint32_t core_0_area_pif_0_wr_ena: 1;
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uint32_t core_0_area_pif_1_rd_ena: 1;
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uint32_t core_0_area_pif_1_wr_ena: 1;
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uint32_t core_0_sp_spill_min_ena: 1;
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uint32_t core_0_sp_spill_max_ena: 1;
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uint32_t core_0_iram0_exception_monitor_ena: 1;
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uint32_t core_0_dram0_exception_monitor_ena: 1;
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uint32_t reserved12: 20;
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uint32_t core_0_area_dram0_0_rd : 1;
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uint32_t core_0_area_dram0_0_wr : 1;
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uint32_t core_0_area_dram0_1_rd : 1;
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uint32_t core_0_area_dram0_1_wr : 1;
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uint32_t core_0_area_pif_0_rd : 1;
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uint32_t core_0_area_pif_0_wr : 1;
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uint32_t core_0_area_pif_1_rd : 1;
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uint32_t core_0_area_pif_1_wr : 1;
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uint32_t core_0_sp_spill_min : 1;
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uint32_t core_0_sp_spill_max : 1;
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uint32_t core_0_iram0_exception_monitor: 1;
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uint32_t core_0_dram0_exception_monitor: 1;
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uint32_t reserved12 : 20;
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};
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uint32_t val;
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} core_0_interrupt_ena;
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union {
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struct {
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uint32_t core_0_area_dram0_0_rd_raw: 1;
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uint32_t core_0_area_dram0_0_wr_raw: 1;
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uint32_t core_0_area_dram0_1_rd_raw: 1;
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uint32_t core_0_area_dram0_1_wr_raw: 1;
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uint32_t core_0_area_pif_0_rd_raw: 1;
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uint32_t core_0_area_pif_0_wr_raw: 1;
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uint32_t core_0_area_pif_1_rd_raw: 1;
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uint32_t core_0_area_pif_1_wr_raw: 1;
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uint32_t core_0_sp_spill_min_raw: 1;
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uint32_t core_0_sp_spill_max_raw: 1;
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uint32_t core_0_iram0_exception_monitor_raw: 1;
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uint32_t core_0_dram0_exception_monitor_raw: 1;
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uint32_t reserved12: 20;
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uint32_t core_0_area_dram0_0_rd : 1;
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uint32_t core_0_area_dram0_0_wr : 1;
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uint32_t core_0_area_dram0_1_rd : 1;
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uint32_t core_0_area_dram0_1_wr : 1;
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uint32_t core_0_area_pif_0_rd : 1;
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uint32_t core_0_area_pif_0_wr : 1;
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uint32_t core_0_area_pif_1_rd : 1;
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uint32_t core_0_area_pif_1_wr : 1;
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uint32_t core_0_sp_spill_min : 1;
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uint32_t core_0_sp_spill_max : 1;
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uint32_t core_0_iram0_exception_monitor: 1;
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uint32_t core_0_dram0_exception_monitor: 1;
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uint32_t reserved12 : 20;
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};
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uint32_t val;
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} core_0_interrupt_raw;
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union {
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struct {
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uint32_t core_0_area_dram0_0_rd_rls: 1;
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uint32_t core_0_area_dram0_0_wr_rls: 1;
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uint32_t core_0_area_dram0_1_rd_rls: 1;
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uint32_t core_0_area_dram0_1_wr_rls: 1;
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uint32_t core_0_area_pif_0_rd_rls: 1;
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uint32_t core_0_area_pif_0_wr_rls: 1;
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uint32_t core_0_area_pif_1_rd_rls: 1;
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uint32_t core_0_area_pif_1_wr_rls: 1;
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uint32_t core_0_sp_spill_min_rls: 1;
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uint32_t core_0_sp_spill_max_rls: 1;
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uint32_t core_0_iram0_exception_monitor_rls: 1;
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uint32_t core_0_dram0_exception_monitor_rls: 1;
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uint32_t reserved12: 20;
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uint32_t core_0_area_dram0_0_rd : 1;
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uint32_t core_0_area_dram0_0_wr : 1;
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uint32_t core_0_area_dram0_1_rd : 1;
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uint32_t core_0_area_dram0_1_wr : 1;
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uint32_t core_0_area_pif_0_rd : 1;
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uint32_t core_0_area_pif_0_wr : 1;
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uint32_t core_0_area_pif_1_rd : 1;
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uint32_t core_0_area_pif_1_wr : 1;
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uint32_t core_0_sp_spill_min : 1;
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uint32_t core_0_sp_spill_max : 1;
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uint32_t core_0_iram0_exception_monitor: 1;
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uint32_t core_0_dram0_exception_monitor: 1;
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uint32_t reserved12 : 20;
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};
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uint32_t val;
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} core_0_interrupt_rls;
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union {
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struct {
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uint32_t core_0_area_dram0_0_rd_clr: 1;
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uint32_t core_0_area_dram0_0_wr_clr: 1;
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uint32_t core_0_area_dram0_1_rd_clr: 1;
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uint32_t core_0_area_dram0_1_wr_clr: 1;
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uint32_t core_0_area_pif_0_rd_clr: 1;
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uint32_t core_0_area_pif_0_wr_clr: 1;
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uint32_t core_0_area_pif_1_rd_clr: 1;
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uint32_t core_0_area_pif_1_wr_clr: 1;
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uint32_t core_0_sp_spill_min_clr: 1;
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uint32_t core_0_sp_spill_max_clr: 1;
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uint32_t core_0_iram0_exception_monitor_clr: 1;
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uint32_t core_0_dram0_exception_monitor_clr: 1;
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uint32_t reserved12: 20;
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uint32_t core_0_area_dram0_0_rd : 1;
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uint32_t core_0_area_dram0_0_wr : 1;
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uint32_t core_0_area_dram0_1_rd : 1;
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uint32_t core_0_area_dram0_1_wr : 1;
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uint32_t core_0_area_pif_0_rd : 1;
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uint32_t core_0_area_pif_0_wr : 1;
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uint32_t core_0_area_pif_1_rd : 1;
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uint32_t core_0_area_pif_1_wr : 1;
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uint32_t core_0_sp_spill_min : 1;
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uint32_t core_0_sp_spill_max : 1;
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uint32_t core_0_iram0_exception_monitor: 1;
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uint32_t core_0_dram0_exception_monitor: 1;
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uint32_t reserved12 : 20;
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};
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uint32_t val;
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} core_0_interrupt_clr;
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uint32_t core_0_area_dram0_0_min; /**/
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uint32_t core_0_area_dram0_0_max; /**/
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uint32_t core_0_area_dram0_1_min; /**/
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uint32_t core_0_area_dram0_1_max; /**/
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uint32_t core_0_area_pif_0_min; /**/
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uint32_t core_0_area_pif_0_max; /**/
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uint32_t core_0_area_pif_1_min; /**/
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uint32_t core_0_area_pif_1_max; /**/
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uint32_t core_0_area_sp; /**/
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uint32_t core_0_area_pc; /**/
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uint32_t core_0_area_dram0_0_min;
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uint32_t core_0_area_dram0_0_max;
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uint32_t core_0_area_dram0_1_min;
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uint32_t core_0_area_dram0_1_max;
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uint32_t core_0_area_pif_0_min;
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uint32_t core_0_area_pif_0_max;
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uint32_t core_0_area_pif_1_min;
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uint32_t core_0_area_pif_1_max;
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uint32_t core_0_area_sp;
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uint32_t core_0_area_pc;
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union {
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struct {
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uint32_t core_0_sp_unstable: 8;
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uint32_t reserved8: 24;
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uint32_t core_0_sp_unstable : 8;
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uint32_t reserved8 : 24;
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};
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uint32_t val;
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} core_0_sp_unstable;
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uint32_t core_0_sp_min; /**/
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uint32_t core_0_sp_max; /**/
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uint32_t core_0_sp_pc; /**/
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uint32_t core_0_sp_min;
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uint32_t core_0_sp_max;
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uint32_t core_0_sp_pc;
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union {
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struct {
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uint32_t core_0_rcd_pdebugenable: 1;
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uint32_t reserved1: 31;
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uint32_t core_0_rcd_pdebugenable : 1;
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uint32_t reserved1 : 31;
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};
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uint32_t val;
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} core_0_rcd_pdebugenable;
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union {
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struct {
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uint32_t core_0_rcd_recording: 1;
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uint32_t reserved1: 31;
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uint32_t core_0_rcd_recording : 1;
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uint32_t reserved1 : 31;
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};
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uint32_t val;
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} core_0_rcd_recording;
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uint32_t core_0_rcd_pdebuginst; /**/
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uint32_t core_0_rcd_pdebuginst;
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union {
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struct {
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uint32_t core_0_rcd_pdebugstatus: 8;
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uint32_t reserved8: 24;
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uint32_t core_0_rcd_pdebugstatus : 8;
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uint32_t reserved8 : 24;
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};
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uint32_t val;
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} core_0_rcd_pdebugstatus;
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uint32_t core_0_rcd_pdebugdata; /**/
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uint32_t core_0_rcd_pdebugpc; /**/
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uint32_t core_0_rcd_pdebugls0stat; /**/
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uint32_t core_0_rcd_pdebugls0addr; /**/
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uint32_t core_0_rcd_pdebugls0data; /**/
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uint32_t core_0_rcd_sp; /**/
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uint32_t core_0_rcd_pdebugdata;
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uint32_t core_0_rcd_pdebugpc;
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uint32_t core_0_rcd_pdebugls0stat;
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uint32_t core_0_rcd_pdebugls0addr;
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uint32_t core_0_rcd_pdebugls0data;
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uint32_t core_0_rcd_sp;
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union {
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struct {
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uint32_t core_0_iram0_recording_addr_0: 24;
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uint32_t core_0_iram0_recording_wr_0: 1;
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uint32_t core_0_iram0_recording_loadstore_0: 1;
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uint32_t reserved26: 6;
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uint32_t core_0_iram0_recording_addr_0 : 24;
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uint32_t core_0_iram0_recording_wr_0 : 1;
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uint32_t core_0_iram0_recording_loadstore_0: 1;
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uint32_t reserved26 : 6;
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};
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uint32_t val;
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} core_0_iram0_exception_monitor_0;
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union {
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struct {
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uint32_t core_0_iram0_recording_addr_1: 24;
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uint32_t core_0_iram0_recording_wr_1: 1;
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uint32_t core_0_iram0_recording_loadstore_1: 1;
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uint32_t reserved26: 6;
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uint32_t core_0_iram0_recording_addr_1 : 24;
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uint32_t core_0_iram0_recording_wr_1 : 1;
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uint32_t core_0_iram0_recording_loadstore_1: 1;
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uint32_t reserved26 : 6;
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};
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uint32_t val;
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} core_0_iram0_exception_monitor_1;
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union {
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struct {
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uint32_t core_0_dram0_recording_addr_0: 22;
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uint32_t core_0_dram0_recording_wr_0: 1;
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uint32_t reserved23: 9;
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uint32_t core_0_dram0_recording_addr_0 : 22;
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uint32_t core_0_dram0_recording_wr_0 : 1;
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uint32_t reserved23 : 9;
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};
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uint32_t val;
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} core_0_dram0_exception_monitor_0;
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union {
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struct {
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uint32_t core_0_dram0_recording_byteen_0: 16;
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uint32_t reserved16: 16;
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uint32_t core_0_dram0_recording_byteen_0: 16;
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uint32_t reserved16 : 16;
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};
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uint32_t val;
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} core_0_dram0_exception_monitor_1;
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uint32_t core_0_dram0_exception_monitor_2; /**/
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uint32_t core_0_dram0_exception_monitor_2;
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union {
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struct {
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uint32_t core_0_dram0_recording_addr_1: 22;
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uint32_t core_0_dram0_recording_wr_1: 1;
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uint32_t reserved23: 9;
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uint32_t core_0_dram0_recording_addr_1 : 22;
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uint32_t core_0_dram0_recording_wr_1 : 1;
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uint32_t reserved23 : 9;
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};
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uint32_t val;
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} core_0_dram0_exception_monitor_3;
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union {
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struct {
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uint32_t core_0_dram0_recording_byteen_1: 16;
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uint32_t reserved16: 16;
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uint32_t core_0_dram0_recording_byteen_1: 16;
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uint32_t reserved16 : 16;
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};
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uint32_t val;
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} core_0_dram0_exception_monitor_4;
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uint32_t core_0_dram0_exception_monitor_5; /**/
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uint32_t core_0_dram0_exception_monitor_5;
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union {
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struct {
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uint32_t core_1_area_dram0_0_rd_ena: 1;
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uint32_t core_1_area_dram0_0_wr_ena: 1;
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uint32_t core_1_area_dram0_1_rd_ena: 1;
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uint32_t core_1_area_dram0_1_wr_ena: 1;
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uint32_t core_1_area_pif_0_rd_ena: 1;
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uint32_t core_1_area_pif_0_wr_ena: 1;
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uint32_t core_1_area_pif_1_rd_ena: 1;
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uint32_t core_1_area_pif_1_wr_ena: 1;
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uint32_t core_1_sp_spill_min_ena: 1;
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uint32_t core_1_sp_spill_max_ena: 1;
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uint32_t core_1_iram0_exception_monitor_ena: 1;
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uint32_t core_1_dram0_exception_monitor_ena: 1;
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uint32_t reserved12: 20;
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uint32_t core_1_area_dram0_0_rd : 1;
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uint32_t core_1_area_dram0_0_wr : 1;
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uint32_t core_1_area_dram0_1_rd : 1;
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uint32_t core_1_area_dram0_1_wr : 1;
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uint32_t core_1_area_pif_0_rd : 1;
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uint32_t core_1_area_pif_0_wr : 1;
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uint32_t core_1_area_pif_1_rd : 1;
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uint32_t core_1_area_pif_1_wr : 1;
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uint32_t core_1_sp_spill_min : 1;
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uint32_t core_1_sp_spill_max : 1;
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uint32_t core_1_iram0_exception_monitor: 1;
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uint32_t core_1_dram0_exception_monitor: 1;
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uint32_t reserved12 : 20;
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};
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uint32_t val;
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} core_1_interrupt_ena;
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union {
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struct {
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uint32_t core_1_area_dram0_0_rd_raw: 1;
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uint32_t core_1_area_dram0_0_wr_raw: 1;
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uint32_t core_1_area_dram0_1_rd_raw: 1;
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uint32_t core_1_area_dram0_1_wr_raw: 1;
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uint32_t core_1_area_pif_0_rd_raw: 1;
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uint32_t core_1_area_pif_0_wr_raw: 1;
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uint32_t core_1_area_pif_1_rd_raw: 1;
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uint32_t core_1_area_pif_1_wr_raw: 1;
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uint32_t core_1_sp_spill_min_raw: 1;
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uint32_t core_1_sp_spill_max_raw: 1;
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uint32_t core_1_iram0_exception_monitor_raw: 1;
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uint32_t core_1_dram0_exception_monitor_raw: 1;
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uint32_t reserved12: 20;
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uint32_t core_1_area_dram0_0_rd : 1;
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uint32_t core_1_area_dram0_0_wr : 1;
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uint32_t core_1_area_dram0_1_rd : 1;
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uint32_t core_1_area_dram0_1_wr : 1;
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uint32_t core_1_area_pif_0_rd : 1;
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uint32_t core_1_area_pif_0_wr : 1;
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uint32_t core_1_area_pif_1_rd : 1;
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uint32_t core_1_area_pif_1_wr : 1;
|
||||
uint32_t core_1_sp_spill_min : 1;
|
||||
uint32_t core_1_sp_spill_max : 1;
|
||||
uint32_t core_1_iram0_exception_monitor: 1;
|
||||
uint32_t core_1_dram0_exception_monitor: 1;
|
||||
uint32_t reserved12 : 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_interrupt_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_area_dram0_0_rd_rls: 1;
|
||||
uint32_t core_1_area_dram0_0_wr_rls: 1;
|
||||
uint32_t core_1_area_dram0_1_rd_rls: 1;
|
||||
uint32_t core_1_area_dram0_1_wr_rls: 1;
|
||||
uint32_t core_1_area_pif_0_rd_rls: 1;
|
||||
uint32_t core_1_area_pif_0_wr_rls: 1;
|
||||
uint32_t core_1_area_pif_1_rd_rls: 1;
|
||||
uint32_t core_1_area_pif_1_wr_rls: 1;
|
||||
uint32_t core_1_sp_spill_min_rls: 1;
|
||||
uint32_t core_1_sp_spill_max_rls: 1;
|
||||
uint32_t core_1_iram0_exception_monitor_rls: 1;
|
||||
uint32_t core_1_dram0_exception_monitor_rls: 1;
|
||||
uint32_t reserved12: 20;
|
||||
uint32_t core_1_area_dram0_0_rd : 1;
|
||||
uint32_t core_1_area_dram0_0_wr : 1;
|
||||
uint32_t core_1_area_dram0_1_rd : 1;
|
||||
uint32_t core_1_area_dram0_1_wr : 1;
|
||||
uint32_t core_1_area_pif_0_rd : 1;
|
||||
uint32_t core_1_area_pif_0_wr : 1;
|
||||
uint32_t core_1_area_pif_1_rd : 1;
|
||||
uint32_t core_1_area_pif_1_wr : 1;
|
||||
uint32_t core_1_sp_spill_min : 1;
|
||||
uint32_t core_1_sp_spill_max : 1;
|
||||
uint32_t core_1_iram0_exception_monitor: 1;
|
||||
uint32_t core_1_dram0_exception_monitor: 1;
|
||||
uint32_t reserved12 : 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_interrupt_rls;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_area_dram0_0_rd_clr: 1;
|
||||
uint32_t core_1_area_dram0_0_wr_clr: 1;
|
||||
uint32_t core_1_area_dram0_1_rd_clr: 1;
|
||||
uint32_t core_1_area_dram0_1_wr_clr: 1;
|
||||
uint32_t core_1_area_pif_0_rd_clr: 1;
|
||||
uint32_t core_1_area_pif_0_wr_clr: 1;
|
||||
uint32_t core_1_area_pif_1_rd_clr: 1;
|
||||
uint32_t core_1_area_pif_1_wr_clr: 1;
|
||||
uint32_t core_1_sp_spill_min_clr: 1;
|
||||
uint32_t core_1_sp_spill_max_clr: 1;
|
||||
uint32_t core_1_iram0_exception_monitor_clr: 1;
|
||||
uint32_t core_1_dram0_exception_monitor_clr: 1;
|
||||
uint32_t reserved12: 20;
|
||||
uint32_t core_1_area_dram0_0_rd : 1;
|
||||
uint32_t core_1_area_dram0_0_wr : 1;
|
||||
uint32_t core_1_area_dram0_1_rd : 1;
|
||||
uint32_t core_1_area_dram0_1_wr : 1;
|
||||
uint32_t core_1_area_pif_0_rd : 1;
|
||||
uint32_t core_1_area_pif_0_wr : 1;
|
||||
uint32_t core_1_area_pif_1_rd : 1;
|
||||
uint32_t core_1_area_pif_1_wr : 1;
|
||||
uint32_t core_1_sp_spill_min : 1;
|
||||
uint32_t core_1_sp_spill_max : 1;
|
||||
uint32_t core_1_iram0_exception_monitor: 1;
|
||||
uint32_t core_1_dram0_exception_monitor: 1;
|
||||
uint32_t reserved12 : 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_interrupt_clr;
|
||||
uint32_t core_1_area_dram0_0_min; /**/
|
||||
uint32_t core_1_area_dram0_0_max; /**/
|
||||
uint32_t core_1_area_dram0_1_min; /**/
|
||||
uint32_t core_1_area_dram0_1_max; /**/
|
||||
uint32_t core_1_area_pif_0_min; /**/
|
||||
uint32_t core_1_area_pif_0_max; /**/
|
||||
uint32_t core_1_area_pif_1_min; /**/
|
||||
uint32_t core_1_area_pif_1_max; /**/
|
||||
uint32_t core_1_area_pc; /**/
|
||||
uint32_t core_1_area_sp; /**/
|
||||
uint32_t core_1_area_dram0_0_min;
|
||||
uint32_t core_1_area_dram0_0_max;
|
||||
uint32_t core_1_area_dram0_1_min;
|
||||
uint32_t core_1_area_dram0_1_max;
|
||||
uint32_t core_1_area_pif_0_min;
|
||||
uint32_t core_1_area_pif_0_max;
|
||||
uint32_t core_1_area_pif_1_min;
|
||||
uint32_t core_1_area_pif_1_max;
|
||||
uint32_t core_1_area_pc;
|
||||
uint32_t core_1_area_sp;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_sp_unstable: 8;
|
||||
uint32_t reserved8: 24;
|
||||
uint32_t core_1_sp_unstable : 8;
|
||||
uint32_t reserved8 : 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_sp_unstable;
|
||||
uint32_t core_1_sp_min; /**/
|
||||
uint32_t core_1_sp_max; /**/
|
||||
uint32_t core_1_sp_pc; /**/
|
||||
uint32_t core_1_sp_min;
|
||||
uint32_t core_1_sp_max;
|
||||
uint32_t core_1_sp_pc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_rcd_pdebugenable: 1;
|
||||
uint32_t reserved1: 31;
|
||||
uint32_t core_1_rcd_pdebugenable : 1;
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_rcd_pdebugenable;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_rcd_recording: 1;
|
||||
uint32_t reserved1: 31;
|
||||
uint32_t core_1_rcd_recording : 1;
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_rcd_recording;
|
||||
uint32_t core_1_rcd_pdebuginst; /**/
|
||||
uint32_t core_1_rcd_pdebuginst;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_rcd_pdebugstatus: 8;
|
||||
uint32_t reserved8: 24;
|
||||
uint32_t core_1_rcd_pdebugstatus : 8;
|
||||
uint32_t reserved8 : 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_rcd_pdebugstatus;
|
||||
uint32_t core_1_rcd_pdebugdata; /**/
|
||||
uint32_t core_1_rcd_pdebugpc; /**/
|
||||
uint32_t core_1_rcd_pdebugls0stat; /**/
|
||||
uint32_t core_1_rcd_pdebugls0addr; /**/
|
||||
uint32_t core_1_rcd_pdebugls0data; /**/
|
||||
uint32_t core_1_rcd_sp; /**/
|
||||
uint32_t core_1_rcd_pdebugdata;
|
||||
uint32_t core_1_rcd_pdebugpc;
|
||||
uint32_t core_1_rcd_pdebugls0stat;
|
||||
uint32_t core_1_rcd_pdebugls0addr;
|
||||
uint32_t core_1_rcd_pdebugls0data;
|
||||
uint32_t core_1_rcd_sp;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_iram0_recording_addr_0: 24;
|
||||
uint32_t core_1_iram0_recording_wr_0: 1;
|
||||
uint32_t core_1_iram0_recording_loadstore_0: 1;
|
||||
uint32_t reserved26: 6;
|
||||
uint32_t core_1_iram0_recording_addr_0 : 24;
|
||||
uint32_t core_1_iram0_recording_wr_0 : 1;
|
||||
uint32_t core_1_iram0_recording_loadstore_0: 1;
|
||||
uint32_t reserved26 : 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_iram0_exception_monitor_0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_iram0_recording_addr_1: 24;
|
||||
uint32_t core_1_iram0_recording_wr_1: 1;
|
||||
uint32_t core_1_iram0_recording_loadstore_1: 1;
|
||||
uint32_t reserved26: 6;
|
||||
uint32_t core_1_iram0_recording_addr_1 : 24;
|
||||
uint32_t core_1_iram0_recording_wr_1 : 1;
|
||||
uint32_t core_1_iram0_recording_loadstore_1: 1;
|
||||
uint32_t reserved26 : 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_iram0_exception_monitor_1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_dram0_recording_addr_0: 22;
|
||||
uint32_t core_1_dram0_recording_wr_0: 1;
|
||||
uint32_t reserved23: 9;
|
||||
uint32_t core_1_dram0_recording_addr_0 : 22;
|
||||
uint32_t core_1_dram0_recording_wr_0 : 1;
|
||||
uint32_t reserved23 : 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_dram0_exception_monitor_0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_dram0_recording_byteen_0: 16;
|
||||
uint32_t reserved16: 16;
|
||||
uint32_t core_1_dram0_recording_byteen_0: 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_dram0_exception_monitor_1;
|
||||
uint32_t core_1_dram0_exception_monitor_2; /**/
|
||||
uint32_t core_1_dram0_exception_monitor_2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_dram0_recording_addr_1: 22;
|
||||
uint32_t core_1_dram0_recording_wr_1: 1;
|
||||
uint32_t reserved23: 9;
|
||||
uint32_t core_1_dram0_recording_addr_1 : 22;
|
||||
uint32_t core_1_dram0_recording_wr_1 : 1;
|
||||
uint32_t reserved23 : 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_dram0_exception_monitor_3;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_dram0_recording_byteen_1: 16;
|
||||
uint32_t reserved16: 16;
|
||||
uint32_t core_1_dram0_recording_byteen_1: 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_dram0_exception_monitor_4;
|
||||
uint32_t core_1_dram0_exception_monitor_5; /**/
|
||||
uint32_t core_1_dram0_exception_monitor_5;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_x_iram0_dram0_limit_cycle_0: 20;
|
||||
uint32_t reserved20: 12;
|
||||
uint32_t core_x_iram0_dram0_limit_cycle_0: 20;
|
||||
uint32_t reserved20 : 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_x_iram0_dram0_exception_monitor_0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_x_iram0_dram0_limit_cycle_1: 20;
|
||||
uint32_t reserved20: 12;
|
||||
uint32_t core_x_iram0_dram0_limit_cycle_1: 20;
|
||||
uint32_t reserved20 : 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_x_iram0_dram0_exception_monitor_1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t log_ena: 3;
|
||||
uint32_t log_mode: 3;
|
||||
uint32_t log_mem_loop_enable: 1;
|
||||
uint32_t reserved7: 25;
|
||||
uint32_t log : 3;
|
||||
uint32_t log_mode : 3;
|
||||
uint32_t log_mem_loopble : 1;
|
||||
uint32_t reserved7 : 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} log_setting;
|
||||
uint32_t log_data_0; /**/
|
||||
uint32_t log_data_1; /**/
|
||||
uint32_t log_data_2; /**/
|
||||
uint32_t log_data_3; /**/
|
||||
uint32_t log_data_0;
|
||||
uint32_t log_data_1;
|
||||
uint32_t log_data_2;
|
||||
uint32_t log_data_3;
|
||||
union {
|
||||
struct {
|
||||
uint32_t log_data_size: 16;
|
||||
uint32_t reserved16: 16;
|
||||
uint32_t log_data_size : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} log_data_mask;
|
||||
uint32_t log_min; /**/
|
||||
uint32_t log_max; /**/
|
||||
uint32_t log_mem_start; /**/
|
||||
uint32_t log_mem_end; /**/
|
||||
uint32_t log_mem_writing_addr; /**/
|
||||
uint32_t log_min;
|
||||
uint32_t log_max;
|
||||
uint32_t log_mem_start;
|
||||
uint32_t log_mem_end;
|
||||
uint32_t log_mem_writing_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t log_mem_full_flag: 1;
|
||||
uint32_t reserved1: 31;
|
||||
uint32_t log_mem_full_flag : 1;
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} log_mem_full_flag;
|
||||
@@ -449,15 +450,17 @@ typedef volatile struct {
|
||||
uint32_t reserved_1f8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date: 28;
|
||||
uint32_t reserved28: 4;
|
||||
uint32_t assist_debug_reg_date : 28;
|
||||
uint32_t reserved28 : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} reg_date;
|
||||
} assist_debug_dev_t;
|
||||
|
||||
extern assist_debug_dev_t ASSIST_DEBUG;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_ASSIST_DEBUG_STRUCT_H_ */
|
||||
|
||||
Reference in New Issue
Block a user