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soc: update the csv headers for esp32s3

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This commit is contained in:
Cao Sen Miao
2021-06-09 18:42:54 +08:00
parent 0c8a495be0
commit 11672dc9e5
82 changed files with 12272 additions and 11264 deletions
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36
components/soc/esp32s3/include/soc/sensitive_reg.h
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@@ -1,4 +1,4 @@
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -15,10 +15,10 @@
#define _SOC_SENSITIVE_REG_H_
#include "soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define SENSITIVE_CACHE_DATAARRAY_CONNECT_0_REG (DR_REG_SENSITIVE_BASE + 0x0)
/* SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
@@ -1663,12 +1663,6 @@ extern "C" {
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V 0x3
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S 14
/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
/*description: .*/
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V 0x3
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S 12
/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
/*description: .*/
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE 0x00000003
@@ -2007,12 +2001,6 @@ extern "C" {
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V 0x3
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S 14
/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
/*description: .*/
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER 0x00000003
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S))
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V 0x3
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S 12
/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
/*description: .*/
#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE 0x00000003
@@ -2877,12 +2865,6 @@ extern "C" {
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S))
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V 0x3
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S 14
/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
/*description: .*/
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER 0x00000003
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S))
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V 0x3
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S 12
/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
/*description: .*/
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE 0x00000003
@@ -3221,12 +3203,6 @@ extern "C" {
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S))
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V 0x3
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S 14
/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
/*description: .*/
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER 0x00000003
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S))
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V 0x3
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S 12
/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
/*description: .*/
#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE 0x00000003
@@ -4091,12 +4067,6 @@ extern "C" {
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S 14
/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
/*description: .*/
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER 0x00000003
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_M ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_S))
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_V 0x3
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_S 12
/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
/*description: .*/
#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE 0x00000003
@@ -4739,7 +4709,7 @@ extern "C" {
#define SENSITIVE_DIS_RTC_CPU_S 0
#define SENSITIVE_DATE_REG (DR_REG_SENSITIVE_BASE + 0xFFC)
/* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101180 ; */
/* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101280 ; */
/*description: .*/
#define SENSITIVE_DATE 0x0FFFFFFF
#define SENSITIVE_DATE_M ((SENSITIVE_DATE_V)<<(SENSITIVE_DATE_S))