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https://github.com/espressif/esp-idf.git
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Merge branch 'feature/efuse_esp32p4_add_new' into 'master'
feat(efuse): Adds new efuses for esp32p4 See merge request espressif/esp-idf!29085
This commit is contained in:
Konstantin Kondrashov
@@ -1,5 +1,5 @@
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/**
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -735,32 +735,116 @@ extern "C" {
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#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
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#define EFUSE_MAC_1_V 0x0000FFFFU
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#define EFUSE_MAC_1_S 0
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/** EFUSE_MAC_EXT : RO; bitpos: [31:16]; default: 0;
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/** EFUSE_RESERVED_1_16 : RO; bitpos: [31:16]; default: 0;
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* Stores the extended bits of MAC address.
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*/
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#define EFUSE_MAC_EXT 0x0000FFFFU
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#define EFUSE_MAC_EXT_M (EFUSE_MAC_EXT_V << EFUSE_MAC_EXT_S)
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#define EFUSE_MAC_EXT_V 0x0000FFFFU
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#define EFUSE_MAC_EXT_S 16
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#define EFUSE_RESERVED_1_16 0x0000FFFFU
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#define EFUSE_RESERVED_1_16_M (EFUSE_RESERVED_1_16_V << EFUSE_RESERVED_1_16_S)
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#define EFUSE_RESERVED_1_16_V 0x0000FFFFU
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#define EFUSE_RESERVED_1_16_S 16
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/** EFUSE_RD_MAC_SYS_2_REG register
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* BLOCK1 data register $n.
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*/
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#define EFUSE_RD_MAC_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c)
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/** EFUSE_MAC_RESERVED_1 : RO; bitpos: [13:0]; default: 0;
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* Reserved.
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/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [3:0]; default: 0;
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* Minor chip version
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*/
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#define EFUSE_MAC_RESERVED_1 0x00003FFFU
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#define EFUSE_MAC_RESERVED_1_M (EFUSE_MAC_RESERVED_1_V << EFUSE_MAC_RESERVED_1_S)
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#define EFUSE_MAC_RESERVED_1_V 0x00003FFFU
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#define EFUSE_MAC_RESERVED_1_S 0
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/** EFUSE_MAC_RESERVED_0 : RO; bitpos: [31:14]; default: 0;
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* Reserved.
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#define EFUSE_WAFER_VERSION_MINOR 0x0000000FU
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#define EFUSE_WAFER_VERSION_MINOR_M (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S)
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#define EFUSE_WAFER_VERSION_MINOR_V 0x0000000FU
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#define EFUSE_WAFER_VERSION_MINOR_S 0
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/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [5:4]; default: 0;
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* Major chip version
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*/
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#define EFUSE_MAC_RESERVED_0 0x0003FFFFU
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#define EFUSE_MAC_RESERVED_0_M (EFUSE_MAC_RESERVED_0_V << EFUSE_MAC_RESERVED_0_S)
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#define EFUSE_MAC_RESERVED_0_V 0x0003FFFFU
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#define EFUSE_MAC_RESERVED_0_S 14
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#define EFUSE_WAFER_VERSION_MAJOR 0x00000003U
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#define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S)
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#define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U
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#define EFUSE_WAFER_VERSION_MAJOR_S 4
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/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [6]; default: 0;
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* Disables check of wafer version major
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*/
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#define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(6))
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#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
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#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U
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#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 6
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/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [7]; default: 0;
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* Disables check of blk version major
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*/
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#define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(7))
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#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
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#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U
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#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 7
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/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [10:8]; default: 0;
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* BLK_VERSION_MINOR of BLOCK2
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*/
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#define EFUSE_BLK_VERSION_MINOR 0x00000007U
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#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
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#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U
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#define EFUSE_BLK_VERSION_MINOR_S 8
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/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [12:11]; default: 0;
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* BLK_VERSION_MAJOR of BLOCK2
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*/
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#define EFUSE_BLK_VERSION_MAJOR 0x00000003U
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#define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
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#define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U
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#define EFUSE_BLK_VERSION_MAJOR_S 11
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/** EFUSE_FLASH_CAP : R; bitpos: [15:13]; default: 0;
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* Flash capacity
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*/
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#define EFUSE_FLASH_CAP 0x00000007U
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#define EFUSE_FLASH_CAP_M (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S)
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#define EFUSE_FLASH_CAP_V 0x00000007U
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#define EFUSE_FLASH_CAP_S 13
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/** EFUSE_FLASH_TEMP : R; bitpos: [17:16]; default: 0;
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* Flash temperature
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*/
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#define EFUSE_FLASH_TEMP 0x00000003U
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#define EFUSE_FLASH_TEMP_M (EFUSE_FLASH_TEMP_V << EFUSE_FLASH_TEMP_S)
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#define EFUSE_FLASH_TEMP_V 0x00000003U
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#define EFUSE_FLASH_TEMP_S 16
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/** EFUSE_FLASH_VENDOR : R; bitpos: [20:18]; default: 0;
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* Flash vendor
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*/
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#define EFUSE_FLASH_VENDOR 0x00000007U
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#define EFUSE_FLASH_VENDOR_M (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S)
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#define EFUSE_FLASH_VENDOR_V 0x00000007U
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#define EFUSE_FLASH_VENDOR_S 18
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/** EFUSE_PSRAM_CAP : R; bitpos: [22:21]; default: 0;
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* PSRAM capacity
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*/
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#define EFUSE_PSRAM_CAP 0x00000003U
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#define EFUSE_PSRAM_CAP_M (EFUSE_PSRAM_CAP_V << EFUSE_PSRAM_CAP_S)
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#define EFUSE_PSRAM_CAP_V 0x00000003U
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#define EFUSE_PSRAM_CAP_S 21
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/** EFUSE_PSRAM_TEMP : R; bitpos: [24:23]; default: 0;
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* PSRAM temperature
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*/
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#define EFUSE_PSRAM_TEMP 0x00000003U
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#define EFUSE_PSRAM_TEMP_M (EFUSE_PSRAM_TEMP_V << EFUSE_PSRAM_TEMP_S)
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#define EFUSE_PSRAM_TEMP_V 0x00000003U
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#define EFUSE_PSRAM_TEMP_S 23
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/** EFUSE_PSRAM_VENDOR : R; bitpos: [26:25]; default: 0;
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* PSRAM vendor
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*/
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#define EFUSE_PSRAM_VENDOR 0x00000003U
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#define EFUSE_PSRAM_VENDOR_M (EFUSE_PSRAM_VENDOR_V << EFUSE_PSRAM_VENDOR_S)
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#define EFUSE_PSRAM_VENDOR_V 0x00000003U
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#define EFUSE_PSRAM_VENDOR_S 25
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/** EFUSE_PKG_VERSION : R; bitpos: [29:27]; default: 0;
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* Package version
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*/
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#define EFUSE_PKG_VERSION 0x00000007U
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#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
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#define EFUSE_PKG_VERSION_V 0x00000007U
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#define EFUSE_PKG_VERSION_S 27
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/** EFUSE_RESERVED_1_94 : R; bitpos: [31:30]; default: 0;
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* reserved
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*/
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#define EFUSE_RESERVED_1_94 0x00000003U
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#define EFUSE_RESERVED_1_94_M (EFUSE_RESERVED_1_94_V << EFUSE_RESERVED_1_94_S)
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#define EFUSE_RESERVED_1_94_V 0x00000003U
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#define EFUSE_RESERVED_1_94_S 30
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/** EFUSE_RD_MAC_SYS_3_REG register
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* BLOCK1 data register $n.
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@@ -809,49 +893,49 @@ extern "C" {
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* Register $n of BLOCK2 (system).
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*/
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#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
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/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0;
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* Stores the zeroth 32 bits of the first part of system data.
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/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0;
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* Optional unique 128-bit ID
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*/
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#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S)
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#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_0_S 0
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#define EFUSE_OPTIONAL_UNIQUE_ID 0xFFFFFFFFU
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#define EFUSE_OPTIONAL_UNIQUE_ID_M (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S)
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#define EFUSE_OPTIONAL_UNIQUE_ID_V 0xFFFFFFFFU
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#define EFUSE_OPTIONAL_UNIQUE_ID_S 0
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/** EFUSE_RD_SYS_PART1_DATA1_REG register
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* Register $n of BLOCK2 (system).
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*/
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#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
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/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0;
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* Stores the first 32 bits of the first part of system data.
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/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0;
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* Optional unique 128-bit ID
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*/
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#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S)
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#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_1_S 0
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#define EFUSE_OPTIONAL_UNIQUE_ID_1 0xFFFFFFFFU
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#define EFUSE_OPTIONAL_UNIQUE_ID_1_M (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S)
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#define EFUSE_OPTIONAL_UNIQUE_ID_1_V 0xFFFFFFFFU
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#define EFUSE_OPTIONAL_UNIQUE_ID_1_S 0
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/** EFUSE_RD_SYS_PART1_DATA2_REG register
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* Register $n of BLOCK2 (system).
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*/
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#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
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/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0;
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* Stores the second 32 bits of the first part of system data.
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/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0;
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* Optional unique 128-bit ID
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*/
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#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S)
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#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_2_S 0
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#define EFUSE_OPTIONAL_UNIQUE_ID_2 0xFFFFFFFFU
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#define EFUSE_OPTIONAL_UNIQUE_ID_2_M (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S)
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#define EFUSE_OPTIONAL_UNIQUE_ID_2_V 0xFFFFFFFFU
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#define EFUSE_OPTIONAL_UNIQUE_ID_2_S 0
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/** EFUSE_RD_SYS_PART1_DATA3_REG register
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* Register $n of BLOCK2 (system).
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*/
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#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
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/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0;
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* Stores the third 32 bits of the first part of system data.
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/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0;
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* Optional unique 128-bit ID
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*/
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#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S)
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#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_3_S 0
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#define EFUSE_OPTIONAL_UNIQUE_ID_3 0xFFFFFFFFU
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#define EFUSE_OPTIONAL_UNIQUE_ID_3_M (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S)
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#define EFUSE_OPTIONAL_UNIQUE_ID_3_V 0xFFFFFFFFU
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#define EFUSE_OPTIONAL_UNIQUE_ID_3_S 0
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/** EFUSE_RD_SYS_PART1_DATA4_REG register
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* Register $n of BLOCK2 (system).
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@@ -977,25 +1061,39 @@ extern "C" {
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* Register $n of BLOCK3 (user).
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*/
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#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94)
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/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0;
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* Stores the sixth 32 bits of BLOCK3 (user).
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/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0;
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* reserved
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*/
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#define EFUSE_USR_DATA6 0xFFFFFFFFU
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#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S)
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#define EFUSE_USR_DATA6_V 0xFFFFFFFFU
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#define EFUSE_USR_DATA6_S 0
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#define EFUSE_RESERVED_3_192 0x000000FFU
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#define EFUSE_RESERVED_3_192_M (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S)
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#define EFUSE_RESERVED_3_192_V 0x000000FFU
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#define EFUSE_RESERVED_3_192_S 0
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/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0;
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* Custom MAC
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*/
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#define EFUSE_CUSTOM_MAC 0x00FFFFFFU
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#define EFUSE_CUSTOM_MAC_M (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S)
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#define EFUSE_CUSTOM_MAC_V 0x00FFFFFFU
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#define EFUSE_CUSTOM_MAC_S 8
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/** EFUSE_RD_USR_DATA7_REG register
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* Register $n of BLOCK3 (user).
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*/
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#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98)
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/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0;
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* Stores the seventh 32 bits of BLOCK3 (user).
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/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0;
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* Custom MAC
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*/
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#define EFUSE_USR_DATA7 0xFFFFFFFFU
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#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S)
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#define EFUSE_USR_DATA7_V 0xFFFFFFFFU
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#define EFUSE_USR_DATA7_S 0
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#define EFUSE_CUSTOM_MAC_1 0x00FFFFFFU
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#define EFUSE_CUSTOM_MAC_1_M (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S)
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#define EFUSE_CUSTOM_MAC_1_V 0x00FFFFFFU
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#define EFUSE_CUSTOM_MAC_1_S 0
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/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0;
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* reserved
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*/
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#define EFUSE_RESERVED_3_248 0x000000FFU
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#define EFUSE_RESERVED_3_248_M (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S)
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#define EFUSE_RESERVED_3_248_V 0x000000FFU
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#define EFUSE_RESERVED_3_248_S 24
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/** EFUSE_RD_KEY0_DATA0_REG register
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* Register $n of BLOCK4 (KEY0).
|
||||
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@@ -1,5 +1,5 @@
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/**
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
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@@ -554,10 +554,10 @@ typedef union {
|
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* Stores the high 16 bits of MAC address.
|
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*/
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uint32_t mac_1:16;
|
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/** mac_ext : RO; bitpos: [31:16]; default: 0;
|
||||
/** reserved_1_16 : RO; bitpos: [31:16]; default: 0;
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* Stores the extended bits of MAC address.
|
||||
*/
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uint32_t mac_ext:16;
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uint32_t reserved_1_16:16;
|
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};
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uint32_t val;
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} efuse_rd_mac_sys_1_reg_t;
|
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@@ -567,14 +567,62 @@ typedef union {
|
||||
*/
|
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typedef union {
|
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struct {
|
||||
/** mac_reserved_1 : RO; bitpos: [13:0]; default: 0;
|
||||
* Reserved.
|
||||
/** wafer_version_minor : R; bitpos: [3:0]; default: 0;
|
||||
* Minor chip version
|
||||
*/
|
||||
uint32_t mac_reserved_1:14;
|
||||
/** mac_reserved_0 : RO; bitpos: [31:14]; default: 0;
|
||||
* Reserved.
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uint32_t wafer_version_minor:4;
|
||||
/** wafer_version_major : R; bitpos: [5:4]; default: 0;
|
||||
* Major chip version
|
||||
*/
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||||
uint32_t mac_reserved_0:18;
|
||||
uint32_t wafer_version_major:2;
|
||||
/** disable_wafer_version_major : R; bitpos: [6]; default: 0;
|
||||
* Disables check of wafer version major
|
||||
*/
|
||||
uint32_t disable_wafer_version_major:1;
|
||||
/** disable_blk_version_major : R; bitpos: [7]; default: 0;
|
||||
* Disables check of blk version major
|
||||
*/
|
||||
uint32_t disable_blk_version_major:1;
|
||||
/** blk_version_minor : R; bitpos: [10:8]; default: 0;
|
||||
* BLK_VERSION_MINOR of BLOCK2
|
||||
*/
|
||||
uint32_t blk_version_minor:3;
|
||||
/** blk_version_major : R; bitpos: [12:11]; default: 0;
|
||||
* BLK_VERSION_MAJOR of BLOCK2
|
||||
*/
|
||||
uint32_t blk_version_major:2;
|
||||
/** flash_cap : R; bitpos: [15:13]; default: 0;
|
||||
* Flash capacity
|
||||
*/
|
||||
uint32_t flash_cap:3;
|
||||
/** flash_temp : R; bitpos: [17:16]; default: 0;
|
||||
* Flash temperature
|
||||
*/
|
||||
uint32_t flash_temp:2;
|
||||
/** flash_vendor : R; bitpos: [20:18]; default: 0;
|
||||
* Flash vendor
|
||||
*/
|
||||
uint32_t flash_vendor:3;
|
||||
/** psram_cap : R; bitpos: [22:21]; default: 0;
|
||||
* PSRAM capacity
|
||||
*/
|
||||
uint32_t psram_cap:2;
|
||||
/** psram_temp : R; bitpos: [24:23]; default: 0;
|
||||
* PSRAM temperature
|
||||
*/
|
||||
uint32_t psram_temp:2;
|
||||
/** psram_vendor : R; bitpos: [26:25]; default: 0;
|
||||
* PSRAM vendor
|
||||
*/
|
||||
uint32_t psram_vendor:2;
|
||||
/** pkg_version : R; bitpos: [29:27]; default: 0;
|
||||
* Package version
|
||||
*/
|
||||
uint32_t pkg_version:3;
|
||||
/** reserved_1_94 : R; bitpos: [31:30]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t reserved_1_94:2;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_mac_sys_2_reg_t;
|
||||
@@ -627,10 +675,10 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_0 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the zeroth 32 bits of the first part of system data.
|
||||
/** optional_unique_id : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
uint32_t sys_data_part1_0:32;
|
||||
uint32_t optional_unique_id:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data0_reg_t;
|
||||
@@ -640,10 +688,10 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_1 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the first 32 bits of the first part of system data.
|
||||
/** optional_unique_id_1 : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
uint32_t sys_data_part1_1:32;
|
||||
uint32_t optional_unique_id_1:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data1_reg_t;
|
||||
@@ -653,10 +701,10 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_2 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the second 32 bits of the first part of system data.
|
||||
/** optional_unique_id_2 : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
uint32_t sys_data_part1_2:32;
|
||||
uint32_t optional_unique_id_2:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data2_reg_t;
|
||||
@@ -666,10 +714,10 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_3 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the third 32 bits of the first part of system data.
|
||||
/** optional_unique_id_3 : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
uint32_t sys_data_part1_3:32;
|
||||
uint32_t optional_unique_id_3:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data3_reg_t;
|
||||
@@ -809,10 +857,14 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** usr_data6 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the sixth 32 bits of BLOCK3 (user).
|
||||
/** reserved_3_192 : R; bitpos: [7:0]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t usr_data6:32;
|
||||
uint32_t reserved_3_192:8;
|
||||
/** custom_mac : R; bitpos: [31:8]; default: 0;
|
||||
* Custom MAC
|
||||
*/
|
||||
uint32_t custom_mac:24;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_usr_data6_reg_t;
|
||||
@@ -822,10 +874,14 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** usr_data7 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the seventh 32 bits of BLOCK3 (user).
|
||||
/** custom_mac_1 : R; bitpos: [23:0]; default: 0;
|
||||
* Custom MAC
|
||||
*/
|
||||
uint32_t usr_data7:32;
|
||||
uint32_t custom_mac_1:24;
|
||||
/** reserved_3_248 : R; bitpos: [31:24]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t reserved_3_248:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_usr_data7_reg_t;
|
||||
|
||||
Reference in New Issue
Block a user