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esp32h2: add rtc clock support

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This commit is contained in:
sly
2021-07-07 11:28:07 +08:00
committed by Shu Chen
parent 6ab495b4dc
commit 11dfd802e0
23 changed files with 1818 additions and 623 deletions
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141
components/soc/esp32h2/i2c_bbpll.h
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@@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
@@ -24,7 +16,8 @@
*/
#define I2C_BBPLL 0x66
#define I2C_BBPLL_HOSTID 1
#define I2C_BBPLL_HOSTID 0
#define I2C_BBPLL_IR_CAL_DELAY 0
#define I2C_BBPLL_IR_CAL_DELAY_MSB 3
@@ -58,71 +51,39 @@
#define I2C_BBPLL_OC_REF_DIV_MSB 3
#define I2C_BBPLL_OC_REF_DIV_LSB 0
#define I2C_BBPLL_OC_DCHGP 2
#define I2C_BBPLL_OC_DCHGP_MSB 6
#define I2C_BBPLL_OC_DCHGP_LSB 4
#define I2C_BBPLL_OC_DIV 3
#define I2C_BBPLL_OC_DIV_MSB 5
#define I2C_BBPLL_OC_DIV_LSB 0
#define I2C_BBPLL_OC_ENB_FCAL 2
#define I2C_BBPLL_OC_CHGP_DCUR 4
#define I2C_BBPLL_OC_CHGP_DCUR_MSB 2
#define I2C_BBPLL_OC_CHGP_DCUR_LSB 0
#define I2C_BBPLL_OC_BUFF_DCUR 4
#define I2C_BBPLL_OC_BUFF_DCUR_MSB 5
#define I2C_BBPLL_OC_BUFF_DCUR_LSB 3
#define I2C_BBPLL_OC_TSCHGP 4
#define I2C_BBPLL_OC_TSCHGP_MSB 6
#define I2C_BBPLL_OC_TSCHGP_LSB 6
#define I2C_BBPLL_OC_ENB_FCAL 4
#define I2C_BBPLL_OC_ENB_FCAL_MSB 7
#define I2C_BBPLL_OC_ENB_FCAL_LSB 7
#define I2C_BBPLL_OC_DIV_7_0 3
#define I2C_BBPLL_OC_DIV_7_0_MSB 7
#define I2C_BBPLL_OC_DIV_7_0_LSB 0
#define I2C_BBPLL_OC_LPF_DR 5
#define I2C_BBPLL_OC_LPF_DR_MSB 1
#define I2C_BBPLL_OC_LPF_DR_LSB 0
#define I2C_BBPLL_RSTB_DIV_ADC 4
#define I2C_BBPLL_RSTB_DIV_ADC_MSB 0
#define I2C_BBPLL_RSTB_DIV_ADC_LSB 0
#define I2C_BBPLL_OC_VCO_DCUR 5
#define I2C_BBPLL_OC_VCO_DCUR_MSB 3
#define I2C_BBPLL_OC_VCO_DCUR_LSB 2
#define I2C_BBPLL_MODE_HF 4
#define I2C_BBPLL_MODE_HF_MSB 1
#define I2C_BBPLL_MODE_HF_LSB 1
#define I2C_BBPLL_DIV_ADC 4
#define I2C_BBPLL_DIV_ADC_MSB 3
#define I2C_BBPLL_DIV_ADC_LSB 2
#define I2C_BBPLL_DIV_DAC 4
#define I2C_BBPLL_DIV_DAC_MSB 4
#define I2C_BBPLL_DIV_DAC_LSB 4
#define I2C_BBPLL_DIV_CPU 4
#define I2C_BBPLL_DIV_CPU_MSB 5
#define I2C_BBPLL_DIV_CPU_LSB 5
#define I2C_BBPLL_OC_ENB_VCON 4
#define I2C_BBPLL_OC_ENB_VCON_MSB 6
#define I2C_BBPLL_OC_ENB_VCON_LSB 6
#define I2C_BBPLL_OC_TSCHGP 4
#define I2C_BBPLL_OC_TSCHGP_MSB 7
#define I2C_BBPLL_OC_TSCHGP_LSB 7
#define I2C_BBPLL_OC_DR1 5
#define I2C_BBPLL_OC_DR1_MSB 2
#define I2C_BBPLL_OC_DR1_LSB 0
#define I2C_BBPLL_OC_DR3 5
#define I2C_BBPLL_OC_DR3_MSB 6
#define I2C_BBPLL_OC_DR3_LSB 4
#define I2C_BBPLL_EN_USB 5
#define I2C_BBPLL_EN_USB_MSB 7
#define I2C_BBPLL_EN_USB_LSB 7
#define I2C_BBPLL_OC_DCUR 6
#define I2C_BBPLL_OC_DCUR_MSB 2
#define I2C_BBPLL_OC_DCUR_LSB 0
#define I2C_BBPLL_INC_CUR 6
#define I2C_BBPLL_INC_CUR_MSB 3
#define I2C_BBPLL_INC_CUR_LSB 3
#define I2C_BBPLL_OC_DHREF_SEL 6
#define I2C_BBPLL_OC_DHREF_SEL 5
#define I2C_BBPLL_OC_DHREF_SEL_MSB 5
#define I2C_BBPLL_OC_DHREF_SEL_LSB 4
#define I2C_BBPLL_OC_DLREF_SEL 6
#define I2C_BBPLL_OC_DLREF_SEL 5
#define I2C_BBPLL_OC_DLREF_SEL_MSB 7
#define I2C_BBPLL_OC_DLREF_SEL_LSB 6
@@ -146,38 +107,14 @@
#define I2C_BBPLL_OR_LOCK_MSB 7
#define I2C_BBPLL_OR_LOCK_LSB 7
#define I2C_BBPLL_BBADC_DELAY1 9
#define I2C_BBPLL_BBADC_DELAY1_MSB 1
#define I2C_BBPLL_BBADC_DELAY1_LSB 0
#define I2C_BBPLL_BBADC_DELAY2 9
#define I2C_BBPLL_BBADC_DELAY2_MSB 3
#define I2C_BBPLL_BBADC_DELAY2_LSB 2
#define I2C_BBPLL_BBADC_DVDD 9
#define I2C_BBPLL_BBADC_DVDD_MSB 5
#define I2C_BBPLL_BBADC_DVDD_LSB 4
#define I2C_BBPLL_BBADC_DREF 9
#define I2C_BBPLL_BBADC_DREF_MSB 7
#define I2C_BBPLL_BBADC_DREF_LSB 6
#define I2C_BBPLL_BBADC_DCUR 10
#define I2C_BBPLL_BBADC_DCUR_MSB 1
#define I2C_BBPLL_BBADC_DCUR_LSB 0
#define I2C_BBPLL_BBADC_INPUT_SHORT 10
#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2
#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2
#define I2C_BBPLL_DTEST 10
#define I2C_BBPLL_DTEST_MSB 1
#define I2C_BBPLL_DTEST_LSB 0
#define I2C_BBPLL_ENT_PLL 10
#define I2C_BBPLL_ENT_PLL_MSB 3
#define I2C_BBPLL_ENT_PLL_LSB 3
#define I2C_BBPLL_ENT_PLL_MSB 2
#define I2C_BBPLL_ENT_PLL_LSB 2
#define I2C_BBPLL_DTEST 10
#define I2C_BBPLL_DTEST_MSB 5
#define I2C_BBPLL_DTEST_LSB 4
#define I2C_BBPLL_ENT_ADC 10
#define I2C_BBPLL_ENT_ADC_MSB 7
#define I2C_BBPLL_ENT_ADC_LSB 6
#define I2C_BBPLL_DIV_CPU 10
#define I2C_BBPLL_DIV_CPU_MSB 3
#define I2C_BBPLL_DIV_CPU_LSB 3

112
components/soc/esp32h2/i2c_bias.h Normal file
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@@ -0,0 +1,112 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#define I2C_BIAS 0x6a
#define I2C_BIAS_HOSTID 0
#define I2C_BIAS_DREG_1P6 0
#define I2C_BIAS_DREG_1P6_MSB 3
#define I2C_BIAS_DREG_1P6_LSB 0
#define I2C_BIAS_DREG_0P8 0
#define I2C_BIAS_DREG_0P8_MSB 7
#define I2C_BIAS_DREG_0P8_LSB 4
#define I2C_BIAS_DREG_1P1_PVT 1
#define I2C_BIAS_DREG_1P1_PVT_MSB 3
#define I2C_BIAS_DREG_1P1_PVT_LSB 0
#define I2C_BIAS_DREG_1P2 1
#define I2C_BIAS_DREG_1P2_MSB 7
#define I2C_BIAS_DREG_1P2_LSB 4
#define I2C_BIAS_ENT_CPREG 2
#define I2C_BIAS_ENT_CPREG_MSB 0
#define I2C_BIAS_ENT_CPREG_LSB 0
#define I2C_BIAS_ENT_CGM 2
#define I2C_BIAS_ENT_CGM_MSB 1
#define I2C_BIAS_ENT_CGM_LSB 1
#define I2C_BIAS_CGM_BIAS 2
#define I2C_BIAS_CGM_BIAS_MSB 3
#define I2C_BIAS_CGM_BIAS_LSB 2
#define I2C_BIAS_DREF_IGM 2
#define I2C_BIAS_DREF_IGM_MSB 4
#define I2C_BIAS_DREF_IGM_LSB 4
#define I2C_BIAS_RC_DVREF 2
#define I2C_BIAS_RC_DVREF_MSB 6
#define I2C_BIAS_RC_DVREF_LSB 5
#define I2C_BIAS_FORCE_DISABLE_BIAS_SLEEP 2
#define I2C_BIAS_FORCE_DISABLE_BIAS_SLEEP_MSB 7
#define I2C_BIAS_FORCE_DISABLE_BIAS_SLEEP_LSB 7
#define I2C_BIAS_RC_ENX 3
#define I2C_BIAS_RC_ENX_MSB 0
#define I2C_BIAS_RC_ENX_LSB 0
#define I2C_BIAS_RC_START 3
#define I2C_BIAS_RC_START_MSB 1
#define I2C_BIAS_RC_START_LSB 1
#define I2C_BIAS_RC_DCAP_EXT 3
#define I2C_BIAS_RC_DCAP_EXT_MSB 7
#define I2C_BIAS_RC_DCAP_EXT_LSB 2
#define I2C_BIAS_XPD_RC 4
#define I2C_BIAS_XPD_RC_MSB 0
#define I2C_BIAS_XPD_RC_LSB 0
#define I2C_BIAS_ENT_CONSTI 4
#define I2C_BIAS_ENT_CONSTI_MSB 1
#define I2C_BIAS_ENT_CONSTI_LSB 1
#define I2C_BIAS_XPD_ICX 4
#define I2C_BIAS_XPD_ICX_MSB 2
#define I2C_BIAS_XPD_ICX_LSB 2
#define I2C_BIAS_RC_RSTB 4
#define I2C_BIAS_RC_RSTB_MSB 3
#define I2C_BIAS_RC_RSTB_LSB 3
#define I2C_BIAS_RC_DIV 4
#define I2C_BIAS_RC_DIV_MSB 7
#define I2C_BIAS_RC_DIV_LSB 4
#define I2C_BIAS_RC_CAP 5
#define I2C_BIAS_RC_CAP_MSB 5
#define I2C_BIAS_RC_CAP_LSB 0
#define I2C_BIAS_RC_UD 5
#define I2C_BIAS_RC_UD_MSB 6
#define I2C_BIAS_RC_UD_LSB 6
#define I2C_BIAS_RC_LOCKB 5
#define I2C_BIAS_RC_LOCKB_MSB 7
#define I2C_BIAS_RC_LOCKB_LSB 7
#define I2C_BIAS_RC_CHG_COUNT 6
#define I2C_BIAS_RC_CHG_COUNT_MSB 4
#define I2C_BIAS_RC_CHG_COUNT_LSB 0
#define I2C_BIAS_XPD_CPREG 7
#define I2C_BIAS_XPD_CPREG_MSB 0
#define I2C_BIAS_XPD_CPREG_LSB 0
#define I2C_BIAS_XPD_CGM 7
#define I2C_BIAS_XPD_CGM_MSB 1
#define I2C_BIAS_XPD_CGM_LSB 1
#define I2C_BIAS_DTEST 7
#define I2C_BIAS_DTEST_MSB 3
#define I2C_BIAS_DTEST_LSB 2
#define I2C_BIAS_DRES12K 7
#define I2C_BIAS_DRES12K_MSB 7
#define I2C_BIAS_DRES12K_LSB 4

280
components/soc/esp32h2/i2c_pmu.h Normal file
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@@ -0,0 +1,280 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#define I2C_PMU 0x6d
#define I2C_PMU_HOSTID 0
#define I2C_PMU_THRES_HIGH_7_0 0
#define I2C_PMU_THRES_HIGH_7_0_MSB 7
#define I2C_PMU_THRES_HIGH_7_0_LSB 0
#define I2C_PMU_THRES_LOW_7_0 1
#define I2C_PMU_THRES_LOW_7_0_MSB 7
#define I2C_PMU_THRES_LOW_7_0_LSB 0
#define I2C_PMU_THRES_HIGH_11_8 2
#define I2C_PMU_THRES_HIGH_11_8_MSB 3
#define I2C_PMU_THRES_HIGH_11_8_LSB 0
#define I2C_PMU_THRES_LOW_11_8 2
#define I2C_PMU_THRES_LOW_11_8_MSB 7
#define I2C_PMU_THRES_LOW_11_8_LSB 4
#define I2C_PMU_PVT_DELAY_INIT 3
#define I2C_PMU_PVT_DELAY_INIT_MSB 7
#define I2C_PMU_PVT_DELAY_INIT_LSB 0
#define I2C_PMU_PVT_DELAY_COUNT 4
#define I2C_PMU_PVT_DELAY_COUNT_MSB 5
#define I2C_PMU_PVT_DELAY_COUNT_LSB 0
#define I2C_PMU_OR_EN_CONT_CAL 4
#define I2C_PMU_OR_EN_CONT_CAL_MSB 7
#define I2C_PMU_OR_EN_CONT_CAL_LSB 7
#define I2C_PMU_I2C_RTC_DREG 5
#define I2C_PMU_I2C_RTC_DREG_MSB 4
#define I2C_PMU_I2C_RTC_DREG_LSB 0
#define I2C_PMU_I2C_DIG_DREG 6
#define I2C_PMU_I2C_DIG_DREG_MSB 4
#define I2C_PMU_I2C_DIG_DREG_LSB 0
#define I2C_PMU_I2C_RTC_DREG_SLP 7
#define I2C_PMU_I2C_RTC_DREG_SLP_MSB 3
#define I2C_PMU_I2C_RTC_DREG_SLP_LSB 0
#define I2C_PMU_I2C_DIG_DREG_SLP 7
#define I2C_PMU_I2C_DIG_DREG_SLP_MSB 7
#define I2C_PMU_I2C_DIG_DREG_SLP_LSB 4
#define I2C_PMU_EN_I2C_RTC_DREG 10
#define I2C_PMU_EN_I2C_RTC_DREG_MSB 0
#define I2C_PMU_EN_I2C_RTC_DREG_LSB 0
#define I2C_PMU_EN_I2C_DIG_DREG 10
#define I2C_PMU_EN_I2C_DIG_DREG_MSB 1
#define I2C_PMU_EN_I2C_DIG_DREG_LSB 1
#define I2C_PMU_EN_I2C_RTC_DREG_SLP 10
#define I2C_PMU_EN_I2C_RTC_DREG_SLP_MSB 2
#define I2C_PMU_EN_I2C_RTC_DREG_SLP_LSB 2
#define I2C_PMU_EN_I2C_DIG_DREG_SLP 10
#define I2C_PMU_EN_I2C_DIG_DREG_SLP_MSB 3
#define I2C_PMU_EN_I2C_DIG_DREG_SLP_LSB 3
#define I2C_PMU_ENX_RTC_DREG 11
#define I2C_PMU_ENX_RTC_DREG_MSB 0
#define I2C_PMU_ENX_RTC_DREG_LSB 0
#define I2C_PMU_ENX_DIG_DREG 11
#define I2C_PMU_ENX_DIG_DREG_MSB 1
#define I2C_PMU_ENX_DIG_DREG_LSB 1
#define I2C_PMU_OR_XPD_RTC_SLAVE_3P3 11
#define I2C_PMU_OR_XPD_RTC_SLAVE_3P3_MSB 2
#define I2C_PMU_OR_XPD_RTC_SLAVE_3P3_LSB 2
#define I2C_PMU_OR_XPD_RTC_REG 11
#define I2C_PMU_OR_XPD_RTC_REG_MSB 4
#define I2C_PMU_OR_XPD_RTC_REG_LSB 4
#define I2C_PMU_OR_XPD_DIG_REG 11
#define I2C_PMU_OR_XPD_DIG_REG_MSB 5
#define I2C_PMU_OR_XPD_DIG_REG_LSB 5
#define I2C_PMU_OR_PD_RTC_REG_SLP 11
#define I2C_PMU_OR_PD_RTC_REG_SLP_MSB 6
#define I2C_PMU_OR_PD_RTC_REG_SLP_LSB 6
#define I2C_PMU_OR_PD_DIG_REG_SLP 11
#define I2C_PMU_OR_PD_DIG_REG_SLP_MSB 7
#define I2C_PMU_OR_PD_DIG_REG_SLP_LSB 7
#define I2C_PMU_INT_DREG 12
#define I2C_PMU_INT_DREG_MSB 4
#define I2C_PMU_INT_DREG_LSB 0
#define I2C_PMU_O_UDF 12
#define I2C_PMU_O_UDF_MSB 5
#define I2C_PMU_O_UDF_LSB 5
#define I2C_PMU_O_OVF 12
#define I2C_PMU_O_OVF_MSB 6
#define I2C_PMU_O_OVF_LSB 6
#define I2C_PMU_O_UPDATE 12
#define I2C_PMU_O_UPDATE_MSB 7
#define I2C_PMU_O_UPDATE_LSB 7
#define I2C_PMU_PVT_COUNT_7_0 13
#define I2C_PMU_PVT_COUNT_7_0_MSB 7
#define I2C_PMU_PVT_COUNT_7_0_LSB 0
#define I2C_PMU_PVT_COUNT_11_8 14
#define I2C_PMU_PVT_COUNT_11_8_MSB 3
#define I2C_PMU_PVT_COUNT_11_8_LSB 0
#define I2C_PMU_IC_VGOOD_LVDET 14
#define I2C_PMU_IC_VGOOD_LVDET_MSB 4
#define I2C_PMU_IC_VGOOD_LVDET_LSB 4
#define I2C_PMU_IC_POWER_GOOD_DCDC 14
#define I2C_PMU_IC_POWER_GOOD_DCDC_MSB 5
#define I2C_PMU_IC_POWER_GOOD_DCDC_LSB 5
#define I2C_PMU_IC_VGOOD_DIGDET 14
#define I2C_PMU_IC_VGOOD_DIGDET_MSB 6
#define I2C_PMU_IC_VGOOD_DIGDET_LSB 6
#define I2C_PMU_OR_XPD_DCDC 15
#define I2C_PMU_OR_XPD_DCDC_MSB 0
#define I2C_PMU_OR_XPD_DCDC_LSB 0
#define I2C_PMU_OR_DISALBE_DEEP_SLEEP_DCDC 15
#define I2C_PMU_OR_DISALBE_DEEP_SLEEP_DCDC_MSB 1
#define I2C_PMU_OR_DISALBE_DEEP_SLEEP_DCDC_LSB 1
#define I2C_PMU_OR_DISALBE_LIGHT_SLEEP_DCDC 15
#define I2C_PMU_OR_DISALBE_LIGHT_SLEEP_DCDC_MSB 2
#define I2C_PMU_OR_DISALBE_LIGHT_SLEEP_DCDC_LSB 2
#define I2C_PMU_OR_ENALBE_TRX_MODE_DCDC 15
#define I2C_PMU_OR_ENALBE_TRX_MODE_DCDC_MSB 3
#define I2C_PMU_OR_ENALBE_TRX_MODE_DCDC_LSB 3
#define I2C_PMU_OR_ENX_REG_DCDC 15
#define I2C_PMU_OR_ENX_REG_DCDC_MSB 4
#define I2C_PMU_OR_ENX_REG_DCDC_LSB 4
#define I2C_PMU_OR_UNLOCK_DCDC 15
#define I2C_PMU_OR_UNLOCK_DCDC_MSB 5
#define I2C_PMU_OR_UNLOCK_DCDC_LSB 5
#define I2C_PMU_OR_FORCE_LOCK_DCDC 15
#define I2C_PMU_OR_FORCE_LOCK_DCDC_MSB 6
#define I2C_PMU_OR_FORCE_LOCK_DCDC_LSB 6
#define I2C_PMU_OR_ENB_SLOW_CLK 15
#define I2C_PMU_OR_ENB_SLOW_CLK_MSB 7
#define I2C_PMU_OR_ENB_SLOW_CLK_LSB 7
#define I2C_PMU_OC_SCK_DCAP 16
#define I2C_PMU_OC_SCK_DCAP_MSB 7
#define I2C_PMU_OC_SCK_DCAP_LSB 0
#define I2C_PMU_OC_XPD_LVDET 17
#define I2C_PMU_OC_XPD_LVDET_MSB 0
#define I2C_PMU_OC_XPD_LVDET_LSB 0
#define I2C_PMU_OC_MODE_LVDET 17
#define I2C_PMU_OC_MODE_LVDET_MSB 1
#define I2C_PMU_OC_MODE_LVDET_LSB 1
#define I2C_PMU_OR_XPD_TRX 17
#define I2C_PMU_OR_XPD_TRX_MSB 2
#define I2C_PMU_OR_XPD_TRX_LSB 2
#define I2C_PMU_OR_EN_RESET_CHIP 17
#define I2C_PMU_OR_EN_RESET_CHIP_MSB 3
#define I2C_PMU_OR_EN_RESET_CHIP_LSB 3
#define I2C_PMU_OC_DREF_LVDET 17
#define I2C_PMU_OC_DREF_LVDET_MSB 6
#define I2C_PMU_OC_DREF_LVDET_LSB 4
#define I2C_PMU_OR_FORCE_XPD_REG_SLAVE 17
#define I2C_PMU_OR_FORCE_XPD_REG_SLAVE_MSB 7
#define I2C_PMU_OR_FORCE_XPD_REG_SLAVE_LSB 7
#define I2C_PMU_DTEST 18
#define I2C_PMU_DTEST_MSB 1
#define I2C_PMU_DTEST_LSB 0
#define I2C_PMU_ENT_BIAS 18
#define I2C_PMU_ENT_BIAS_MSB 2
#define I2C_PMU_ENT_BIAS_LSB 2
#define I2C_PMU_ENT_VDD 18
#define I2C_PMU_ENT_VDD_MSB 5
#define I2C_PMU_ENT_VDD_LSB 3
#define I2C_PMU_EN_DMUX 18
#define I2C_PMU_EN_DMUX_MSB 6
#define I2C_PMU_EN_DMUX_LSB 6
#define I2C_PMU_WD_DISABLE 18
#define I2C_PMU_WD_DISABLE_MSB 7
#define I2C_PMU_WD_DISABLE_LSB 7
#define I2C_PMU_DTEST_DCDC 19
#define I2C_PMU_DTEST_DCDC_MSB 0
#define I2C_PMU_DTEST_DCDC_LSB 0
#define I2C_PMU_TESTEN_DCDC 19
#define I2C_PMU_TESTEN_DCDC_MSB 1
#define I2C_PMU_TESTEN_DCDC_LSB 1
#define I2C_PMU_ADD_DCDC 19
#define I2C_PMU_ADD_DCDC_MSB 6
#define I2C_PMU_ADD_DCDC_LSB 4
#define I2C_PMU_OR_POCPENB_DCDC 20
#define I2C_PMU_OR_POCPENB_DCDC_MSB 0
#define I2C_PMU_OR_POCPENB_DCDC_LSB 0
#define I2C_PMU_OR_SSTIME_DCDC 20
#define I2C_PMU_OR_SSTIME_DCDC_MSB 1
#define I2C_PMU_OR_SSTIME_DCDC_LSB 1
#define I2C_PMU_OR_CCM_DCDC 20
#define I2C_PMU_OR_CCM_DCDC_MSB 2
#define I2C_PMU_OR_CCM_DCDC_LSB 2
#define I2C_PMU_OR_VSET_LOW_DCDC 20
#define I2C_PMU_OR_VSET_LOW_DCDC_MSB 7
#define I2C_PMU_OR_VSET_LOW_DCDC_LSB 3
#define I2C_PMU_OR_FSW_DCDC 21
#define I2C_PMU_OR_FSW_DCDC_MSB 2
#define I2C_PMU_OR_FSW_DCDC_LSB 0
#define I2C_PMU_OR_DCMLEVEL_DCDC 21
#define I2C_PMU_OR_DCMLEVEL_DCDC_MSB 4
#define I2C_PMU_OR_DCMLEVEL_DCDC_LSB 3
#define I2C_PMU_OR_DCM2ENB_DCDC 21
#define I2C_PMU_OR_DCM2ENB_DCDC_MSB 5
#define I2C_PMU_OR_DCM2ENB_DCDC_LSB 5
#define I2C_PMU_OR_RAMP_DCDC 21
#define I2C_PMU_OR_RAMP_DCDC_MSB 6
#define I2C_PMU_OR_RAMP_DCDC_LSB 6
#define I2C_PMU_OR_RAMPLEVEL_DCDC 21
#define I2C_PMU_OR_RAMPLEVEL_DCDC_MSB 7
#define I2C_PMU_OR_RAMPLEVEL_DCDC_LSB 7
#define I2C_PMU_OR_VSET_HIGH_DCDC 22
#define I2C_PMU_OR_VSET_HIGH_DCDC_MSB 4
#define I2C_PMU_OR_VSET_HIGH_DCDC_LSB 0
#define I2C_PMU_OC_DEL_SSEND 22
#define I2C_PMU_OC_DEL_SSEND_MSB 7
#define I2C_PMU_OC_DEL_SSEND_LSB 5
#define I2C_PMU_OC_XPD_DIGDET 23
#define I2C_PMU_OC_XPD_DIGDET_MSB 0
#define I2C_PMU_OC_XPD_DIGDET_LSB 0
#define I2C_PMU_OC_MODE_DIGDET 23
#define I2C_PMU_OC_MODE_DIGDET_MSB 1
#define I2C_PMU_OC_MODE_DIGDET_LSB 1
#define I2C_PMU_OC_DREF_DIGDET 23
#define I2C_PMU_OC_DREF_DIGDET_MSB 6
#define I2C_PMU_OC_DREF_DIGDET_LSB 4

108
components/soc/esp32h2/i2c_ulp.h Normal file
View File

@@ -0,0 +1,108 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#define I2C_ULP 0x61
#define I2C_ULP_HOSTID 0
#define I2C_ULP_IR_RESETB 0
#define I2C_ULP_IR_RESETB_MSB 0
#define I2C_ULP_IR_RESETB_LSB 0
#define I2C_ULP_XPD_REG_SLP 0
#define I2C_ULP_XPD_REG_SLP_MSB 1
#define I2C_ULP_XPD_REG_SLP_LSB 1
#define I2C_ULP_DBIAS_SLP 0
#define I2C_ULP_DBIAS_SLP_MSB 7
#define I2C_ULP_DBIAS_SLP_LSB 4
#define I2C_ULP_IR_FORCE_XPD_BIAS_BUF 1
#define I2C_ULP_IR_FORCE_XPD_BIAS_BUF_MSB 1
#define I2C_ULP_IR_FORCE_XPD_BIAS_BUF_LSB 1
#define I2C_ULP_IR_FORCE_XPD_IPH 1
#define I2C_ULP_IR_FORCE_XPD_IPH_MSB 2
#define I2C_ULP_IR_FORCE_XPD_IPH_LSB 2
#define I2C_ULP_IR_FORCE_XPD_VGATE_BUF 1
#define I2C_ULP_IR_FORCE_XPD_VGATE_BUF_MSB 3
#define I2C_ULP_IR_FORCE_XPD_VGATE_BUF_LSB 3
#define I2C_ULP_IR_FORCE_DISABLE_BIAS_SLEEP 1
#define I2C_ULP_IR_FORCE_DISABLE_BIAS_SLEEP_MSB 4
#define I2C_ULP_IR_FORCE_DISABLE_BIAS_SLEEP_LSB 4
#define I2C_ULP_IR_ZOS_XPD 2
#define I2C_ULP_IR_ZOS_XPD_MSB 0
#define I2C_ULP_IR_ZOS_XPD_LSB 0
#define I2C_ULP_IR_ZOS_RSTB 2
#define I2C_ULP_IR_ZOS_RSTB_MSB 1
#define I2C_ULP_IR_ZOS_RSTB_LSB 1
#define I2C_ULP_IR_ZOS_RESTART 2
#define I2C_ULP_IR_ZOS_RESTART_MSB 2
#define I2C_ULP_IR_ZOS_RESTART_LSB 2
#define I2C_ULP_DTEST 3
#define I2C_ULP_DTEST_MSB 1
#define I2C_ULP_DTEST_LSB 0
#define I2C_ULP_ENT_BG 3
#define I2C_ULP_ENT_BG_MSB 2
#define I2C_ULP_ENT_BG_LSB 2
#define I2C_ULP_MODE_LVDET 3
#define I2C_ULP_MODE_LVDET_MSB 3
#define I2C_ULP_MODE_LVDET_LSB 3
#define I2C_ULP_DREF_LVDET 3
#define I2C_ULP_DREF_LVDET_MSB 6
#define I2C_ULP_DREF_LVDET_LSB 4
#define I2C_ULP_XPD_LVDET 3
#define I2C_ULP_XPD_LVDET_MSB 7
#define I2C_ULP_XPD_LVDET_LSB 7
#define I2C_ULP_INT_XPD_XTAL_CK_DIG_REG 4
#define I2C_ULP_INT_XPD_XTAL_CK_DIG_REG_MSB 0
#define I2C_ULP_INT_XPD_XTAL_CK_DIG_REG_LSB 0
#define I2C_ULP_INT_XPD_XTAL_BUF 4
#define I2C_ULP_INT_XPD_XTAL_BUF_MSB 1
#define I2C_ULP_INT_XPD_XTAL_BUF_LSB 1
#define I2C_ULP_INT_XPD_RC_CK 4
#define I2C_ULP_INT_XPD_RC_CK_MSB 2
#define I2C_ULP_INT_XPD_RC_CK_LSB 2
#define I2C_ULP_XTAL_DPHASE 4
#define I2C_ULP_XTAL_DPHASE_MSB 3
#define I2C_ULP_XTAL_DPHASE_LSB 3
#define I2C_ULP_INT_XPD_XTAL_LIN_REG 4
#define I2C_ULP_INT_XPD_XTAL_LIN_REG_MSB 4
#define I2C_ULP_INT_XPD_XTAL_LIN_REG_LSB 4
#define I2C_ULP_XTAL_RESTART_DC_CAL 4
#define I2C_ULP_XTAL_RESTART_DC_CAL_MSB 5
#define I2C_ULP_XTAL_RESTART_DC_CAL_LSB 5
#define I2C_ULP_XTAL_DAC 5
#define I2C_ULP_XTAL_DAC_MSB 3
#define I2C_ULP_XTAL_DAC_LSB 0
#define I2C_ULP_XTAL_DBLEED 6
#define I2C_ULP_XTAL_DBLEED_MSB 4
#define I2C_ULP_XTAL_DBLEED_LSB 0
#define I2C_ULP_XTAL_CAL_DONE 6
#define I2C_ULP_XTAL_CAL_DONE_MSB 5
#define I2C_ULP_XTAL_CAL_DONE_LSB 5
#define I2C_ULP_ZOS_DONE 6
#define I2C_ULP_ZOS_DONE_MSB 6
#define I2C_ULP_ZOS_DONE_LSB 6

221
components/soc/esp32h2/include/soc/rtc.h
View File

@@ -54,12 +54,12 @@ extern "C" {
#define MHZ (1000000)
#define RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12)
#define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles) (cycles << 12)
#define RTC_SLOW_CLK_RC32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12)
#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10)
#define RTC_SLOW_CLK_FREQ_150K 150000
#define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_APPROX / 256)
#define RTC_SLOW_CLK_FREQ_150K 130000
#define RTC_SLOW_CLK_FREQ_32K 32768
#define RTC_SLOW_CLK_FREQ_RC32 32768
#define OTHER_BLOCKS_POWERUP 1
#define OTHER_BLOCKS_WAIT 1
@@ -68,14 +68,27 @@ extern "C" {
* RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
* Valid if RTC_CNTL_DBG_ATTEN is 0.
*/
#define RTC_CNTL_DBIAS_SLP 0 //sleep dig_dbias & rtc_dbias
#define RTC_CNTL_DBIAS_1V00 0
#define RTC_CNTL_DBIAS_1V05 4
#define RTC_CNTL_DBIAS_1V10 5
#define RTC_CNTL_DBIAS_1V15 6
#define RTC_CNTL_DBIAS_1V20 7
#define RTC_CNTL_DBIAS_SLP 0 //sleep dig_dbias & rtc_dbias
#define RTC_CNTL_DBIAS_1V00 0
#define RTC_CNTL_DBIAS_1V05 4
#define RTC_CNTL_DBIAS_1V10 5
#define RTC_CNTL_DBIAS_1V15 6
#define RTC_CNTL_DBIAS_1V20 7
#define RTC_CNTL_DBIAS_DEFAULT 8
/* The value of 1V00 can be adjusted between 0~3*/
/* dcdc mode
*/
#define RTC_CNTL_DCDC_TRX_MODE 0b100
#define RTC_CNTL_DCDC_LSLP_MODE 0b110
#define RTC_CNTL_DCDC_DSLP_MODE 0b101
#define RTC_CNTL_DCDC_FREQ_DEFAULT 3
#define DCDC_SLP_TRX_MODE 0
#define DCDC_SLP_LSLP_MODE 1
#define DCDC_SLP_DSLP_MODE 2
#define RTC_CNTL_DIG_DBIAS_0V85 0
#define RTC_CNTL_DIG_DBIAS_0V90 1
#define RTC_CNTL_DIG_DBIAS_0V95 2
@@ -105,8 +118,10 @@ extern "C" {
#define RTC_CNTL_CK8M_WAIT_DEFAULT 20
#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100
#define RTC_CNTL_SCK_DCAP_DEFAULT 255
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 600
#define RTC_CNTL_SCK_DCAP_DEFAULT 128
#define RTC_CNTL_RC32K_DFREQ_DEFAULT 707
/* Various delays to be programmed into power control state machines */
#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250)
@@ -138,28 +153,14 @@ typedef enum {
RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL
} rtc_xtal_freq_t;
/**
* @brief CPU frequency values
*/
typedef enum {
RTC_CPU_FREQ_XTAL = 0, //!< Main XTAL frequency
RTC_CPU_FREQ_80M = 1, //!< 80 MHz
RTC_CPU_FREQ_160M = 2, //!< 160 MHz
RTC_CPU_FREQ_240M = 3, //!< 240 MHz
RTC_CPU_FREQ_2M = 4, //!< 2 MHz
RTC_CPU_320M_80M = 5, //!< for test
RTC_CPU_320M_160M = 6, //!< for test
RTC_CPU_FREQ_XTAL_DIV2 = 7, //!< XTAL/2 after reset
} rtc_cpu_freq_t;
/**
* @brief CPU clock source
*/
typedef enum {
RTC_CPU_FREQ_SRC_XTAL, //!< XTAL
RTC_CPU_FREQ_SRC_PLL, //!< PLL (480M or 320M)
RTC_CPU_FREQ_SRC_8M, //!< Internal 8M RTC oscillator
RTC_CPU_FREQ_SRC_APLL //!< APLL
RTC_CPU_FREQ_SRC_PLL, //!< PLL (96M)
RTC_CPU_FREQ_SRC_8M, //!< Internal 18M RTC oscillator
RTC_CPU_FREQ_SRC_XTAL_D2 //!< XTAL/2
} rtc_cpu_freq_src_t;
/**
@@ -178,7 +179,7 @@ typedef struct rtc_cpu_freq_config_s {
typedef enum {
RTC_SLOW_FREQ_RTC = 0, //!< Internal 150 kHz RC oscillator
RTC_SLOW_FREQ_32K_XTAL = 1, //!< External 32 kHz XTAL
RTC_SLOW_FREQ_8MD256 = 2, //!< Internal 8 MHz RC oscillator, divided by 256
RTC_SLOW_FREQ_RC32K = 2, //!< Internal 32 KHz RC oscillator
} rtc_slow_freq_t;
/**
@@ -202,7 +203,7 @@ typedef enum {
*/
typedef enum {
RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK
RTC_CAL_8MD256 = 1, //!< Internal 8 MHz RC oscillator, divided by 256
RTC_CAL_RC32K = 1, //!< Internal 32 kHz RC oscillator
RTC_CAL_32K_XTAL = 2 //!< External 32 kHz XTAL
} rtc_cal_sel_t;
@@ -217,21 +218,23 @@ typedef struct {
uint32_t clk_rtc_clk_div : 8;
uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency)
uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency)
uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency)
uint32_t clk_8m_dfreq : 10; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency)
uint32_t root_clk_slt : 2; //!< Select clock root source for esp32h2 (default 0: xtal_32M)
} rtc_clk_config_t;
/**
* Default initializer for rtc_clk_config_t
*/
#define RTC_CLK_CONFIG_DEFAULT() { \
.xtal_freq = RTC_XTAL_FREQ_40M, \
.cpu_freq_mhz = 80, \
.xtal_freq = RTC_XTAL_FREQ_32M, \
.cpu_freq_mhz = 32, \
.fast_freq = RTC_FAST_FREQ_8M, \
.slow_freq = RTC_SLOW_FREQ_RTC, \
.clk_rtc_clk_div = 0, \
.clk_8m_clk_div = 0, \
.clk_rtc_clk_div = 1, \
.clk_8m_clk_div = 1, \
.slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \
.clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
.root_clk_slt = 0, \
}
typedef struct {
@@ -241,6 +244,7 @@ typedef struct {
uint32_t dbuf: 1;
} x32k_config_t;
#define X32K_CONFIG_DEFAULT() { \
.dac = 3, \
.dres = 3, \
@@ -248,6 +252,14 @@ typedef struct {
.dbuf = 1, \
}
typedef struct {
uint32_t dfreq : 10;
} rc32k_config_t;
#define RC32K_CONFIG_DEFAULT() {\
.dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT,\
}
typedef struct {
uint16_t wifi_powerup_cycles : 7;
uint16_t wifi_wait_cycles : 9;
@@ -499,6 +511,10 @@ void rtc_clk_apb_freq_update(uint32_t apb_freq);
*/
uint32_t rtc_clk_apb_freq_get(void);
void rtc_clk_cpu_freq_set(uint32_t source, uint32_t div);
uint32_t rtc_clk_ahb_freq_get(void);
uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles);
/**
@@ -633,7 +649,7 @@ typedef struct {
uint32_t rtc_fastmem_pd_en : 1; //!< power down RTC fast memory
uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory
uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals
uint32_t wifi_pd_en : 1; //!< power down WiFi
uint32_t dig_ret_pd_en : 1; //!< power down dig_ret
uint32_t bt_pd_en : 1; //!< power down BT
uint32_t cpu_pd_en : 1; //!< power down CPU, but not restart when lightsleep.
uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals
@@ -662,7 +678,7 @@ typedef struct {
.rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \
.rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \
.rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \
.wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \
.dig_ret_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_RET) ? 1 : 0, \
.bt_pd_en = ((sleep_flags) & RTC_SLEEP_PD_BT) ? 1 : 0, \
.cpu_pd_en = ((sleep_flags) & RTC_SLEEP_PD_CPU) ? 1 : 0, \
.dig_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, \
@@ -683,7 +699,7 @@ typedef struct {
#define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) //!< Power down RTC FAST memory
#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU
#define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator
#define RTC_SLEEP_PD_WIFI BIT(6) //!< Power down WIFI
#define RTC_SLEEP_PD_DIG_RET BIT(6) //!< Power down WIFI
#define RTC_SLEEP_PD_BT BIT(7) //!< Power down BT
#define RTC_SLEEP_PD_CPU BIT(8) //!< Power down CPU when in lightsleep, but not restart
#define RTC_SLEEP_PD_DIG_PERIPH BIT(9) //!< Power down DIG peripherals
@@ -791,11 +807,11 @@ typedef struct {
uint32_t pll_wait : 8; //!< Number of rtc_fast_clk cycles to wait for PLL to be ready
uint32_t clkctl_init : 1; //!< Perform clock control related initialization
uint32_t pwrctl_init : 1; //!< Perform power control related initialization
uint32_t rtc_dboost_fpd : 1; //!< Force power down RTC_DBOOST
uint32_t xtal_fpu : 1;
uint32_t bbpll_fpu : 1;
uint32_t cpu_waiti_clk_gate : 1;
uint32_t cali_ocode : 1; //!< Calibrate Ocode to make bangap voltage more precise.
uint32_t pmu_ctl : 1;
} rtc_config_t;
/**
@@ -810,17 +826,93 @@ typedef struct {
.pll_wait = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \
.clkctl_init = 1, \
.pwrctl_init = 1, \
.rtc_dboost_fpd = 1, \
.xtal_fpu = 0, \
.bbpll_fpu = 0, \
.cpu_waiti_clk_gate = 1, \
.cali_ocode = 0\
.cali_ocode = 0, \
.pmu_ctl = 1\
}
typedef struct {
/* data */
uint32_t or_en_cont_cal : 1; //!< default:0 rtc_init:0 pvt can be enable by either this register or digital -- if_en_cont_cal
uint32_t enx_rtc_dreg : 1; //!< default:1 rtc_init:1 use i2c registers to configure rtc regulator voltage level instead of pvt result -- int_dreg
uint32_t enx_dig_dreg : 1; //!< default:1 rtc_init:1 use i2c registers to configure dig regulator voltage level instead of pvt result -- int_dreg
uint32_t en_i2c_rtc_dreg : 1; //!< default:1 rtc_init:0 1: i2c_rtc_dreg; 0: if_rtc_dreg
uint32_t en_i2c_dig_dreg : 1; //!< default:1 rtc_init:0 1: i2c_dig_dreg; 0: if_dig_dreg
uint32_t en_i2c_rtc_dreg_slp : 1; //!< default:1 rtc_init:0 1: i2c_rtc_dreg_slp; 0: if_rtc_dreg_slp
uint32_t en_i2c_dig_dreg_slp : 1; //!< default:1 rtc_init:0 1: i2c_dig_dreg_slp; 0: if_dig_dreg_slp
uint32_t or_xpd_rtc_slave_3p3 : 1; //!< default:1 rtc_init:0 to turn off rtc slave, which is only required before DCDC running
uint32_t or_xpd_rtc_reg : 1; //!< default:1 rtc_init:0 handover control to digital -- if_xpd_rtc_reg
uint32_t or_xpd_dig_reg : 1; //!< default:1 rtc_init:0 handover control to digital -- if_xpd_dig_reg
uint32_t or_pd_rtc_reg_slp : 1; //!< default:0 rtc_init:1 configure this i2c to control rtc_sleep_regulator on off, no coressponding digital control signal
uint32_t or_pd_dig_reg_slp : 1; //!< default:0 rtc_init:0 default value 0 puts dig_sleep_regulator controlled by digital -- if_xpd_dig_reg_slp
uint32_t or_xpd_dcdc : 1; //!< default:1 rtc_init:0 handover control to digital -- if_xpd_dcdc
uint32_t or_disalbe_deep_sleep_dcdc : 1; //!< default:1 rtc_init:0 handover control to digital -- if_enable_deep_sleep_dcdc
uint32_t or_disalbe_light_sleep_dcdc : 1; //!< default:1 rtc_init:0 handover control to digital -- if_enable_light_sleep_dcdc
uint32_t or_enalbe_trx_mode_dcdc : 1; //!< default:1 rtc_init:0 handover control to digital -- if_enable_trx_mode_dcdc
uint32_t or_enx_reg_dcdc : 1; //!< default:0 rtc_init:1 handover dcdc configuration registers to digital control signals, including popenb, sstime, ccm, vset, fsw, dcmlevel, dcm2enb, ramp, ramplevel
uint32_t or_unlock_dcdc : 1; //!< default:0 rtc_init:0 not used in this version of silicon, can be unleashed if metal change if_vgood_lock_dcdc signal to high
uint32_t or_force_lock_dcdc : 1; //!< default:0 rtc_init:0 dcdc will be locked and shut-off if this register sets to 1
uint32_t or_enb_slow_clk : 1; //!< default:0 rtc_init:1 handover slow clock control to digital -- if_enb_slow_clk
uint32_t or_xpd_trx : 1; //!< default:1 rtc_init:0 handover trx control to digital -- if_xpd_trx
uint32_t or_en_reset_chip : 1; //!< default:0 rtc_init:1 handover reset chip control to digital -- if_reset_chip
uint32_t or_force_xpd_reg_slave : 1; //!< default:0 rtc_init:1 set this reg to 1 after DCDC ready, to have rtc & dig slave control independent of DCDC status
} pmu_config_t;
#define PMU_CONFIG_DEFAULT() {\
.or_en_cont_cal = 0, \
.enx_rtc_dreg = 1, \
.enx_dig_dreg = 1, \
.en_i2c_rtc_dreg = 0, \
.en_i2c_dig_dreg = 0, \
.en_i2c_rtc_dreg_slp = 0, \
.en_i2c_dig_dreg_slp = 0, \
.or_xpd_rtc_slave_3p3 = 0, \
.or_xpd_rtc_reg = 0, \
.or_xpd_dig_reg = 0, \
.or_pd_rtc_reg_slp = 0, \
.or_pd_dig_reg_slp = 0, \
.or_xpd_dcdc = 0, \
.or_disalbe_deep_sleep_dcdc = 0, \
.or_disalbe_light_sleep_dcdc = 0, \
.or_enalbe_trx_mode_dcdc = 0, \
.or_enx_reg_dcdc = 1, \
.or_unlock_dcdc = 0, \
.or_force_lock_dcdc = 0, \
.or_xpd_trx = 0, \
.or_en_reset_chip = 1, \
.or_force_xpd_reg_slave = 1\
}
typedef struct {
uint32_t swt_idle: 1; //!< If 1, swt_idle is sleep mode ; if 0, swt_idle is active mode
uint32_t swt_monitor: 1; //!< If 1, swt_monitor is sleep mode ; if 0, swt_monitor is active mode
uint32_t swt_slp: 1; //!< If 1, swt_slp is sleep mode ; if 0, swt_slp is active mode
} dbias_swt_cfg_t;
#define DBIAS_SWITCH_CONFIG_DEFAULT(){\
.swt_idle = 0, \
.swt_monitor = 1, \
.swt_slp = 1\
}
typedef struct {
/* data */
uint32_t dig_regul0_en: 1; //!< If 1, dig_regulator0 is ctl by fsm; if 0, dig_regulator0 force pd.
uint32_t dig_regul1_en: 1; //!< If 1, dig_regulator1 is ctl by fsm; if 0, dig_regulator1 force pd.
uint32_t rtc_regul0_en: 1; //!< If 1, rtc_regulator0 is ctl by fsm; if 0, rtc_regulator0 force pd.
} regulator_cfg_t;
#define REGULATOR_SET_DEFAULT(){\
.dig_regul0_en = 1, \
.dig_regul1_en = 1, \
.rtc_regul0_en = 1, \
}
/**
* Initialize RTC clock and power control related functions
* @param cfg configuration options as rtc_config_t
*/
* Initialize RTC clock and power control related functions
* @param cfg configuration options as rtc_config_t
*/
void rtc_init(rtc_config_t cfg);
/**
@@ -853,6 +945,47 @@ rtc_vddsdio_config_t rtc_vddsdio_get_config(void);
*/
void rtc_vddsdio_set_config(rtc_vddsdio_config_t config);
/* Select clock root source for esp32h2. return source clk freq_mhz
*/
uint32_t root_clk_slt(uint32_t source);
uint32_t root_clk_get(void);
/**
* Regulator config
*/
typedef struct {
uint32_t dig_source : 1;
uint32_t dig_active_dbias : 5;
uint32_t dig_slp_dbias : 5;
uint32_t rtc_source : 1;
uint32_t rtc_active_dbias : 5;
uint32_t rtc_slp_dbias : 5;
} regulator_config_t;
#define REGULATOR0_CONFIG_DEFAULT() {\
.dig_source = 0, \
.dig_active_dbias = 20, \
.dig_slp_dbias = 8, \
.rtc_source = 0, \
.rtc_active_dbias = 20, \
.rtc_slp_dbias = 8 \
}
#define REGULATOR1_CONFIG_DEFAULT() {\
.dig_source = 1, \
.dig_active_dbias = 15, \
.dig_slp_dbias = 8, \
.rtc_source = 1, \
.rtc_active_dbias = 15, \
.rtc_slp_dbias = 8 \
}
/**
* gpio hangup
*/
void rtc_gpio_hangup(uint32_t gpio_no);
#ifdef __cplusplus
}
#endif

10
components/soc/esp32h2/include/soc/soc_caps.h
View File

@@ -245,9 +245,6 @@
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
/*-------------------------- WI-FI HARDWARE TSF CAPS -------------------------------*/
#define SOC_WIFI_HW_TSF (1)
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)
@@ -255,16 +252,9 @@
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
#define SOC_MAC_BB_PD_MEM_SIZE (192*4)
/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/
#define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12)
/*-------------------------- Power Management CAPS ----------------------------*/
#define SOC_PM_SUPPORT_WIFI_WAKEUP (1)
#define SOC_PM_SUPPORT_BT_WAKEUP (1)
#define SOC_PM_SUPPORT_CPU_PD (1)
#define SOC_PM_SUPPORT_WIFI_PD (1)
#define SOC_PM_SUPPORT_BT_PD (1)