feat(esp_hw_support): add clk tree source gate management api

components/esp_driver_gptimer/src/gptimer_common.c

@@ -6,8 +6,10 @@
 
 #include "esp_check.h"
 #include "esp_clk_tree.h"
+#include "esp_private/esp_clk_tree_common.h"
 #include "esp_private/gptimer.h"
 #include "gptimer_priv.h"
+#include "soc/soc_caps.h"
 
 static const char *TAG = "gptimer";
 
@@ -196,6 +198,7 @@ esp_err_t gptimer_select_periph_clock(gptimer_t *timer, gptimer_clock_source_t s
     }
 #endif // CONFIG_PM_ENABLE
 
+    esp_clk_tree_enable_src((soc_module_clk_t)src_clk, true);
     // !!! HARDWARE SHARED RESOURCE !!!
     // on some ESP chip, different peripheral's clock source setting are mixed in the same register
     // so we need to make this done in an atomic way