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Merge branch 'feat/c61_enable_ci_build_test' into 'master'

Browse Source 
feat(esp32c61): enable c61 ci build test

Closes IDF-9289

See merge request espressif/esp-idf!30448
This commit is contained in:
Wan Lei
2024-07-17 09:33:31 +08:00
parent fcd0b82c1c 3cf069c7d8
commit 146d07dacf
134 changed files with 454 additions and 743 deletions
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344
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
View File

@@ -223,138 +223,14 @@ config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
bool
default y
config SOC_I2C_NUM
int
default 1
config SOC_HP_I2C_NUM
int
default 1
config SOC_I2C_FIFO_LEN
int
default 32
config SOC_I2C_CMD_REG_NUM
int
default 8
config SOC_I2C_SUPPORT_SLAVE
bool
default y
config SOC_I2C_SUPPORT_HW_FSM_RST
bool
default y
config SOC_I2C_SUPPORT_HW_CLR_BUS
bool
default y
config SOC_I2C_SUPPORT_XTAL
bool
default y
config SOC_I2C_SUPPORT_RTC
bool
default y
config SOC_I2C_SUPPORT_10BIT_ADDR
bool
default y
config SOC_I2C_SLAVE_SUPPORT_BROADCAST
bool
default y
config SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
bool
default y
config SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS
bool
default y
config SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH
bool
default y
config SOC_LP_I2C_NUM
int
default 1
config SOC_LP_I2C_FIFO_LEN
int
default 16
config SOC_I2S_NUM
int
default 1
config SOC_I2S_HW_VERSION_2
bool
default y
config SOC_I2S_SUPPORTS_XTAL
bool
default y
config SOC_I2S_SUPPORTS_PLL_F160M
bool
default y
config SOC_I2S_SUPPORTS_PCM
bool
default y
config SOC_I2S_SUPPORTS_PDM
bool
default y
config SOC_I2S_SUPPORTS_PDM_TX
bool
default y
config SOC_I2S_PDM_MAX_TX_LINES
int
default 2
config SOC_I2S_SUPPORTS_TDM
bool
default y
config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
bool
default y
config SOC_LEDC_SUPPORT_XTAL_CLOCK
bool
default y
config SOC_LEDC_CHANNEL_NUM
int
default 6
config SOC_LEDC_TIMER_BIT_WIDTH
int
default 20
config SOC_LEDC_SUPPORT_FADE_STOP
bool
default y
config SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED
bool
default y
config SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX
int
default 16
config SOC_LEDC_FADE_PARAMS_BIT_WIDTH
int
default 10
config SOC_MMU_PAGE_SIZE_CONFIGURABLE
bool
default y
@@ -391,78 +267,6 @@ config SOC_MPU_REGION_WO_SUPPORTED
bool
default n
config SOC_PCNT_GROUPS
int
default 1
config SOC_PCNT_UNITS_PER_GROUP
int
default 4
config SOC_PCNT_CHANNELS_PER_UNIT
int
default 2
config SOC_PCNT_THRES_POINT_PER_UNIT
int
default 2
config SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE
bool
default y
config SOC_MCPWM_GROUPS
int
default 1
config SOC_MCPWM_TIMERS_PER_GROUP
int
default 3
config SOC_MCPWM_OPERATORS_PER_GROUP
int
default 3
config SOC_MCPWM_COMPARATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_GENERATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_TRIGGERS_PER_OPERATOR
int
default 2
config SOC_MCPWM_GPIO_FAULTS_PER_GROUP
int
default 3
config SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP
bool
default y
config SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER
int
default 3
config SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP
int
default 3
config SOC_MCPWM_SWSYNC_CAN_PROPAGATE
bool
default y
config SOC_MCPWM_SUPPORT_ETM
bool
default y
config SOC_MCPWM_CAPTURE_CLK_FROM_GROUP
bool
default y
config SOC_MPI_MEM_BLOCKS_NUM
int
default 4
@@ -475,34 +279,6 @@ config SOC_RSA_MAX_BIT_LEN
int
default 3072
config SOC_SHA_DMA_MAX_BUFFER_SIZE
int
default 3968
config SOC_SHA_SUPPORT_DMA
bool
default y
config SOC_SHA_SUPPORT_RESUME
bool
default y
config SOC_SHA_GDMA
bool
default y
config SOC_SHA_SUPPORT_SHA1
bool
default y
config SOC_SHA_SUPPORT_SHA224
bool
default y
config SOC_SHA_SUPPORT_SHA256
bool
default y
config SOC_SPI_PERIPH_NUM
int
default 2
@@ -511,46 +287,10 @@ config SOC_SPI_MAX_CS_NUM
int
default 6
config SOC_SPI_MAXIMUM_BUFFER_SIZE
int
default 64
config SOC_SPI_SUPPORT_DDRCLK
bool
default y
config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
bool
default y
config SOC_SPI_SUPPORT_CD_SIG
bool
default y
config SOC_SPI_SUPPORT_CONTINUOUS_TRANS
bool
default y
config SOC_SPI_SUPPORT_CLK_XTAL
bool
default y
config SOC_SPI_SUPPORT_CLK_PLL_F80M
bool
default y
config SOC_SPI_SUPPORT_CLK_RC_FAST
bool
default y
config SOC_MEMSPI_IS_INDEPENDENT
bool
default y
config SOC_SPI_MAX_PRE_DIVIDER
int
default 16
config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE
bool
default y
@@ -623,10 +363,6 @@ config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
bool
default y
config SOC_SYSTIMER_SUPPORT_ETM
bool
default y
config SOC_LP_TIMER_BIT_WIDTH_LO
int
default 32
@@ -643,6 +379,10 @@ config SOC_TIMER_GROUP_TIMERS_PER_GROUP
int
default 1
config SOC_TIMER_GROUP_TOTAL_TIMERS
int
default 2
config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
int
default 54
@@ -651,42 +391,6 @@ config SOC_TIMER_GROUP_SUPPORT_XTAL
bool
default y
config SOC_TIMER_GROUP_SUPPORT_RC_FAST
bool
default y
config SOC_TIMER_GROUP_TOTAL_TIMERS
int
default 2
config SOC_TIMER_SUPPORT_ETM
bool
default y
config SOC_MWDT_SUPPORT_XTAL
bool
default y
config SOC_TWAI_CONTROLLER_NUM
int
default 2
config SOC_TWAI_CLK_SUPPORT_XTAL
bool
default y
config SOC_TWAI_BRP_MIN
int
default 2
config SOC_TWAI_BRP_MAX
int
default 32768
config SOC_TWAI_SUPPORTS_RX_STATUS
bool
default y
config SOC_EFUSE_DIS_DOWNLOAD_ICACHE
bool
default n
@@ -883,10 +587,6 @@ config SOC_PM_PAU_LINK_NUM
int
default 4
config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
bool
default y
config SOC_MODEM_CLOCK_IS_INDEPENDENT
bool
default y
@@ -907,42 +607,6 @@ config SOC_RCC_IS_INDEPENDENT
bool
default y
config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC
bool
default y
config SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL
bool
default y
config SOC_TEMPERATURE_SENSOR_INTR_SUPPORT
bool
default y
config SOC_WIFI_HW_TSF
bool
default y
config SOC_WIFI_FTM_SUPPORT
bool
default n
config SOC_WIFI_GCMP_SUPPORT
bool
default y
config SOC_WIFI_WAPI_SUPPORT
bool
default y
config SOC_WIFI_CSI_SUPPORT
bool
default y
config SOC_WIFI_HE_SUPPORT
bool
default y
config SOC_PHY_COMBO_MODULE
bool
default y

183
components/soc/esp32c61/include/soc/soc_caps.h
View File

@@ -232,50 +232,51 @@
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-C61 has 1 I2C
#define SOC_I2C_NUM (1U)
#define SOC_HP_I2C_NUM (1U)
// #define SOC_I2C_NUM (1U)
// #define SOC_HP_I2C_NUM (1U)
#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
#define SOC_I2C_CMD_REG_NUM (8) /*!< Number of I2C command registers */
#define SOC_I2C_SUPPORT_SLAVE (1)
// #define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
// #define SOC_I2C_CMD_REG_NUM (8) /*!< Number of I2C command registers */
// #define SOC_I2C_SUPPORT_SLAVE (1)
#define SOC_I2C_SUPPORT_HW_FSM_RST (1)
#define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
// #define SOC_I2C_SUPPORT_HW_FSM_RST (1)
// #define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
#define SOC_I2C_SUPPORT_XTAL (1)
#define SOC_I2C_SUPPORT_RTC (1)
#define SOC_I2C_SUPPORT_10BIT_ADDR (1)
#define SOC_I2C_SLAVE_SUPPORT_BROADCAST (1)
#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1)
#define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS (1)
#define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH (1)
// #define SOC_I2C_SUPPORT_XTAL (1)
// #define SOC_I2C_SUPPORT_RTC (1)
// #define SOC_I2C_SUPPORT_10BIT_ADDR (1)
// #define SOC_I2C_SLAVE_SUPPORT_BROADCAST (1)
// #define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1)
// #define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS (1)
// #define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH (1)
/*-------------------------- LP_I2C CAPS -------------------------------------*/
// ESP32-C61 has 1 LP_I2C
#define SOC_LP_I2C_NUM (1U)
// #define SOC_LP_I2C_NUM (1U)
#define SOC_LP_I2C_FIFO_LEN (16) /*!< LP_I2C hardware FIFO depth */
// #define SOC_LP_I2C_FIFO_LEN (16) /*!< LP_I2C hardware FIFO depth */
/*-------------------------- I2S CAPS ----------------------------------------*/
#define SOC_I2S_NUM (1U)
#define SOC_I2S_HW_VERSION_2 (1)
#define SOC_I2S_SUPPORTS_XTAL (1)
#define SOC_I2S_SUPPORTS_PLL_F160M (1)
#define SOC_I2S_SUPPORTS_PCM (1)
#define SOC_I2S_SUPPORTS_PDM (1)
#define SOC_I2S_SUPPORTS_PDM_TX (1)
#define SOC_I2S_PDM_MAX_TX_LINES (2)
#define SOC_I2S_SUPPORTS_TDM (1)
// /*-------------------------- I2S CAPS ----------------------------------------*/
// #define SOC_I2S_NUM (1U)
// #define SOC_I2S_HW_VERSION_2 (1)
// #define SOC_I2S_SUPPORTS_XTAL (1)
// #define SOC_I2S_SUPPORTS_PLL_F160M (1)
// #define SOC_I2S_SUPPORTS_PCM (1)
// #define SOC_I2S_SUPPORTS_PDM (1)
// #define SOC_I2S_SUPPORTS_PDM_TX (1)
// #define SOC_I2S_PDM_MAX_TX_LINES (2)
// #define SOC_I2S_SUPPORTS_TDM (1)
/*-------------------------- LEDC CAPS ---------------------------------------*/
//TODO: [ESP32C61] IDF-9291
#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)
#define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
// #define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
#define SOC_LEDC_CHANNEL_NUM (6)
#define SOC_LEDC_TIMER_BIT_WIDTH (20)
#define SOC_LEDC_SUPPORT_FADE_STOP (1)
#define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1)
#define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16)
#define SOC_LEDC_FADE_PARAMS_BIT_WIDTH (10)
// #define SOC_LEDC_TIMER_BIT_WIDTH (20)
// #define SOC_LEDC_SUPPORT_FADE_STOP (1)
// #define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1)
// #define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16)
// #define SOC_LEDC_FADE_PARAMS_BIT_WIDTH (10)
/*-------------------------- MMU CAPS ----------------------------------------*/
#define SOC_MMU_PAGE_SIZE_CONFIGURABLE (1)
@@ -291,26 +292,26 @@
#define SOC_MPU_REGION_WO_SUPPORTED 0
/*-------------------------- PCNT CAPS ---------------------------------------*/
#define SOC_PCNT_GROUPS 1U
#define SOC_PCNT_UNITS_PER_GROUP 4
#define SOC_PCNT_CHANNELS_PER_UNIT 2
#define SOC_PCNT_THRES_POINT_PER_UNIT 2
#define SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE 1
// #define SOC_PCNT_GROUPS 1U
// #define SOC_PCNT_UNITS_PER_GROUP 4
// #define SOC_PCNT_CHANNELS_PER_UNIT 2
// #define SOC_PCNT_THRES_POINT_PER_UNIT 2
// #define SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE 1
/*-------------------------- MCPWM CAPS --------------------------------------*/
#define SOC_MCPWM_GROUPS (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
#define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
#define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
#define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
#define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has
#define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has
#define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of fault signal detectors that each group has
#define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
#define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has
#define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output
#define SOC_MCPWM_SUPPORT_ETM (1) ///< Support ETM (Event Task Matrix)
#define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP (1) ///< Capture timer shares clock with other PWM timers
// #define SOC_MCPWM_GROUPS (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
// #define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
// #define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
// #define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
// #define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has
// #define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has
// #define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of fault signal detectors that each group has
// #define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
// #define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
// #define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has
// #define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output
// #define SOC_MCPWM_SUPPORT_ETM (1) ///< Support ETM (Event Task Matrix)
// #define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP (1) ///< Capture timer shares clock with other PWM timers
/*------------------------ USB SERIAL JTAG CAPS ------------------------------*/
// \#define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
@@ -330,42 +331,42 @@
for SHA this means that the biggest safe amount of bytes is
31 blocks of 128 bytes = 3968
*/
#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
#define SOC_SHA_SUPPORT_DMA (1)
// #define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
// #define SOC_SHA_SUPPORT_DMA (1)
/* The SHA engine is able to resume hashing from a user */
#define SOC_SHA_SUPPORT_RESUME (1)
// /* The SHA engine is able to resume hashing from a user */
// #define SOC_SHA_SUPPORT_RESUME (1)
/* Has a centralized DMA, which is shared with all peripherals */
#define SOC_SHA_GDMA (1)
// /* Has a centralized DMA, which is shared with all peripherals */
// #define SOC_SHA_GDMA (1)
/* Supported HW algorithms */
#define SOC_SHA_SUPPORT_SHA1 (1)
#define SOC_SHA_SUPPORT_SHA224 (1)
#define SOC_SHA_SUPPORT_SHA256 (1)
// /* Supported HW algorithms */
// #define SOC_SHA_SUPPORT_SHA1 (1)
// #define SOC_SHA_SUPPORT_SHA224 (1)
// #define SOC_SHA_SUPPORT_SHA256 (1)
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 2
#define SOC_SPI_PERIPH_CS_NUM(i) 6
#define SOC_SPI_MAX_CS_NUM 6
#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
// #define SOC_SPI_MAX_PRE_DIVIDER 16
// #define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
#define SOC_SPI_SUPPORT_DDRCLK 1
#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
#define SOC_SPI_SUPPORT_CD_SIG 1
#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
// #define SOC_SPI_SUPPORT_DDRCLK 1
// #define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
// #define SOC_SPI_SUPPORT_CD_SIG 1
// #define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
// #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 // TODO : [ESP32C61] IDF-9301
#define SOC_SPI_SUPPORT_CLK_XTAL 1
#define SOC_SPI_SUPPORT_CLK_PLL_F80M 1
#define SOC_SPI_SUPPORT_CLK_RC_FAST 1
// #define SOC_SPI_SUPPORT_CLK_XTAL 1
// #define SOC_SPI_SUPPORT_CLK_PLL_F80M 1
// #define SOC_SPI_SUPPORT_CLK_RC_FAST 1
// Peripheral supports DIO, DOUT, QIO, or QOUT
// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
// // Peripheral supports DIO, DOUT, QIO, or QOUT
// // host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;})
#define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_SPI_MAX_PRE_DIVIDER 16
/*-------------------------- SPI MEM CAPS ---------------------------------------*/
#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
@@ -389,7 +390,7 @@
#define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source
#define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt
#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
#define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event
// #define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
@@ -398,21 +399,21 @@
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_GROUPS (2)
#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U)
#define SOC_TIMER_GROUP_TOTAL_TIMERS (2)
#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
#define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1)
#define SOC_TIMER_GROUP_TOTAL_TIMERS (2)
#define SOC_TIMER_SUPPORT_ETM (1)
// #define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1)
// #define SOC_TIMER_SUPPORT_ETM (1)
/*--------------------------- WATCHDOG CAPS ---------------------------------------*/
#define SOC_MWDT_SUPPORT_XTAL (1)
// #define SOC_MWDT_SUPPORT_XTAL (1)
/*-------------------------- TWAI CAPS ---------------------------------------*/
#define SOC_TWAI_CONTROLLER_NUM 2
#define SOC_TWAI_CLK_SUPPORT_XTAL 1
#define SOC_TWAI_BRP_MIN 2
#define SOC_TWAI_BRP_MAX 32768
#define SOC_TWAI_SUPPORTS_RX_STATUS 1
// #define SOC_TWAI_CONTROLLER_NUM 2
// #define SOC_TWAI_CLK_SUPPORT_XTAL 1
// #define SOC_TWAI_BRP_MIN 2
// #define SOC_TWAI_BRP_MAX 32768
// #define SOC_TWAI_SUPPORTS_RX_STATUS 1
/*-------------------------- eFuse CAPS----------------------------*/
@@ -502,7 +503,7 @@
#define SOC_PM_PAU_LINK_NUM (4)
/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
// #define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1) //TODO: [ESP32C61] IDF-9249
#define SOC_MODEM_CLOCK_IS_INDEPENDENT (1)
#define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */
@@ -512,18 +513,18 @@
#define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control is independent, thanks to the PCR registers */
/*-------------------------- Temperature Sensor CAPS -------------------------------------*/
#define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1)
#define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL (1)
#define SOC_TEMPERATURE_SENSOR_INTR_SUPPORT (1)
// #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1)
// #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL (1)
// #define SOC_TEMPERATURE_SENSOR_INTR_SUPPORT (1)
/*------------------------------------ WI-FI CAPS ------------------------------------*/
#define SOC_WIFI_HW_TSF (1) /*!< Support hardware TSF */
#define SOC_WIFI_FTM_SUPPORT (0) /*!< Support FTM */
#define SOC_WIFI_GCMP_SUPPORT (1) /*!< Support GCMP(GCMP128 and GCMP256) */
#define SOC_WIFI_WAPI_SUPPORT (1) /*!< Support WAPI */
#define SOC_WIFI_CSI_SUPPORT (1) /*!< Support CSI */
// #define SOC_WIFI_HW_TSF (1) /*!< Support hardware TSF */
// #define SOC_WIFI_FTM_SUPPORT (0) /*!< Support FTM */
// #define SOC_WIFI_GCMP_SUPPORT (1) /*!< Support GCMP(GCMP128 and GCMP256) */
// #define SOC_WIFI_WAPI_SUPPORT (1) /*!< Support WAPI */
// #define SOC_WIFI_CSI_SUPPORT (1) /*!< Support CSI */
// #define SOC_WIFI_MESH_SUPPORT (1) /*!< Support WIFI MESH */
#define SOC_WIFI_HE_SUPPORT (1) /*!< Support Wi-Fi 6 */
// #define SOC_WIFI_HE_SUPPORT (1) /*!< Support Wi-Fi 6 */
/*---------------------------------- Bluetooth CAPS ----------------------------------*/
// \#define SOC_BLE_SUPPORTED (1) /*!< Support Bluetooth Low Energy hardware */