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feat(p4): p4 rev3 real chip support
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@@ -74,7 +74,7 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
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/**
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* Register the shared buffer area of the last memory block into the heap during heap initialization
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*/
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#if CONFIG_ESP32P4_SELECTS_REV_LESS_V2
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#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
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#define ROM_STACK_START (SOC_ROM_STACK_START)
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#define APP_USABLE_DIRAM_END (ROM_STACK_START - SOC_ROM_STACK_SIZE) // 0x4ff3cfc0 - 0x2000 = 0x4ff3afc0
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#define STARTUP_DATA_SIZE (SOC_DRAM_HIGH - CONFIG_CACHE_L2_CACHE_SIZE - APP_USABLE_DIRAM_END) // 0x4ffc0000 - 0x20000/0x40000/0x80000 - 0x4ff3afc0 = 0x65040 / 0x45040 / 0x5040
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@@ -108,7 +108,7 @@ const soc_memory_region_t soc_memory_regions[] = {
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const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
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#if CONFIG_ESP32P4_SELECTS_REV_LESS_V2
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#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
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extern int _data_start_low, _data_start_high, _heap_start_low, _heap_start_high, _iram_start, _iram_end, _rtc_force_slow_end;
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#else
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extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end;
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@@ -124,7 +124,7 @@ extern int _rtc_ulp_memory_start;
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*/
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// Static data region. DRAM used by data+bss and possibly rodata
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#if CONFIG_ESP32P4_SELECTS_REV_LESS_V2
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#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
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SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start_low, (intptr_t)&_heap_start_low, dram_data_low);
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SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start_high, (intptr_t)&_heap_start_high, dram_data_high);
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#else
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