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feat(p4): p4 rev3 real chip support

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This commit is contained in:
armando
2025-08-20 14:30:35 +08:00
parent d4a821a03e
commit 179d00a6f8
259 changed files with 91 additions and 58 deletions
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4
components/riscv/include/esp_private/interrupt_clic.h
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@@ -47,7 +47,7 @@ extern "C" {
#define UTVT_CSR 0x007
#if CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_SELECTS_REV_LESS_V2
#if CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_SELECTS_REV_LESS_V3
/**
* The ESP32-P4 and the beta version of the ESP32-C5 implement a non-standard version of the CLIC:
@@ -57,7 +57,7 @@ extern "C" {
#define INTTHRESH_STANDARD 0
#define MINTSTATUS_CSR 0x346
#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H4 || !CONFIG_ESP32P4_SELECTS_REV_LESS_V2
#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H4 || !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
/* The ESP32-C5 (MP), C61, H4 and P4 (since REV2) use the standard CLIC specification, for example, it defines the mintthresh CSR */
#define INTTHRESH_STANDARD 1