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soc: add esp32s3 sdmmc support

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* sync the latest struct header file from ESP32
* add soc_caps.h macros to distinguish between IO MUX and GPIO Matrix
  support in SDMMC on different chips.
* store GPIO matrix signal numbers in sdmmc_slot_info_t
This commit is contained in:
Ivan Grokhotkov
2021-01-04 20:34:31 +01:00
parent bd3a6dda87
commit 17c65dad27
8 changed files with 150 additions and 90 deletions
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22
components/soc/esp32s3/include/soc/sdmmc_pins.h
View File

@@ -14,22 +14,6 @@
#pragma once
#define SDMMC_SLOT0_IOMUX_PIN_NUM_CLK 6
#define SDMMC_SLOT0_IOMUX_PIN_NUM_CMD 11
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D0 7
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D1 8
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D2 9
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D3 10
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D4 16
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D5 17
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D6 5
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D7 18
#define SDMMC_SLOT0_FUNC 0
#define SDMMC_SLOT1_IOMUX_PIN_NUM_CLK 14
#define SDMMC_SLOT1_IOMUX_PIN_NUM_CMD 15
#define SDMMC_SLOT1_IOMUX_PIN_NUM_D0 2
#define SDMMC_SLOT1_IOMUX_PIN_NUM_D1 4
#define SDMMC_SLOT1_IOMUX_PIN_NUM_D2 12
#define SDMMC_SLOT1_IOMUX_PIN_NUM_D3 13
#define SDMMC_SLOT1_FUNC 4
/* SDMMC pins on ESP32-S3 are configurable through GPIO matrix.
* This file is kept for compatibility only.
*/

34
components/soc/esp32s3/include/soc/sdmmc_struct.h
View File

@@ -19,7 +19,7 @@
extern "C" {
#endif
typedef struct {
typedef struct sdmmc_desc_s {
uint32_t reserved1: 1;
uint32_t disable_int_on_completion: 1;
uint32_t last_descriptor: 1;
@@ -32,10 +32,10 @@ typedef struct {
uint32_t buffer1_size: 13;
uint32_t buffer2_size: 13;
uint32_t reserved3: 6;
void *buffer1_ptr;
void* buffer1_ptr;
union {
void *buffer2_ptr;
void *next_desc_ptr;
void* buffer2_ptr;
void* next_desc_ptr;
};
} sdmmc_desc_t;
@@ -44,7 +44,7 @@ typedef struct {
_Static_assert(sizeof(sdmmc_desc_t) == 16, "invalid size of sdmmc_desc_t structure");
typedef struct {
typedef struct sdmmc_hw_cmd_s {
uint32_t cmd_index: 6; ///< Command index
uint32_t response_expect: 1; ///< set if response is expected
uint32_t response_long: 1; ///< 0: short response expected, 1: long response expected
@@ -73,7 +73,7 @@ typedef struct {
_Static_assert(sizeof(sdmmc_hw_cmd_t) == 4, "invalid size of sdmmc_cmd_t structure");
typedef volatile struct {
typedef volatile struct sdmmc_dev_s {
union {
struct {
uint32_t controller_reset: 1;
@@ -282,7 +282,12 @@ typedef volatile struct {
uint32_t usrid; ///< user ID
uint32_t verid; ///< IP block version
uint32_t hcon; ///< compile-time IP configuration
uint32_t uhs; ///< TBD
union {
struct {
uint32_t voltage: 16; ///< voltage control for slots; no-op on ESP32.
uint32_t ddr: 16; ///< bit N enables DDR mode for card N
};
} uhs; ///< UHS related settings
union {
struct {
@@ -306,7 +311,7 @@ typedef volatile struct {
} bmod;
uint32_t pldmnd; ///< set any bit to resume IDMAC FSM from suspended state
sdmmc_desc_t *dbaddr; ///< descriptor list base
sdmmc_desc_t* dbaddr; ///< descriptor list base
union {
struct {
@@ -347,7 +352,16 @@ typedef volatile struct {
uint32_t bufaddrl; ///< unused
uint32_t bufaddru; ///< unused
uint32_t reserved_a8[22];
uint32_t cardthrctl;
union {
struct {
uint32_t read_thr_en : 1; ///< initiate transfer only if FIFO has more space than the read threshold
uint32_t busy_clr_int_en : 1; ///< enable generation of busy clear interrupts
uint32_t write_thr_en : 1; ///< equivalent of read_thr_en for writes
uint32_t reserved1 : 13;
uint32_t card_threshold : 12; ///< threshold value for reads/writes, in bytes
};
uint32_t val;
} cardthrctl;
uint32_t back_end_power;
uint32_t uhs_reg_ext;
uint32_t emmc_ddr_reg;
@@ -361,6 +375,8 @@ typedef volatile struct {
uint32_t div_factor_p: 4; ///< controls clock period; it will be (div_factor_p + 1) / 160MHz
uint32_t div_factor_h: 4; ///< controls length of high pulse; it will be (div_factor_h + 1) / 160MHz
uint32_t div_factor_m: 4; ///< should be equal to div_factor_p
uint32_t reserved1 : 2;
uint32_t clk_sel : 1; ///< clock source select (0: XTAL, 1: 160 MHz from PLL)
};
uint32_t val;
} clock;

11
components/soc/esp32s3/include/soc/soc_caps.h
View File

@@ -21,6 +21,7 @@
#define SOC_HMAC_SUPPORTED 1
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
#define SOC_SDMMC_HOST_SUPPORTED 1
/*-------------------------- ADC CAPS ----------------------------------------*/
@@ -214,3 +215,13 @@
#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)
/*-------------------------- SDMMC CAPS -----------------------------------------*/
/* Card detect, write protect, interrupt use GPIO Matrix on all chips.
* On ESP32-S3, clock/cmd/data pins use GPIO Matrix as well.
*/
#define SOC_SDMMC_USE_GPIO_MATRIX 1
#define SOC_SDMMC_NUM_SLOTS 2
/* Indicates that there is an option to use XTAL clock instead of PLL for SDMMC */
#define SOC_SDMMC_SUPPORT_XTAL_CLOCK 1

53
components/soc/esp32s3/sdmmc_periph.c
View File

@@ -14,37 +14,44 @@
#include "soc/sdmmc_periph.h"
const sdmmc_slot_info_t sdmmc_slot_info[2] = {
const sdmmc_slot_info_t sdmmc_slot_info[SOC_SDMMC_NUM_SLOTS] = {
{
.clk_gpio = SDMMC_SLOT0_IOMUX_PIN_NUM_CLK,
.cmd_gpio = SDMMC_SLOT0_IOMUX_PIN_NUM_CMD,
.d0_gpio = SDMMC_SLOT0_IOMUX_PIN_NUM_D0,
.d1_gpio = SDMMC_SLOT0_IOMUX_PIN_NUM_D1,
.d2_gpio = SDMMC_SLOT0_IOMUX_PIN_NUM_D2,
.d3_gpio = SDMMC_SLOT0_IOMUX_PIN_NUM_D3,
.d4_gpio = SDMMC_SLOT0_IOMUX_PIN_NUM_D4,
.d5_gpio = SDMMC_SLOT0_IOMUX_PIN_NUM_D5,
.d6_gpio = SDMMC_SLOT0_IOMUX_PIN_NUM_D6,
.d7_gpio = SDMMC_SLOT0_IOMUX_PIN_NUM_D7,
.width = 8,
.card_detect = SDHOST_CARD_DETECT_N_1_IDX,
.write_protect = SDHOST_CARD_WRITE_PRT_1_IDX,
.card_int = SDHOST_CARD_INT_N_1_IDX,
.width = 8
},
{
.clk_gpio = SDMMC_SLOT1_IOMUX_PIN_NUM_CLK,
.cmd_gpio = SDMMC_SLOT1_IOMUX_PIN_NUM_CMD,
.d0_gpio = SDMMC_SLOT1_IOMUX_PIN_NUM_D0,
.d1_gpio = SDMMC_SLOT1_IOMUX_PIN_NUM_D1,
.d2_gpio = SDMMC_SLOT1_IOMUX_PIN_NUM_D2,
.d3_gpio = SDMMC_SLOT1_IOMUX_PIN_NUM_D3,
.d4_gpio = -1, //slot1 has no D4-7
.d5_gpio = -1,
.d6_gpio = -1,
.d7_gpio = -1,
.width = 8,
.card_detect = SDHOST_CARD_DETECT_N_2_IDX,
.write_protect = SDHOST_CARD_WRITE_PRT_2_IDX,
.card_int = SDHOST_CARD_INT_N_2_IDX,
.width = 4
}
};
const sdmmc_slot_io_info_t sdmmc_slot_gpio_sig[SOC_SDMMC_NUM_SLOTS] = {
{
.clk = SDHOST_CCLK_OUT_1_IDX,
.cmd = SDHOST_CCMD_OUT_1_IDX,
.d0 = SDHOST_CDATA_OUT_10_IDX,
.d1 = SDHOST_CDATA_OUT_11_IDX,
.d2 = SDHOST_CDATA_OUT_12_IDX,
.d3 = SDHOST_CDATA_OUT_13_IDX,
.d4 = SDHOST_CDATA_OUT_14_IDX,
.d5 = SDHOST_CDATA_OUT_15_IDX,
.d6 = SDHOST_CDATA_OUT_16_IDX,
.d7 = SDHOST_CDATA_OUT_17_IDX,
},
{
.clk = SDHOST_CCLK_OUT_2_IDX,
.cmd = SDHOST_CCMD_OUT_2_IDX,
.d0 = SDHOST_CDATA_OUT_20_IDX,
.d1 = SDHOST_CDATA_OUT_21_IDX,
.d2 = SDHOST_CDATA_OUT_22_IDX,
.d3 = SDHOST_CDATA_OUT_23_IDX,
.d4 = SDHOST_CDATA_OUT_24_IDX,
.d5 = SDHOST_CDATA_OUT_25_IDX,
.d6 = SDHOST_CDATA_OUT_26_IDX,
.d7 = SDHOST_CDATA_OUT_27_IDX,
}
};