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Merge branch 'bugfix/i80_pll240_esp32s3' into 'master'

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lcd: support PLL240M as i80 clock source on esp32s3

See merge request espressif/esp-idf!22285
This commit is contained in:
morris
2023-02-14 12:27:57 +08:00
parent d1b6ff6cca 78855a88c9
commit 18295bb2f5
9 changed files with 67 additions and 73 deletions
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8
components/soc/esp32/include/soc/clk_tree_defs.h
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@@ -165,16 +165,14 @@ typedef enum {
/**
* @brief Array initializer for all supported clock sources of LCD
*/
#define SOC_LCD_CLKS {SOC_MOD_CLK_PLL_D2, SOC_MOD_CLK_APLL, SOC_MOD_CLK_XTAL}
#define SOC_LCD_CLKS {SOC_MOD_CLK_PLL_F160M}
/**
* @brief Type of LCD clock source
*/
typedef enum {
LCD_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_D2, /*!< Select PLL_D2 (default to 160MHz) as the source clock */
LCD_CLK_SRC_APLL = SOC_MOD_CLK_APLL, /*!< Select APLL as the source clock */
LCD_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
LCD_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_D2, /*!< Select PLL_D2 (default to 160MHz) as the default choice */
LCD_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_160M as the source clock */
LCD_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_160M as the default choice */
} soc_periph_lcd_clk_src_t;
//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////