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Merge branch 'bugfix/i80_pll240_esp32s3' into 'master'
lcd: support PLL240M as i80 clock source on esp32s3 See merge request espressif/esp-idf!22285
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@@ -165,16 +165,14 @@ typedef enum {
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/**
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* @brief Array initializer for all supported clock sources of LCD
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*/
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#define SOC_LCD_CLKS {SOC_MOD_CLK_PLL_D2, SOC_MOD_CLK_APLL, SOC_MOD_CLK_XTAL}
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#define SOC_LCD_CLKS {SOC_MOD_CLK_PLL_F160M}
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/**
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* @brief Type of LCD clock source
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*/
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typedef enum {
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LCD_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_D2, /*!< Select PLL_D2 (default to 160MHz) as the source clock */
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LCD_CLK_SRC_APLL = SOC_MOD_CLK_APLL, /*!< Select APLL as the source clock */
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LCD_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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LCD_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_D2, /*!< Select PLL_D2 (default to 160MHz) as the default choice */
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LCD_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_160M as the source clock */
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LCD_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_160M as the default choice */
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} soc_periph_lcd_clk_src_t;
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//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
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