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clk_tree: Add basic clock support for esp32c6

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- Support SOC ROOT clock source switch
    - Support CPU frequency change
    - Support RTC SLOW clock source switch
    - Support RTC SLOW clock + RC FAST calibration

    Remove FPGA build for esp32c6
This commit is contained in:
Song Ruo Jing
2022-11-18 17:59:05 +08:00
parent 3b31370e39
commit 182e937c5a
35 changed files with 1130 additions and 660 deletions
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8
components/esptool_py/Kconfig.projbuild
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@@ -88,7 +88,7 @@ menu "Serial flasher config"
choice ESPTOOLPY_FLASHFREQ
prompt "Flash SPI speed"
default ESPTOOLPY_FLASHFREQ_40M if IDF_TARGET_ESP32
default ESPTOOLPY_FLASHFREQ_80M if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C3
default ESPTOOLPY_FLASHFREQ_80M if ESPTOOLPY_FLASHFREQ_80M_DEFAULT
default ESPTOOLPY_FLASHFREQ_60M if IDF_TARGET_ESP32C2
default ESPTOOLPY_FLASHFREQ_48M if IDF_TARGET_ESP32H4
config ESPTOOLPY_FLASHFREQ_120M
@@ -124,6 +124,12 @@ menu "Serial flasher config"
depends on SOC_MEMSPI_SRC_FREQ_15M_SUPPORTED
endchoice
config ESPTOOLPY_FLASHFREQ_80M_DEFAULT
bool
default y if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C6
help
This is an invisible item, used to define the targets that defaults to use 80MHz Flash SPI speed.
config ESPTOOLPY_FLASHFREQ
string
# On some of the ESP chips, max boot frequency would be equal to (or even lower than) 80m.