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https://github.com/espressif/esp-idf.git
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clk_tree: Add basic clock support for esp32c6
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
Remove FPGA build for esp32c6
This commit is contained in:
Song Ruo Jing
@@ -5,44 +5,50 @@
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*/
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#pragma once
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#include "sdkconfig.h" // TODO: IDF-5973
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#ifdef __cplusplus
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extern "C" {
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#endif
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// TODO: IDF-5346 Copied from C3, need to update
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/*
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************************* ESP32C6 Root Clock Source ****************************
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* 1) Internal 17.5MHz RC Oscillator: RC_FAST (usually referred as FOSC or CK8M/CLK8M in TRM and reg. description)
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* 1) Internal 17.5MHz RC Oscillator: RC_FAST (may also referred as FOSC in TRM and reg. description)
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*
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* This RC oscillator generates a ~17.5MHz clock signal output as the RC_FAST_CLK.
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* The ~17.5MHz signal output is also passed into a configurable divider, which by default divides the input clock
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* frequency by 256, to generate a RC_FAST_D256_CLK (usually referred as 8md256 or simply d256 in reg. description).
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*
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* The exact frequency of RC_FAST_CLK can be computed in runtime through calibration on the RC_FAST_D256_CLK.
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* The exact frequency of RC_FAST_CLK can be computed in runtime through calibration.
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*
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* 2) External 40MHz Crystal Clock: XTAL
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*
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* 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referrred as RTC in TRM or reg. description)
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* 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referrred as SOSC in TRM or reg. description)
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*
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* This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
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* can be computed in runtime through calibration.
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*
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* 4) External 32kHz Crystal Clock (optional): XTAL32K
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* 4) Internal 32kHz RC Oscillator: RC32K
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*
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* The clock source for this XTAL32K_CLK can be either a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N
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* pins or a 32kHz clock signal generated by an external circuit. The external signal must be connected to the
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* XTAL_32K_P pin.
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* The exact frequency of this clock can be computed in runtime through calibration.
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*
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* 5) External 32kHz Crystal Clock (optional): XTAL32K
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*
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* The clock source for this XTAL32K_CLK should be a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N
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* pins.
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*
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* XTAL32K_CLK can also be calibrated to get its exact frequency.
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*
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* 6) External Slow Clock (optional): OSC_SLOW
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*
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* A clock signal generated by an external circuit with frequency ~32kHz can be connected to GPIO0
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* to be the clock source for the RTC_SLOW_CLK.
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*
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* OSC_SLOW_CLK can also be calibrated to get its exact frequency.
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*/
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/* With the default value of CK8M_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */
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/* With the default value of FOSC_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */
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#define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!< Approximate RC_FAST_CLK frequency in Hz */
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#define SOC_CLK_RC_SLOW_FREQ_APPROX 136000 /*!< Approximate RC_SLOW_CLK frequency in Hz */
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#define SOC_CLK_RC_FAST_D256_FREQ_APPROX (SOC_CLK_RC_FAST_FREQ_APPROX / 256) /*!< Approximate RC_FAST_D256_CLK frequency in Hz */
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#define SOC_CLK_RC32K_FREQ_APPROX 32768 /*!< Approximate RC32K_CLK frequency in Hz */
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#define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */
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#define SOC_CLK_OSC_SLOW_FREQ_APPROX 32768 /*!< Approximate OSC_SLOW_CLK (external slow clock) frequency in Hz */
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// Naming convention: SOC_ROOT_CLK_{loc}_{type}_[attr]
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// {loc}: EXT, INT
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@@ -55,7 +61,9 @@ typedef enum {
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SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 17.5MHz RC oscillator */
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SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 136kHz RC oscillator */
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SOC_ROOT_CLK_EXT_XTAL, /*!< External 40MHz crystal */
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SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal/clock signal */
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SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal */
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SOC_ROOT_CLK_INT_RC32K, /*!< Internal 32kHz RC oscillator */
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SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin0, only support 32.768 kHz currently */
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} soc_root_clk_t;
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/**
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@@ -64,7 +72,7 @@ typedef enum {
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*/
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typedef enum {
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SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */
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SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, can be 480MHz or 320MHz) */
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SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, 480MHz) */
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SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */
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SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */
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} soc_cpu_clk_src_t;
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@@ -74,10 +82,11 @@ typedef enum {
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* @note Enum values are matched with the register field values on purpose
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*/
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typedef enum {
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SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */
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SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */
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SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 = 2, /*!< Select RC_FAST_D256_CLK (referred as FOSC_DIV or 8m_d256/8md256 in TRM and reg. description) as RTC_SLOW_CLK source */
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SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */
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SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */
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SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */
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SOC_RTC_SLOW_CLK_SRC_RC32K = 2, /*!< Select RC32K_CLK as RTC_SLOW_CLK source */
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SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 3, /*!< Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source */
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SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */
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} soc_rtc_slow_clk_src_t;
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/**
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@@ -85,9 +94,9 @@ typedef enum {
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* @note Enum values are matched with the register field values on purpose
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*/
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typedef enum {
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SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 0, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */
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SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
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SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */
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SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
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SOC_RTC_FAST_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
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SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
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} soc_rtc_fast_clk_src_t;
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@@ -106,13 +115,12 @@ typedef enum {
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SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
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SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or RC_FAST_D256 by configuring soc_rtc_slow_clk_src_t */
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// For digital domain: peripherals, WIFI, BLE
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SOC_MOD_CLK_APB, /*!< APB_CLK is highly dependent on the CPU_CLK source */
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SOC_MOD_CLK_APB, /*!< APB_CLK is highly dependent on the CPU_CLK source */ // TODO: IDF-6343 This should be removed on ESP32C6! Impacts on all following peripheral drivers!
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SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL, and has a fixed frequency of 80MHz */
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SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL, and has a fixed frequency of 160MHz */
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SOC_MOD_CLK_PLL_D2, /*!< PLL_D2_CLK is derived from PLL, it has a fixed divider of 2 */
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SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from PLL, and has a fixed frequency of 240MHz */
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SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
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SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
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SOC_MOD_CLK_RC_FAST_D256, /*!< RC_FAST_D256_CLK comes from the internal 20MHz rc oscillator, divided by 256, and passing a clock gating to the peripherals */
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SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */
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} soc_module_clk_t;
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@@ -141,11 +149,7 @@ typedef enum {
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* }
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* @endcode
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*/
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#if CONFIG_IDF_ENV_FPGA
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#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_XTAL}
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#else
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#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_XTAL}
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#endif
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/**
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* @brief Type of GPTimer clock source
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@@ -153,11 +157,7 @@ typedef enum {
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typedef enum {
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GPTIMER_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
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GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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#if CONFIG_IDF_ENV_FPGA
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GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */
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#else
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GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
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#endif
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} soc_periph_gptimer_clk_src_t;
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/**
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@@ -174,11 +174,7 @@ typedef enum {
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/**
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* @brief Array initializer for all supported clock sources of RMT
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*/
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#if CONFIG_IDF_ENV_FPGA
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#define SOC_RMT_CLKS {SOC_MOD_CLK_XTAL}
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#else
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#define SOC_RMT_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_XTAL}
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#endif
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/**
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* @brief Type of RMT clock source
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@@ -186,11 +182,7 @@ typedef enum {
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typedef enum {
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RMT_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
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RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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#if CONFIG_IDF_ENV_FPGA
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RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */
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#else
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RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
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#endif
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} soc_periph_rmt_clk_src_t;
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/**
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@@ -227,11 +219,7 @@ typedef enum {
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UART_SCLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock is PLL_F80M */
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UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */
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UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */
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#if CONFIG_IDF_ENV_FPGA
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UART_SCLK_DEFAULT = SOC_MOD_CLK_XTAL, /*!< UART source clock default choice is XTAL for FPGA environment */
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#else
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UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock default choice is PLL_F80M */
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#endif
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} soc_periph_uart_clk_src_legacy_t;
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//////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////
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@@ -247,11 +235,7 @@ typedef enum {
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typedef enum {
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MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
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MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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#if CONFIG_IDF_ENV_FPGA
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MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
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#else
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MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
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#endif
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} soc_periph_mcpwm_timer_clk_src_t;
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/**
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@@ -265,11 +249,7 @@ typedef enum {
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typedef enum {
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MCPWM_CAPTURE_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
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MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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#if CONFIG_IDF_ENV_FPGA
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MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
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#else
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MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
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#endif
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} soc_periph_mcpwm_capture_clk_src_t;
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///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
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@@ -277,21 +257,13 @@ typedef enum {
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/**
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* @brief Array initializer for all supported clock sources of I2S
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*/
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#if CONFIG_IDF_ENV_FPGA
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#define SOC_I2S_CLKS {SOC_MOD_CLK_XTAL}
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#else
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#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
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#endif
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/**
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* @brief I2S clock source enum
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*/
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typedef enum {
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#if CONFIG_IDF_ENV_FPGA
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I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,
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#else
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I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */
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#endif
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I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
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I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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} soc_periph_i2s_clk_src_t;
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@@ -146,6 +146,8 @@
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#define USB_DM_GPIO_NUM 12
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#define USB_DP_GPIO_NUM 13
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#define EXT_OSC_SLOW_GPIO_NUM 0
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#define MAX_RTC_GPIO_NUM 8
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#define MAX_PAD_GPIO_NUM 30
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#define MAX_GPIO_NUM 34
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@@ -11,7 +11,7 @@
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* @brief Register definitions for bias
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*
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* This file lists register fields of BIAS. These definitions are used via macros defined in regi2c_ctrl.h, by
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* bootloader_hardware_init function in bootloader_esp32c3.c.
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* bootloader_hardware_init function in bootloader_esp32c6.c.
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*/
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#define I2C_BIAS 0X6A
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@@ -9,11 +9,13 @@
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#include "esp_bit_defs.h"
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/* Analog function control register */
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#define I2C_MST_ANA_CONF0_REG 0x6000E040
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#define I2C_MST_ANA_CONF0_REG 0x600AF818
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#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
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#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
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#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
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#define I2C_MST_BBPLL_CAL_DONE (BIT(24))
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#define ANA_CONFIG_REG 0x6000E044
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#define ANA_CONFIG_REG 0x600AF81C
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#define ANA_CONFIG_S (8)
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#define ANA_CONFIG_M (0x3FF)
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@@ -21,11 +23,12 @@
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#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */
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#define ANA_CONFIG2_REG 0x6000E048
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#define ANA_CONFIG2_REG 0x600AF820
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#define ANA_CONFIG2_M BIT(18)
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#define ANA_I2C_SAR_FORCE_PU BIT(16)
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/**
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* Restore regi2c analog calibration related configuration registers.
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* This is a workaround, and is fixed on later chips
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64
components/soc/esp32c6/include/soc/regi2c_dig_reg.h
Normal file
64
components/soc/esp32c6/include/soc/regi2c_dig_reg.h
Normal file
@@ -0,0 +1,64 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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/**
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* @file regi2c_dig_reg.h
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* @brief Register definitions for digital to get rtc voltage & digital voltage
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* by setting rtc_dbias_Wak & dig_dbias_wak or by analog self-calibration.
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*/
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#define I2C_DIG_REG 0x6D
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#define I2C_DIG_REG_HOSTID 0
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#define I2C_DIG_REG_EXT_RTC_DREG 4
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#define I2C_DIG_REG_EXT_RTC_DREG_MSB 4
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#define I2C_DIG_REG_EXT_RTC_DREG_LSB 0
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#define I2C_DIG_REG_ENX_RTC_DREG 4
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#define I2C_DIG_REG_ENX_RTC_DREG_MSB 7
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#define I2C_DIG_REG_ENX_RTC_DREG_LSB 7
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#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP 5
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#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_MSB 4
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#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_LSB 0
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#define I2C_DIG_REG_ENIF_RTC_DREG 5
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#define I2C_DIG_REG_ENIF_RTC_DREG_MSB 7
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#define I2C_DIG_REG_ENIF_RTC_DREG_LSB 7
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#define I2C_DIG_REG_EXT_DIG_DREG 6
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#define I2C_DIG_REG_EXT_DIG_DREG_MSB 4
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#define I2C_DIG_REG_EXT_DIG_DREG_LSB 0
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#define I2C_DIG_REG_ENX_DIG_DREG 6
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#define I2C_DIG_REG_ENX_DIG_DREG_MSB 7
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#define I2C_DIG_REG_ENX_DIG_DREG_LSB 7
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#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP 7
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#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_MSB 4
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#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_LSB 0
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#define I2C_DIG_REG_ENIF_DIG_DREG 7
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#define I2C_DIG_REG_ENIF_DIG_DREG_MSB 7
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#define I2C_DIG_REG_ENIF_DIG_DREG_LSB 7
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|
||||
#define I2C_DIG_REG_OR_EN_CONT_CAL 9
|
||||
#define I2C_DIG_REG_OR_EN_CONT_CAL_MSB 7
|
||||
#define I2C_DIG_REG_OR_EN_CONT_CAL_LSB 7
|
||||
|
||||
#define I2C_DIG_REG_XPD_RTC_REG 13
|
||||
#define I2C_DIG_REG_XPD_RTC_REG_MSB 2
|
||||
#define I2C_DIG_REG_XPD_RTC_REG_LSB 2
|
||||
|
||||
#define I2C_DIG_REG_XPD_DIG_REG 13
|
||||
#define I2C_DIG_REG_XPD_DIG_REG_MSB 3
|
||||
#define I2C_DIG_REG_XPD_DIG_REG_LSB 3
|
||||
|
||||
#define I2C_DIG_REG_SCK_DCAP 14
|
||||
#define I2C_DIG_REG_SCK_DCAP_MSB 7
|
||||
#define I2C_DIG_REG_SCK_DCAP_LSB 0
|
||||
@@ -46,13 +46,14 @@ extern "C" {
|
||||
|
||||
#define MHZ (1000000)
|
||||
|
||||
#define RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12)
|
||||
#define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles) (cycles << 12)
|
||||
#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10)
|
||||
#define RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12)
|
||||
#define RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(cycles) (TIMG_RTC_CALI_TIMEOUT_THRES_V) // Just use the max timeout thres value
|
||||
|
||||
#define OTHER_BLOCKS_POWERUP 1
|
||||
#define OTHER_BLOCKS_WAIT 1
|
||||
|
||||
// TODO: IDF-5781
|
||||
/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
|
||||
* RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
|
||||
*/
|
||||
@@ -74,9 +75,10 @@ extern "C" {
|
||||
#define SOC_DELAY_RTC_SLOW_CLK_SWITCH 300
|
||||
#define SOC_DELAY_RC_FAST_ENABLE 50
|
||||
#define SOC_DELAY_RC_FAST_DIGI_SWITCH 5
|
||||
#define SOC_DELAY_RC32K_ENABLE 300
|
||||
|
||||
/* Core voltage:
|
||||
* Currently, ESP32C3 never adjust its wake voltage in runtime
|
||||
/* Core voltage: // TODO: IDF-5781
|
||||
* Currently, ESP32C6 never adjust its wake voltage in runtime
|
||||
* Only sets dig/rtc voltage dbias at startup time
|
||||
*/
|
||||
#define DIG_DBIAS_80M RTC_CNTL_DBIAS_1V20
|
||||
@@ -89,8 +91,9 @@ extern "C" {
|
||||
#define RTC_CNTL_CK8M_WAIT_DEFAULT 20
|
||||
#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5
|
||||
|
||||
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100
|
||||
#define RTC_CNTL_SCK_DCAP_DEFAULT 255
|
||||
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100
|
||||
#define RTC_CNTL_SCK_DCAP_DEFAULT 128
|
||||
#define RTC_CNTL_RC32K_DFREQ_DEFAULT 700
|
||||
|
||||
/* Various delays to be programmed into power control state machines */
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250)
|
||||
@@ -140,7 +143,7 @@ typedef enum {
|
||||
typedef struct rtc_cpu_freq_config_s {
|
||||
soc_cpu_clk_src_t source; //!< The clock from which CPU clock is derived
|
||||
uint32_t source_freq_mhz; //!< Source clock frequency
|
||||
uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div
|
||||
uint32_t div; //!< Divider, freq_mhz = SOC_ROOT_CLK freq_mhz / div
|
||||
uint32_t freq_mhz; //!< CPU clock frequency
|
||||
} rtc_cpu_freq_config_t;
|
||||
|
||||
@@ -151,12 +154,18 @@ typedef struct rtc_cpu_freq_config_s {
|
||||
|
||||
/**
|
||||
* @brief Clock source to be calibrated using rtc_clk_cal function
|
||||
*
|
||||
* @note On previous targets, the enum values somehow reflects the register field values of TIMG_RTC_CALI_CLK_SEL
|
||||
* However, this is not true on ESP32C6. The conversion to register field values is explicitly done in
|
||||
* rtc_clk_cal_internal
|
||||
*/
|
||||
typedef enum {
|
||||
RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK
|
||||
RTC_CAL_32K_XTAL = 2, //!< External 32 kHz XTAL
|
||||
RTC_CAL_INTERNAL_OSC = 3, //!< Internal 150 kHz oscillator
|
||||
RTC_CAL_RC_FAST, //!< Internal 20 MHz oscillator
|
||||
RTC_CAL_RTC_MUX = -1, //!< Currently selected RTC_SLOW_CLK
|
||||
RTC_CAL_RC_SLOW = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 150kHz RC oscillator
|
||||
RTC_CAL_RC32K = SOC_RTC_SLOW_CLK_SRC_RC32K, //!< Internal 32kHz RC oscillator, as one type of 32k clock
|
||||
RTC_CAL_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32kHz XTAL, as one type of 32k clock
|
||||
RTC_CAL_32K_OSC_SLOW = SOC_RTC_SLOW_CLK_SRC_OSC_SLOW, //!< External 32kHz clk signal input by lp_pad_gpio0, as one type of 32k clock
|
||||
RTC_CAL_RC_FAST //!< Internal 20MHz RC oscillator
|
||||
} rtc_cal_sel_t;
|
||||
|
||||
/**
|
||||
@@ -166,11 +175,12 @@ typedef struct {
|
||||
rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
|
||||
uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz
|
||||
soc_rtc_fast_clk_src_t fast_clk_src : 2; //!< RTC_FAST_CLK clock source to choose
|
||||
soc_rtc_slow_clk_src_t slow_clk_src : 2; //!< RTC_SLOW_CLK clock source to choose
|
||||
soc_rtc_slow_clk_src_t slow_clk_src : 3; //!< RTC_SLOW_CLK clock source to choose
|
||||
uint32_t clk_rtc_clk_div : 8;
|
||||
uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency)
|
||||
uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency)
|
||||
uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency)
|
||||
uint32_t clk_8m_clk_div : 3; //!< RC_FAST clock divider (division is by clk_8m_div+1, i.e. 0 means ~20MHz frequency)
|
||||
uint32_t slow_clk_dcap : 8; //!< RC_SLOW clock adjustment parameter (higher value leads to lower frequency)
|
||||
uint32_t clk_8m_dfreq : 8; //!< RC_FAST clock adjustment parameter (higher value leads to higher frequency)
|
||||
uint32_t rc32k_dfreq : 10; //!< Internal RC32K clock adjustment parameter (higher value leads to higher frequency)
|
||||
} rtc_clk_config_t;
|
||||
|
||||
/**
|
||||
@@ -185,6 +195,7 @@ typedef struct {
|
||||
.clk_8m_clk_div = 0, \
|
||||
.slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \
|
||||
.clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
|
||||
.rc32k_dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT, \
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
@@ -213,10 +224,6 @@ typedef struct {
|
||||
.dg_peri_wait_cycles = OTHER_BLOCKS_WAIT, \
|
||||
}
|
||||
|
||||
void rtc_clk_divider_set(uint32_t div);
|
||||
|
||||
void rtc_clk_8m_divider_set(uint32_t div);
|
||||
|
||||
/**
|
||||
* Initialize clocks and set CPU frequency
|
||||
*
|
||||
@@ -273,23 +280,18 @@ bool rtc_clk_32k_enabled(void);
|
||||
*/
|
||||
void rtc_clk_32k_bootstrap(uint32_t cycle);
|
||||
|
||||
/**
|
||||
* @brief Enable or disable 32 kHz internal rc oscillator
|
||||
* @param en true to enable, false to disable
|
||||
*/
|
||||
void rtc_clk_rc32k_enable(bool enable);
|
||||
|
||||
/**
|
||||
* @brief Enable or disable 8 MHz internal oscillator
|
||||
*
|
||||
* Output from 8 MHz internal oscillator is passed into a configurable
|
||||
* divider, which by default divides the input clock frequency by 256.
|
||||
* Output of the divider may be used as RTC_SLOW_CLK source.
|
||||
* Output of the divider is referred to in register descriptions and code as
|
||||
* 8md256 or simply d256. Divider values other than 256 may be configured, but
|
||||
* this facility is not currently needed, so is not exposed in the code.
|
||||
*
|
||||
* When 8MHz/256 divided output is not needed, the divider should be disabled
|
||||
* to reduce power consumption.
|
||||
*
|
||||
* @param clk_8m_en true to enable 8MHz generator
|
||||
* @param d256_en true to enable /256 divider
|
||||
*/
|
||||
void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en);
|
||||
void rtc_clk_8m_enable(bool clk_8m_en);
|
||||
|
||||
/**
|
||||
* @brief Get the state of 8 MHz internal oscillator
|
||||
@@ -297,12 +299,6 @@ void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en);
|
||||
*/
|
||||
bool rtc_clk_8m_enabled(void);
|
||||
|
||||
/**
|
||||
* @brief Get the state of /256 divider which is applied to 8MHz clock
|
||||
* @return true if the divided output is enabled
|
||||
*/
|
||||
bool rtc_clk_8md256_enabled(void);
|
||||
|
||||
/**
|
||||
* @brief Select source for RTC_SLOW_CLK
|
||||
* @param clk_src clock source (one of soc_rtc_slow_clk_src_t values)
|
||||
@@ -401,25 +397,29 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config);
|
||||
void rtc_clk_cpu_freq_set_xtal(void);
|
||||
|
||||
/**
|
||||
* @brief Store new APB frequency value into RTC_APB_FREQ_REG
|
||||
*
|
||||
* This function doesn't change any hardware clocks.
|
||||
*
|
||||
* Functions which perform frequency switching and change APB frequency call
|
||||
* this function to update the value of APB frequency stored in RTC_APB_FREQ_REG
|
||||
* (one of RTC general purpose retention registers). This should not normally
|
||||
* be called from application code.
|
||||
*
|
||||
* @param apb_freq new APB frequency, in Hz
|
||||
*/
|
||||
void rtc_clk_apb_freq_update(uint32_t apb_freq);
|
||||
|
||||
/**
|
||||
* @brief Get the current stored APB frequency.
|
||||
* @return The APB frequency value as last set via rtc_clk_apb_freq_update(), in Hz.
|
||||
* @brief Get the current APB frequency.
|
||||
* @return The calculated APB frequency value, in Hz.
|
||||
*/
|
||||
uint32_t rtc_clk_apb_freq_get(void);
|
||||
|
||||
/**
|
||||
* @brief Clock calibration function used by rtc_clk_cal
|
||||
*
|
||||
* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
|
||||
* This feature counts the number of XTAL clock cycles within a given number of
|
||||
* RTC_SLOW_CLK cycles.
|
||||
*
|
||||
* Slow clock calibration feature has two modes of operation: one-off and cycling.
|
||||
* In cycling mode (which is enabled by default on SoC reset), counting of XTAL
|
||||
* cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
|
||||
* using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
|
||||
* once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
|
||||
* enabled using TIMG_RTC_CALI_START bit.
|
||||
*
|
||||
* @param cal_clk which clock to calibrate
|
||||
* @param slowclk_cycles number of slow clock cycles to count
|
||||
* @return number of XTAL clock cycles within the given number of slow clock cycles
|
||||
*/
|
||||
uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles);
|
||||
|
||||
/**
|
||||
@@ -430,6 +430,11 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles);
|
||||
* 32k XTAL is being calibrated, but the oscillator has not started up (due to
|
||||
* incorrect loading capacitance, board design issue, or lack of 32 XTAL on board).
|
||||
*
|
||||
* @note When 32k CLK is being calibrated, this function will check the accuracy
|
||||
* of the clock. Since the xtal 32k or ext osc 32k is generally very stable, if
|
||||
* the check fails, then consider this an invalid 32k clock and return 0. This
|
||||
* check can filter some jamming signal.
|
||||
*
|
||||
* @param cal_clk clock to be measured
|
||||
* @param slow_clk_cycles number of slow clock cycles to average
|
||||
* @return average slow clock period in microseconds, Q13.19 fixed point format,
|
||||
@@ -437,15 +442,6 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles);
|
||||
*/
|
||||
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
|
||||
|
||||
/**
|
||||
* @brief Measure ratio between XTAL frequency and RTC slow clock frequency
|
||||
* @param cal_clk slow clock to be measured
|
||||
* @param slow_clk_cycles number of slow clock cycles to average
|
||||
* @return average ratio between XTAL frequency and slow clock frequency,
|
||||
* Q13.19 fixed point format, or 0 if calibration has timed out.
|
||||
*/
|
||||
uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
|
||||
|
||||
/**
|
||||
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles
|
||||
* @param time_in_us Time interval in microseconds
|
||||
|
||||
@@ -140,19 +140,10 @@
|
||||
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
|
||||
#define EFUSE_CLK_FREQ_ROM ( 20*1000000)
|
||||
#define CPU_CLK_FREQ APB_CLK_FREQ
|
||||
#if CONFIG_IDF_ENV_FPGA
|
||||
#define APB_CLK_FREQ ( 40*1000000 )
|
||||
#else
|
||||
#define APB_CLK_FREQ ( 80*1000000 )
|
||||
#endif
|
||||
#define APB_CLK_FREQ ( 80*1000000 ) // TODO: IDF-6343 APB clock freq is 40MHz indeed
|
||||
#define REF_CLK_FREQ ( 1000000 )
|
||||
#define RTC_CLK_FREQ (20*1000000)
|
||||
#define XTAL_CLK_FREQ (40*1000000)
|
||||
#define UART_CLK_FREQ APB_CLK_FREQ
|
||||
#define WDT_CLK_FREQ APB_CLK_FREQ
|
||||
#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16
|
||||
#define SPI_CLK_DIV 4
|
||||
#define TICKS_PER_US_ROM 40 // CPU is 80MHz
|
||||
#define GPIO_MATRIX_DELAY_NS 0
|
||||
//}}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user