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spi_master: add feature spi periph clk source selectable
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@@ -145,25 +145,25 @@
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#define TV_WITH_ESP_SLAVE (TV_INT_CONNECT+WIRE_DELAY)
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//currently ESP32 slave only supports up to 20MHz, but 40MHz on the same board
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#define ESP_SPI_SLAVE_MAX_FREQ SPI_MASTER_FREQ_20M
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#define ESP_SPI_SLAVE_MAX_FREQ_SYNC SPI_MASTER_FREQ_40M
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#define ESP_SPI_SLAVE_MAX_FREQ 20 * 1000 * 1000
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#define ESP_SPI_SLAVE_MAX_FREQ_SYNC 40 * 1000 * 1000
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#define MAX_TEST_SIZE 16 ///< in this test we run several transactions, this is the maximum trans that can be run
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#define PSET_NAME_LEN 30 ///< length of each param set name
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//test low frequency, high frequency until freq limit for worst case (both GPIO)
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#define TEST_FREQ_DEFAULT(){ \
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1*1000*1000, \
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SPI_MASTER_FREQ_8M , \
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SPI_MASTER_FREQ_9M , \
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SPI_MASTER_FREQ_10M, \
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SPI_MASTER_FREQ_11M, \
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SPI_MASTER_FREQ_13M, \
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SPI_MASTER_FREQ_16M, \
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SPI_MASTER_FREQ_20M, \
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SPI_MASTER_FREQ_26M, \
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SPI_MASTER_FREQ_40M, \
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SPI_MASTER_FREQ_80M, \
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1 * 1000 * 1000, \
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8 * 1000 * 1000, \
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9 * 1000 * 1000, \
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10 * 1000 * 1000, \
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11 * 1000 * 1000, \
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13 * 1000 * 1000, \
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16 * 1000 * 1000, \
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20 * 1000 * 1000, \
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26 * 1000 * 1000, \
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40 * 1000 * 1000, \
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80 * 1000 * 1000, \
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0,\
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}
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