alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-12-05 00:18:05 +00:00
Code Issues Packages Projects Releases Wiki Activity

fix(i2c): Fix possible error state in clear the bus,

Browse Source 
Closes https://github.com/espressif/esp-idf/issues/13647
This commit is contained in:
C.S.M
2024-08-28 18:21:28 +08:00
parent deb91c7abe
commit 189db78bec
11 changed files with 172 additions and 49 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
components/esp_driver_i2c/i2c_master.c
View File

@@ -50,6 +50,7 @@ static const char *TAG = "i2c.master";
static esp_err_t s_i2c_master_clear_bus(i2c_bus_handle_t handle)
{
esp_err_t ret = ESP_OK;
#if !SOC_I2C_SUPPORT_HW_CLR_BUS
const int scl_half_period = 5; // use standard 100kHz data rate
int i = 0;
@@ -76,9 +77,23 @@ static esp_err_t s_i2c_master_clear_bus(i2c_bus_handle_t handle)
i2c_common_set_pins(handle);
#else
i2c_hal_context_t *hal = &handle->hal;
i2c_ll_master_clr_bus(hal->dev, I2C_LL_RESET_SLV_SCL_PULSE_NUM_DEFAULT);
i2c_ll_master_clr_bus(hal->dev, I2C_LL_RESET_SLV_SCL_PULSE_NUM_DEFAULT, true);
// If the i2c master clear bus state machine got disturbed when its work, it would go into error state.
// The solution here is to use freertos tick counter to set time threshold. If its not return on time,
// return invalid state and turn off the state machine for avoiding its always wrong.
TickType_t start_tick = xTaskGetTickCount();
const TickType_t timeout_ticks = pdMS_TO_TICKS(I2C_CLR_BUS_TIMEOUT_MS);
while (i2c_ll_master_is_bus_clear_done(hal->dev)) {
if ((xTaskGetTickCount() - start_tick) > timeout_ticks) {
ESP_LOGE(TAG, "clear bus failed.");
i2c_ll_master_clr_bus(hal->dev, 0, false);
ret = ESP_ERR_INVALID_STATE;
break;
}
}
i2c_ll_update(hal->dev);
#endif
return ESP_OK;
return ret;
}
/**
@@ -90,6 +105,7 @@ static esp_err_t s_i2c_master_clear_bus(i2c_bus_handle_t handle)
*/
static esp_err_t s_i2c_hw_fsm_reset(i2c_master_bus_handle_t i2c_master)
{
esp_err_t ret = ESP_OK;
i2c_hal_context_t *hal = &i2c_master->base->hal;
#if !SOC_I2C_SUPPORT_HW_FSM_RST
i2c_hal_timing_config_t timing_config;
@@ -99,7 +115,7 @@ static esp_err_t s_i2c_hw_fsm_reset(i2c_master_bus_handle_t i2c_master)
i2c_ll_master_get_filter(hal->dev, &filter_cfg);
//to reset the I2C hw module, we need re-enable the hw
s_i2c_master_clear_bus(i2c_master->base);
ret = s_i2c_master_clear_bus(i2c_master->base);
I2C_RCC_ATOMIC() {
i2c_ll_reset_register(i2c_master->base->port_num);
}
@@ -111,9 +127,9 @@ static esp_err_t s_i2c_hw_fsm_reset(i2c_master_bus_handle_t i2c_master)
i2c_ll_master_set_filter(hal->dev, filter_cfg);
#else
i2c_ll_master_fsm_rst(hal->dev);
s_i2c_master_clear_bus(i2c_master->base);
ret = s_i2c_master_clear_bus(i2c_master->base);
#endif
return ESP_OK;
return ret;
}
static void s_i2c_err_log_print(i2c_master_event_t event, bool bypass_nack_log)
@@ -542,7 +558,7 @@ static esp_err_t s_i2c_transaction_start(i2c_master_dev_handle_t i2c_dev, int xf
// Sometimes when the FSM get stuck, the ACK_ERR interrupt will occur endlessly until we reset the FSM and clear bus.
esp_err_t ret = ESP_OK;
if (i2c_master->status == I2C_STATUS_TIMEOUT || i2c_ll_is_bus_busy(hal->dev)) {
s_i2c_hw_fsm_reset(i2c_master);
ESP_RETURN_ON_ERROR(s_i2c_hw_fsm_reset(i2c_master), TAG, "reset hardware failed");
}
if (i2c_master->base->pm_lock) {