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esp_system: support gpio wakeup from deep sleep on esp32c3

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This commit is contained in:
Cao Sen Miao
2021-02-05 17:10:44 +08:00
parent 0c77299c34
commit 198d350fe5
20 changed files with 407 additions and 213 deletions
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12
components/soc/esp32c3/gpio_periph.c
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@@ -40,12 +40,12 @@ const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
};
const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = {
0, //GPIO0
0, //GPIO1
0, //GPIO2
0, //GPIO3
0, //GPIO4
0, //GPIO5
BIT(0), //GPIO0
BIT(1), //GPIO1
BIT(2), //GPIO2
BIT(3), //GPIO3
BIT(4), //GPIO4
BIT(5), //GPIO5
BIT(5), //GPIO6
BIT(6), //GPIO7
BIT(3), //GPIO8

5
components/soc/esp32c3/include/soc/gpio_caps.h
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@@ -26,7 +26,9 @@ extern "C" {
// On ESP32-C3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
#define GPIO_SUPPORTS_RTC_INDEPENDENT (1)
// Force hold is a new function of ESP32-C3
#define GPIO_SUPPORTS_FORCE_HOLD (1)
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// GPIO0~5 on ESP32C3 can support chip deep sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
#define GPIO_MODE_DEF_DISABLE (0)
#define GPIO_MODE_DEF_INPUT (BIT0)
@@ -35,6 +37,7 @@ extern "C" {
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_DEEP_SLEEP_WAKEUP_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
// Support to configure slept status
#define SOC_GPIO_SUPPORT_SLP_SWITCH (1)

3
components/soc/esp32c3/include/soc/rtc_io_caps.h
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@@ -19,6 +19,3 @@
#define SOC_RTCIO_PIN_COUNT 0
#define RTCIO_LL_PIN_FUNC 0
#define SOC_RTCIO_HOLD_SUPPORTED 1
#define SOC_RTCIO_WAKE_SUPPORTED 1