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efuse: Adds WR_DIS.DIS_CACHE for esp32 and WR_DIS.DIS_ICACHE for rest chips
C2 chip does not have such fields
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -10,7 +10,7 @@ extern "C" {
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#include "esp_efuse.h"
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// md5_digest_table 3ac9188bf7eb0a27f3f636085a260743
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// md5_digest_table 10aa3ea5c0748be491a49b2b2d889166
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// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
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// If you want to change some fields, you need to change esp_efuse_table.csv file
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// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
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@@ -20,6 +20,7 @@ extern "C" {
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extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
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extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
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extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_RTC_RAM_BOOT[];
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extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[];
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extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[];
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extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[];
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extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
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