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fix(esp_driver_gptimer): do gptimer retention by timer unit rather than timer group
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@@ -22,10 +22,10 @@ typedef enum periph_retention_module {
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* TEE, APM, UART, IOMUX, SPIMEM, SysTimer, etc.. */
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SLEEP_RETENTION_MODULE_SYS_PERIPH = 3,
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/* Timer Group by target*/
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SLEEP_RETENTION_MODULE_TG0_WDT = 4,
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SLEEP_RETENTION_MODULE_TG0_WDT = 4,
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SLEEP_RETENTION_MODULE_TG1_WDT = 5,
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SLEEP_RETENTION_MODULE_TG0_TIMER = 6,
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SLEEP_RETENTION_MODULE_TG1_TIMER = 7,
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SLEEP_RETENTION_MODULE_TG0_TIMER0 = 6,
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SLEEP_RETENTION_MODULE_TG1_TIMER0 = 7,
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/* GDMA by channel */
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SLEEP_RETENTION_MODULE_GDMA_CH0 = 8,
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SLEEP_RETENTION_MODULE_GDMA_CH1 = 9,
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@@ -54,8 +54,8 @@ typedef enum periph_retention_module_bitmap {
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/* Timer Group by target*/
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SLEEP_RETENTION_MODULE_BM_TASK_WDT = BIT(SLEEP_RETENTION_MODULE_TG0_WDT),
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SLEEP_RETENTION_MODULE_BM_INT_WDT = BIT(SLEEP_RETENTION_MODULE_TG1_WDT),
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SLEEP_RETENTION_MODULE_BM_TG0_TIMER = BIT(SLEEP_RETENTION_MODULE_TG0_TIMER),
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SLEEP_RETENTION_MODULE_BM_TG1_TIMER = BIT(SLEEP_RETENTION_MODULE_TG1_TIMER),
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SLEEP_RETENTION_MODULE_BM_TG0_TIMER0 = BIT(SLEEP_RETENTION_MODULE_TG0_TIMER0),
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SLEEP_RETENTION_MODULE_BM_TG1_TIMER0 = BIT(SLEEP_RETENTION_MODULE_TG1_TIMER0),
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/* GDMA by channel */
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SLEEP_RETENTION_MODULE_BM_GDMA_CH0 = BIT(SLEEP_RETENTION_MODULE_GDMA_CH0),
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SLEEP_RETENTION_MODULE_BM_GDMA_CH1 = BIT(SLEEP_RETENTION_MODULE_GDMA_CH1),
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@@ -76,8 +76,8 @@ typedef enum periph_retention_module_bitmap {
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#define TOP_DOMAIN_PERIPHERALS_BM (SLEEP_RETENTION_MODULE_BM_SYS_PERIPH \
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| SLEEP_RETENTION_MODULE_BM_TASK_WDT \
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| SLEEP_RETENTION_MODULE_BM_INT_WDT \
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| SLEEP_RETENTION_MODULE_BM_TG0_TIMER \
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| SLEEP_RETENTION_MODULE_BM_TG1_TIMER \
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| SLEEP_RETENTION_MODULE_BM_TG0_TIMER0 \
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| SLEEP_RETENTION_MODULE_BM_TG1_TIMER0 \
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| SLEEP_RETENTION_MODULE_BM_GDMA_CH0 \
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| SLEEP_RETENTION_MODULE_BM_GDMA_CH1 \
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| SLEEP_RETENTION_MODULE_BM_GDMA_CH2 \
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@@ -80,13 +80,20 @@ const regdma_entries_config_t tg1_timer_regs_retention[] = {
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[5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x05), TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
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};
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const tg_reg_ctx_link_t tg_wdt_regs_retention[SOC_TIMER_GROUPS] = {
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[0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)},
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[1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)},
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};
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const tg_reg_ctx_link_t tg_timer_regs_retention[SOC_TIMER_GROUPS] = {
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[0] = {tg0_timer_regs_retention, ARRAY_SIZE(tg0_timer_regs_retention)},
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[1] = {tg1_timer_regs_retention, ARRAY_SIZE(tg1_timer_regs_retention)},
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const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS][SOC_TIMER_GROUP_TIMERS_PER_GROUP] = {
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[0] = {
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[0] = {
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.module = SLEEP_RETENTION_MODULE_TG0_TIMER0,
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.regdma_entry_array = tg0_timer_regdma_entries,
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.array_size = ARRAY_SIZE(tg0_timer_regdma_entries)
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}
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},
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[1] = {
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[0] = {
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.module = SLEEP_RETENTION_MODULE_TG1_TIMER0,
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.regdma_entry_array = tg1_timer_regdma_entries,
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.array_size = ARRAY_SIZE(tg1_timer_regdma_entries)
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}
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},
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};
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#endif
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@@ -80,13 +80,20 @@ const regdma_entries_config_t tg1_timer_regs_retention[] = {
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[5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x05), TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
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};
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const tg_reg_ctx_link_t tg_wdt_regs_retention[SOC_TIMER_GROUPS] = {
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[0] = {tg0_wdt_regs_retention, ARRAY_SIZE(tg0_wdt_regs_retention)},
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[1] = {tg1_wdt_regs_retention, ARRAY_SIZE(tg1_wdt_regs_retention)},
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};
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const tg_reg_ctx_link_t tg_timer_regs_retention[SOC_TIMER_GROUPS] = {
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[0] = {tg0_timer_regs_retention, ARRAY_SIZE(tg0_timer_regs_retention)},
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[1] = {tg1_timer_regs_retention, ARRAY_SIZE(tg1_timer_regs_retention)},
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const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS][SOC_TIMER_GROUP_TIMERS_PER_GROUP] = {
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[0] = {
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[0] = {
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.module = SLEEP_RETENTION_MODULE_TG0_TIMER0,
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.regdma_entry_array = tg0_timer_regdma_entries,
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.array_size = ARRAY_SIZE(tg0_timer_regdma_entries)
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}
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},
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[1] = {
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[0] = {
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.module = SLEEP_RETENTION_MODULE_TG1_TIMER0,
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.regdma_entry_array = tg1_timer_regdma_entries,
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.array_size = ARRAY_SIZE(tg1_timer_regdma_entries)
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}
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},
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};
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#endif
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