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fix(uart): LP UART does not have the pre-divider for its clock source

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Closes https://github.com/espressif/esp-idf/issues/15427
This commit is contained in:
Song Ruo Jing
2025-02-24 21:27:41 +08:00
parent 4244d8af54
commit 1b09bb3037
18 changed files with 235 additions and 206 deletions
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14
components/esp_driver_uart/src/uart.c
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@@ -349,20 +349,20 @@ esp_err_t uart_set_baudrate(uart_port_t uart_num, uint32_t baud_rate)
uart_hal_get_sclk(&(uart_context[uart_num].hal), &src_clk);
ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz(src_clk, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq), UART_TAG, "Invalid src_clk");
bool success = false;
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
if (uart_num < SOC_UART_HP_NUM) {
HP_UART_SRC_CLK_ATOMIC() {
uart_hal_set_baudrate(&(uart_context[uart_num].hal), baud_rate, sclk_freq);
success = uart_hal_set_baudrate(&(uart_context[uart_num].hal), baud_rate, sclk_freq);
}
}
#if (SOC_UART_LP_NUM >= 1)
else {
lp_uart_ll_set_baudrate(uart_context[uart_num].hal.dev, baud_rate, sclk_freq);
success = lp_uart_ll_set_baudrate(uart_context[uart_num].hal.dev, baud_rate, sclk_freq);
}
#endif
UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
ESP_RETURN_ON_FALSE(success, ESP_FAIL, UART_TAG, "baud rate unachievable");
return ESP_OK;
}
@@ -911,13 +911,14 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf
uint32_t sclk_freq;
ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz(uart_sclk_sel, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq), UART_TAG, "Invalid src_clk");
bool success = false;
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
uart_hal_init(&(uart_context[uart_num].hal), uart_num);
if (uart_num < SOC_UART_HP_NUM) {
esp_clk_tree_enable_src((soc_module_clk_t)uart_sclk_sel, true);
HP_UART_SRC_CLK_ATOMIC() {
uart_hal_set_sclk(&(uart_context[uart_num].hal), uart_sclk_sel);
uart_hal_set_baudrate(&(uart_context[uart_num].hal), uart_config->baud_rate, sclk_freq);
success = uart_hal_set_baudrate(&(uart_context[uart_num].hal), uart_config->baud_rate, sclk_freq);
}
}
#if (SOC_UART_LP_NUM >= 1)
@@ -925,7 +926,7 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf
LP_UART_SRC_CLK_ATOMIC() {
lp_uart_ll_set_source_clk(uart_context[uart_num].hal.dev, (soc_periph_lp_uart_clk_src_t)uart_sclk_sel);
}
lp_uart_ll_set_baudrate(uart_context[uart_num].hal.dev, uart_config->baud_rate, sclk_freq);
success = lp_uart_ll_set_baudrate(uart_context[uart_num].hal.dev, uart_config->baud_rate, sclk_freq);
}
#endif
uart_hal_set_parity(&(uart_context[uart_num].hal), uart_config->parity);
@@ -936,6 +937,7 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf
UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
uart_hal_rxfifo_rst(&(uart_context[uart_num].hal));
uart_hal_txfifo_rst(&(uart_context[uart_num].hal));
ESP_RETURN_ON_FALSE(success, ESP_FAIL, UART_TAG, "baud rate unachievable");
return ESP_OK;
}