alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-07 20:00:53 +00:00
Code Issues Packages Projects Releases Wiki Activity

fix(uart): LP UART does not have the pre-divider for its clock source

Browse Source 
Closes https://github.com/espressif/esp-idf/issues/15427
This commit is contained in:
Song Ruo Jing
2025-02-24 21:27:41 +08:00
parent 4244d8af54
commit 1b09bb3037
18 changed files with 235 additions and 206 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
components/hal/esp32c3/include/hal/uart_ll.h
View File

@@ -213,23 +213,28 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source
* @param baud The baud rate to be set.
* @param sclk_freq Frequency of the clock source of UART, in Hz.
*
* @return None
* @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved
*/
FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
FORCE_INLINE_ATTR bool uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
{
#define DIV_UP(a, b) (((a) + (b) - 1) / (b))
const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits
if (baud == 0) {
return false;
}
const uint32_t max_div = UART_CLKDIV_V; // UART divider integer part only has 12 bits
uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud);
#undef DIV_UP
if (sclk_div == 0) abort();
if (sclk_div == 0 || sclk_div > (UART_SCLK_DIV_NUM_V + 1)) {
return false; // unachievable baud-rate
}
uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div);
// The baud rate configuration register is divided into
// an integer part and a fractional part.
// The baud rate configuration register is divided into an integer part and a fractional part.
hw->clk_div.div_int = clk_div >> 4;
hw->clk_div.div_frag = clk_div & 0xf;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1);
#undef DIV_UP
return true;
}
/**