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Merge branch 'fix/fix_tg_retention_failure' into 'master'

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fix(esp_driver_gptimer): do gptimer retention by timer unit rather than timer group

Closes PM-233 and IDFCI-2427

See merge request espressif/esp-idf!35284
This commit is contained in:
Wu Zheng Hui
2024-12-02 16:44:05 +08:00
parent 1b7bdcbd6d 3ae1929e58
commit 1b44d4df3b
17 changed files with 315 additions and 225 deletions
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69
components/soc/esp32p4/include/soc/retention_periph_defs.h
View File

@@ -24,39 +24,42 @@ typedef enum periph_retention_module {
/* Timer Group by target*/
SLEEP_RETENTION_MODULE_TG0_WDT = 3,
SLEEP_RETENTION_MODULE_TG1_WDT = 4,
SLEEP_RETENTION_MODULE_TG0_TIMER = 5,
SLEEP_RETENTION_MODULE_TG1_TIMER = 6,
SLEEP_RETENTION_MODULE_TG0_TIMER0 = 5,
SLEEP_RETENTION_MODULE_TG0_TIMER1 = 6,
SLEEP_RETENTION_MODULE_TG1_TIMER0 = 7,
SLEEP_RETENTION_MODULE_TG1_TIMER1 = 8,
/* AHB_DMA by channel */
SLEEP_RETENTION_MODULE_AHB_DMA_CH0 = 7,
SLEEP_RETENTION_MODULE_AHB_DMA_CH1 = 8,
SLEEP_RETENTION_MODULE_AHB_DMA_CH2 = 9,
SLEEP_RETENTION_MODULE_AHB_DMA_CH0 = 9,
SLEEP_RETENTION_MODULE_AHB_DMA_CH1 = 10,
SLEEP_RETENTION_MODULE_AHB_DMA_CH2 = 11,
/* AXI_DMA by channel */
SLEEP_RETENTION_MODULE_AXI_DMA_CH0 = 10,
SLEEP_RETENTION_MODULE_AXI_DMA_CH1 = 11,
SLEEP_RETENTION_MODULE_AXI_DMA_CH2 = 12,
SLEEP_RETENTION_MODULE_AXI_DMA_CH0 = 12,
SLEEP_RETENTION_MODULE_AXI_DMA_CH1 = 13,
SLEEP_RETENTION_MODULE_AXI_DMA_CH2 = 14,
/* MISC Peripherals */
SLEEP_RETENTION_MODULE_UART0 = 13,
SLEEP_RETENTION_MODULE_UART1 = 14,
SLEEP_RETENTION_MODULE_UART2 = 15,
SLEEP_RETENTION_MODULE_UART3 = 16,
SLEEP_RETENTION_MODULE_UART4 = 17,
SLEEP_RETENTION_MODULE_RMT0 = 18,
SLEEP_RETENTION_MODULE_I2S0 = 19,
SLEEP_RETENTION_MODULE_I2S1 = 20,
SLEEP_RETENTION_MODULE_I2S2 = 21,
SLEEP_RETENTION_MODULE_I2C0 = 22,
SLEEP_RETENTION_MODULE_I2C1 = 23,
SLEEP_RETENTION_MODULE_ETM0 = 24,
SLEEP_RETENTION_MODULE_TWAI0 = 25,
SLEEP_RETENTION_MODULE_TWAI1 = 26,
SLEEP_RETENTION_MODULE_TWAI2 = 27,
SLEEP_RETENTION_MODULE_PARLIO0 = 28,
SLEEP_RETENTION_MODULE_GPSPI2 = 29,
SLEEP_RETENTION_MODULE_GPSPI3 = 30,
SLEEP_RETENTION_MODULE_LEDC = 31,
SLEEP_RETENTION_MODULE_MCPWM0 = 32,
SLEEP_RETENTION_MODULE_MCPWM1 = 33,
SLEEP_RETENTION_MODULE_PCNT0 = 34,
SLEEP_RETENTION_MODULE_UART0 = 15,
SLEEP_RETENTION_MODULE_UART1 = 16,
SLEEP_RETENTION_MODULE_UART2 = 17,
SLEEP_RETENTION_MODULE_UART3 = 18,
SLEEP_RETENTION_MODULE_UART4 = 19,
SLEEP_RETENTION_MODULE_RMT0 = 20,
SLEEP_RETENTION_MODULE_I2S0 = 21,
SLEEP_RETENTION_MODULE_I2S1 = 22,
SLEEP_RETENTION_MODULE_I2S2 = 23,
SLEEP_RETENTION_MODULE_I2C0 = 24,
SLEEP_RETENTION_MODULE_I2C1 = 25,
SLEEP_RETENTION_MODULE_ETM0 = 26,
SLEEP_RETENTION_MODULE_TWAI0 = 27,
SLEEP_RETENTION_MODULE_TWAI1 = 28,
SLEEP_RETENTION_MODULE_TWAI2 = 29,
SLEEP_RETENTION_MODULE_PARLIO0 = 30,
SLEEP_RETENTION_MODULE_GPSPI2 = 31,
SLEEP_RETENTION_MODULE_GPSPI3 = 32,
SLEEP_RETENTION_MODULE_LEDC = 33,
SLEEP_RETENTION_MODULE_MCPWM0 = 34,
SLEEP_RETENTION_MODULE_MCPWM1 = 35,
SLEEP_RETENTION_MODULE_PCNT0 = 36,
SLEEP_RETENTION_MODULE_MAX = SOC_PM_RETENTION_MODULE_NUM - 1
} periph_retention_module_t;
@@ -67,8 +70,10 @@ typedef enum periph_retention_module {
: ((m) == SLEEP_RETENTION_MODULE_SYS_PERIPH) ? true \
: ((m) == SLEEP_RETENTION_MODULE_TG0_WDT) ? true \
: ((m) == SLEEP_RETENTION_MODULE_TG1_WDT) ? true \
: ((m) == SLEEP_RETENTION_MODULE_TG0_TIMER) ? true \
: ((m) == SLEEP_RETENTION_MODULE_TG1_TIMER) ? true \
: ((m) == SLEEP_RETENTION_MODULE_TG0_TIMER0) ? true \
: ((m) == SLEEP_RETENTION_MODULE_TG0_TIMER1) ? true \
: ((m) == SLEEP_RETENTION_MODULE_TG1_TIMER0) ? true \
: ((m) == SLEEP_RETENTION_MODULE_TG1_TIMER1) ? true \
: ((m) == SLEEP_RETENTION_MODULE_AHB_DMA_CH0) ? true \
: ((m) == SLEEP_RETENTION_MODULE_AHB_DMA_CH1) ? true \
: ((m) == SLEEP_RETENTION_MODULE_AHB_DMA_CH2) ? true \

209
components/soc/esp32p4/timer_periph.c
View File

@@ -26,141 +26,208 @@ const timer_group_signal_conn_t timer_group_periph_signals = {
};
/* Registers in retention context:
* TIMG_T0CONFIG_REG / TIMG_T1CONFIG_REG
* TIMG_T0ALARMLO_REG / TIMG_T1ALARMLO_REG
* TIMG_T0ALARMHI_REG / TIMG_T1ALARMHI_REG
* TIMG_T0LOADLO_REG / TIMG_T1LOADLO_REG
* TIMG_T0LOADHI_REG / TIMG_T1LOADHI_REG
* TIMG_T0CONFIG_REG
* TIMG_T0ALARMLO_REG
* TIMG_T0ALARMHI_REG
* TIMG_T0LOADLO_REG
* TIMG_T0LOADHI_REG
* TIMG_INT_ENA_TIMERS_REG
* TIMG_REGCLK_REG
*/
#define TG_TIMER_RETENTION_REGS_CNT 12
static const uint32_t tg_timer_regs_map[4] = {0x1001e2f1, 0x80000000, 0x0, 0x0};
#define TG0_TIMER0_RETENTION_REGS_BASE (REG_TIMG_BASE(0))
#define TG1_TIMER0_RETENTION_REGS_BASE (REG_TIMG_BASE(1))
#define TG_TIMER0_RETENTION_REGS_CNT 7
static const uint32_t tg_timer0_regs_map[4] = {0x100000f1, 0x80000000, 0x0, 0x0};
const regdma_entries_config_t tg0_timer_regdma_entries[] = {
/* Registers in retention context:
* TIMG_T1CONFIG_REG
* TIMG_T1ALARMLO_REG
* TIMG_T1ALARMHI_REG
* TIMG_T1LOADLO_REG
* TIMG_T1LOADHI_REG
* TIMG_INT_ENA_TIMERS_REG
* TIMG_REGCLK_REG
*/
#define TG0_TIMER1_RETENTION_REGS_BASE (REG_TIMG_BASE(0) + 0x24)
#define TG1_TIMER1_RETENTION_REGS_BASE (REG_TIMG_BASE(1) + 0x24)
#define TG_TIMER1_RETENTION_REGS_CNT 7
static const uint32_t tg_timer1_regs_map[4] = {0x800f1, 0x400000, 0x0, 0x0};
const regdma_entries_config_t tg0_timer0_regdma_entries[] = {
// backup stage: trigger a soft capture
[0] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00),
TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1),
.owner = ENTRY(0)
},
// backup stage: wait for the capture done
[1] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x01),
.config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x01),
TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1),
.owner = ENTRY(0)
},
// backup stage: save the captured counter value
// restore stage: store the captured counter value to the loader register
[2] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x02),
TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0),
.owner = ENTRY(0)
},
// restore stage: trigger a soft reload, so the timer can continue from where it was backed up
[3] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x03),
TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0),
.owner = ENTRY(0)
},
// backup stage: save other configuration and status registers
// restore stage: restore the configuration and status registers
[4] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x04),
TG0_TIMER0_RETENTION_REGS_BASE, TG0_TIMER0_RETENTION_REGS_BASE,
TG_TIMER0_RETENTION_REGS_CNT, 0, 0,
tg_timer0_regs_map[0], tg_timer0_regs_map[1],
tg_timer0_regs_map[2], tg_timer0_regs_map[3]),
.owner = ENTRY(0)
},
};
const regdma_entries_config_t tg0_timer1_regdma_entries[] = {
// backup stage: trigger a soft capture
[0] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x05),
TIMG_T1UPDATE_REG(0), TIMG_T1_UPDATE, TIMG_T1_UPDATE_M, 0, 1),
.owner = ENTRY(0)
},
// backup stage: wait for the capture done
[2] = {
.config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x02),
TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1),
.owner = ENTRY(0)
},
[3] = {
.config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x03),
[1] = {
.config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x06),
TIMG_T1UPDATE_REG(0), 0x0, TIMG_T1_UPDATE_M, 0, 1),
.owner = ENTRY(0)
},
// backup stage: save the captured counter value
// restore stage: store the captured counter value to the loader register
[4] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x04),
TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0),
.owner = ENTRY(0)
},
[5] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x05),
[2] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x07),
TIMG_T1LO_REG(0), TIMG_T1LOADLO_REG(0), 2, 0, 0),
.owner = ENTRY(0)
},
// restore stage: trigger a soft reload, so the timer can continue from where it was backed up
[6] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x06),
TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0),
.owner = ENTRY(0)
},
[7] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x07),
[3] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x08),
TIMG_T1LOAD_REG(0), 0x1, TIMG_T1_LOAD_M, 1, 0),
.owner = ENTRY(0)
},
// backup stage: save other configuration and status registers
// restore stage: restore the configuration and status registers
[8] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x08),
TIMG_T0CONFIG_REG(0), TIMG_T0CONFIG_REG(0),
TG_TIMER_RETENTION_REGS_CNT, 0, 0,
tg_timer_regs_map[0], tg_timer_regs_map[1],
tg_timer_regs_map[2], tg_timer_regs_map[3]),
[4] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x09),
TG0_TIMER1_RETENTION_REGS_BASE, TG0_TIMER1_RETENTION_REGS_BASE,
TG_TIMER1_RETENTION_REGS_CNT, 0, 0,
tg_timer1_regs_map[0], tg_timer1_regs_map[1],
tg_timer1_regs_map[2], tg_timer1_regs_map[3]),
.owner = ENTRY(0)
},
};
const regdma_entries_config_t tg1_timer_regdma_entries[] = {
const regdma_entries_config_t tg1_timer0_regdma_entries[] = {
// backup stage: trigger a soft capture
[0] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00),
TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1),
.owner = ENTRY(0)
},
// backup stage: wait for the capture done
[1] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x01),
.config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x01),
TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1),
.owner = ENTRY(0)
},
// backup stage: save the captured counter value
// restore stage: store the captured counter value to the loader register
[2] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x02),
TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0),
.owner = ENTRY(0)
},
// restore stage: trigger a soft reload, so the timer can continue from where it was backed up
[3] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x03),
TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0),
.owner = ENTRY(0)
},
// backup stage: save other configuration and status registers
// restore stage: restore the configuration and status registers
[4] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x04),
TG1_TIMER0_RETENTION_REGS_BASE, TG1_TIMER0_RETENTION_REGS_BASE,
TG_TIMER0_RETENTION_REGS_CNT, 0, 0,
tg_timer0_regs_map[0], tg_timer0_regs_map[1],
tg_timer0_regs_map[2], tg_timer0_regs_map[3]),
.owner = ENTRY(0)
},
};
const regdma_entries_config_t tg1_timer1_regdma_entries[] = {
// backup stage: trigger a soft capture
[0] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x05),
TIMG_T1UPDATE_REG(1), TIMG_T1_UPDATE, TIMG_T1_UPDATE_M, 0, 1),
.owner = ENTRY(0)
},
// backup stage: wait for the capture done
[2] = {
.config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x02),
TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1),
.owner = ENTRY(0)
},
[3] = {
.config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x03),
[1] = {
.config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x06),
TIMG_T1UPDATE_REG(1), 0x0, TIMG_T1_UPDATE_M, 0, 1),
.owner = ENTRY(0)
},
// backup stage: save the captured counter value
// restore stage: store the captured counter value to the loader register
[4] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x04),
TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0),
.owner = ENTRY(0)
},
[5] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x05),
[2] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x07),
TIMG_T1LO_REG(1), TIMG_T1LOADLO_REG(1), 2, 0, 0),
.owner = ENTRY(0)
},
// restore stage: trigger a soft reload, so the timer can continue from where it was backed up
[6] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x06),
TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0),
.owner = ENTRY(0)
},
[7] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x07),
[3] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x08),
TIMG_T1LOAD_REG(1), 0x1, TIMG_T1_LOAD_M, 1, 0),
.owner = ENTRY(0)
},
// backup stage: save other configuration and status registers
// restore stage: restore the configuration and status registers
[8] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x08),
TIMG_T0CONFIG_REG(1), TIMG_T0CONFIG_REG(1), TG_TIMER_RETENTION_REGS_CNT, 0, 0,
tg_timer_regs_map[0], tg_timer_regs_map[1],
tg_timer_regs_map[2], tg_timer_regs_map[3]),
[4] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x09),
TG1_TIMER1_RETENTION_REGS_BASE, TG1_TIMER1_RETENTION_REGS_BASE,
TG_TIMER1_RETENTION_REGS_CNT, 0, 0,
tg_timer1_regs_map[0], tg_timer1_regs_map[1],
tg_timer1_regs_map[2], tg_timer1_regs_map[3]),
.owner = ENTRY(0)
},
};
const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS] = {
const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS][SOC_TIMER_GROUP_TIMERS_PER_GROUP] = {
[0] = {
.module = SLEEP_RETENTION_MODULE_TG0_TIMER,
.regdma_entry_array = tg0_timer_regdma_entries,
.array_size = ARRAY_SIZE(tg0_timer_regdma_entries)
[0] = {
.module = SLEEP_RETENTION_MODULE_TG0_TIMER0,
.regdma_entry_array = tg0_timer0_regdma_entries,
.array_size = ARRAY_SIZE(tg0_timer0_regdma_entries)
},
[1] = {
.module = SLEEP_RETENTION_MODULE_TG0_TIMER1,
.regdma_entry_array = tg0_timer1_regdma_entries,
.array_size = ARRAY_SIZE(tg0_timer1_regdma_entries)
},
},
[1] = {
.module = SLEEP_RETENTION_MODULE_TG1_TIMER,
.regdma_entry_array = tg1_timer_regdma_entries,
.array_size = ARRAY_SIZE(tg1_timer_regdma_entries)
[0] = {
.module = SLEEP_RETENTION_MODULE_TG1_TIMER0,
.regdma_entry_array = tg1_timer0_regdma_entries,
.array_size = ARRAY_SIZE(tg1_timer0_regdma_entries)
},
[1] = {
.module = SLEEP_RETENTION_MODULE_TG1_TIMER1,
.regdma_entry_array = tg1_timer1_regdma_entries,
.array_size = ARRAY_SIZE(tg1_timer1_regdma_entries)
},
},
};

24
components/soc/esp32p4/wdt_periph.c
View File

@@ -9,21 +9,21 @@
#define N_REGS_TGWDT 6 // TIMG_WDTCONFIG0_REG ... TIMG_WDTCONFIG5_REG & TIMG_INT_ENA_TIMERS_REG
static const regdma_entries_config_t tg0_wdt_regs_retention[] = {
[0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_INT_ENA_TIMERS_REG(0), TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(0), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0)},
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x01), TIMG_WDTCONFIG0_REG(0), TIMG_WDTCONFIG0_REG(0), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0)},
[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(0), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0)},
[3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x03), TIMG_WDTFEED_REG(0), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0)},
[4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_INT_ENA_TIMERS_REG(0), TIMG_INT_ENA_TIMERS_REG(0), 1, 0, 0), .owner = ENTRY(0)},
[5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(0), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0)},
};
static const regdma_entries_config_t tg1_wdt_regs_retention[] = {
[0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_INT_ENA_TIMERS_REG(1), TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0) | ENTRY(2) },
[3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) },
[0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x00), TIMG_WDTWPROTECT_REG(1), TIMG_WDT_WKEY_VALUE, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0)},
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x01), TIMG_INT_ENA_TIMERS_REG(1), TIMG_INT_ENA_TIMERS_REG(1), 1, 0, 0), .owner = ENTRY(0)},
[2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_WDT_LINK(0x02), TIMG_WDTCONFIG0_REG(1), TIMG_WDTCONFIG0_REG(1), N_REGS_TGWDT, 0, 0), .owner = ENTRY(0)},
[3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x03), TIMG_WDTCONFIG0_REG(1), TIMG_WDT_CONF_UPDATE_EN, TIMG_WDT_CONF_UPDATE_EN_M, 1, 0), .owner = ENTRY(0)},
[4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_WDT_LINK(0x04), TIMG_WDTFEED_REG(1), TIMG_WDT_FEED, TIMG_WDT_FEED_M, 1, 0), .owner = ENTRY(0)},
[5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_WDT_LINK(0x05), TIMG_WDTWPROTECT_REG(1), 0, TIMG_WDT_WKEY_M, 1, 0), .owner = ENTRY(0)},
};
const tg_reg_ctx_link_t tg_wdt_regs_retention[SOC_TIMER_GROUPS] = {